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| 1 8266c-mcu wireless-08/11 ATMEGA128RFA1 8-bit microcontroller with low power 2.4ghz transceiver for zigbee and ieee 802.15.4 ATMEGA128RFA1 preliminary 8266c-mcu wireless-08/11 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture - 135 powerful instructions ? most single clock cycle execution - 32x8 general purpose working registers - fully static operation - up to 16 mips throughput at 16 mhz and 1.8v - on-chip 2-cycle multiplier ? non-volatile program and data memories - 128k bytes of in-system self-programmable flash ? endurance: 1000 write/erase cycles @ 125c (2000 cy cles @ 85c) - 4k bytes eeprom ? endurance: 1000 write/erase cycles @ 125c (2000 cy cles @ 85c) - 16k bytes internal sram ? jtag (ieee std. 1149.1 compliant) interface - boundary-scan capabilities according to the jtag st andard - extensive on-chip debug support - programming of flash eeprom, fuses and lock bits th rough the jtag interface ? peripheral features - multiple timer/counter & pwm channels - real time counter with separate oscillator - 10-bit, 330 ks/s a/d converter; analog comparator; on-chip temperature sensor - master/slave spi serial interface - two programmable serial usart - byte oriented 2-wire serial interface ? advanced interrupt handler ? watchdog timer with separate on-chip oscillator ? power-on reset and low current brown-out detector ? advanced power save modes ? fully integrated low power transceiver for 2.4 ghz ism band - supported data rates: 250 kb/s and 500 kb/s, 1 mb/s , 2 mb/s - -100 dbm rx sensitivity; tx output power up to 3.5 dbm - hardware assisted mac (auto-acknowledge, auto-retry ) - 32 bit ieee 802.15.4 symbol counter - baseband signal processing - sfr-detection, spreading; de-spreading; framing ; c rc-16 computation - antenna diversity and tx/rx control - tx/rx 128 byte frame buffer ? hardware security (aes, true random generator) ? integrated crystal oscillators (32.768 khz & 16 mhz , external crystal needed) ? i/o and package - 38 programmable i/o lines - 64-pad qfn (rohs/fully green) ? temperature range: -40c to 125c industrial ? supply voltage range 1.8v to 3.6v with integrated v oltage regulators ? ultra low power consumption (1.8 to 3.6v) for rx/tx & avr: <18.6 ma - cpu active mode (16mhz): 4.1 ma - 2.4ghz transceiver: rx_on 12.5 ma / tx 14.5 ma (max imum tx output power) - deep sleep mode: <250na @ 25c ? speed grade: 0 ? 16 mhz @ 1.8 ? 3.6v applications ? zigbee ? / ieee 802.15.4-2006/2003 ? ? full and reduced function device (ffd/rfd) ? general purpose 2.4ghz ism band transceiver with mi crocontroller ? rf4ce, sp100, wirelesshart ? , ism applications and ipv6 / 6lowpan
2 8266c-mcu wireless-08/11 ATMEGA128RFA1 1 pin configurations figure 1-1. pinout ATMEGA128RFA1 note: the large center pad underneath the qfn/mlf package is made of metal and internally connected to av ss. it should be soldered or glued to the board to ensure good mechanical stability. if the center pad is left unconnected, the package might l oosen from the board 2 disclaimer typical values contained in this datasheet are base d on simulation and characterization results of other avr microcontrollers and radio tra nsceivers manufactured in a similar process technology. minimum and maximum values will be available after the device is characterized. 1 [pf3:adc3:dig4] [pf2:adc2:dig2] 2 3 [pf5:adc5:tms] [pf4:adc4:tck] 4 5 [pf7:adc7:tdi] [pf6:adc6:tdo] 6 7 [rfp] [avss_rfp] 8 9 [avss_rfn] [rfn] 10 11 [rstn] [tst] 12 13 14 [rston] [pg0:dig3] 56 55 54 53 52 51 62 61 60 59 58 57 64 63 ATMEGA128RFA1 exposed paddle: [avss] [dvss] [pe0:rxd0:pcint8] [pe1:txd0] [pe2:xck0:ain0] [clki] [devdd] [dvss] [pb0:ssn:pcint0] [pb1:sck:pcint1] [pb2:mosi:pdi:pcint2] [pb3:miso:pdo:pcint3] [pb4:oc2a:pcint4] [pb5:oc1a:pcint5] [pb6:oc1b:pcint6] 31 32 17 18 19 20 21 23 22 24 25 26 27 0 28 [pd3:txd1:int3] [pd2:rxd1:int2] [pd1:sda:int1] [pd0:scl:int0] [dvss] [devdd] [dvdd] [dvdd] [dvss:dsvss] [pg5:oc0b] [pg4:tosc1] [pg3:tosc2] [pd7:t0] [pd6:t1] 42 41 40 39 38 37 36 35 34 33 48 47 46 45 15 16 [pg1:dig1] [pg2:amr] [pb7:oc0a:oc1c:pcint7] [devdd] 44 43 29 0 30 [pd5:xck1] [pd4:icp1] 50 49 index corner [devdd] [pe7:icp3:int7:clko] [pe6:t3:int6] [pe5:oc3c:int5] [pe4:oc3b:int4] [pe3:oc3a:ain1] [xtal2] [dvss] [pf1:adc1] [pf0:adc0] [aref] [avss] [avdd] [evdd] [avss:asvss] [xtal1] 3 8266c-mcu wireless-08/11 ATMEGA128RFA1 3 overview the ATMEGA128RFA1 is a low-power cmos 8-bit microco ntroller based on the avr enhanced risc architecture combined with a high dat a rate transceiver for the 2.4 ghz ism band. it is derived from the atmega1281 microco ntroller and the at86rf231 radio transceiver. by executing powerful instructions in a single cloc k cycle, the device achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. the radio transceiver provides high data rates from 250 kb/s up to 2 mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication. 3.1 block diagram figure 3-1 block diagram the avr core combines a rich instruction set with 3 2 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu). two independent registers can be accessed with one sing le instruction executed in one clock cycle. the resulting architecture is very cod e efficient while achieving throughputs up to ten times faster than conventional cisc micro controllers. the system includes internal voltage regulation and an advanced power m anagement. distinguished by the small leakage current it allows an extended operati on time from battery. the radio transceiver is a fully integrated zigbee solution using a minimum number of external components. it combines excellent rf perfo rmance with low cost, small size and low current consumption. the radio transceiver includes a crystal stabilized fractional-n synthesizer, transmitter and receiver, and full direct sequence spread 4 8266c-mcu wireless-08/11 ATMEGA128RFA1 spectrum signal (dsss) processing with spreading an d despreading. the device is fully compatible with ieee802.15.4-2006/2003 and zi gbee standards. the ATMEGA128RFA1 provides the following features: 128k bytes of in-system programmable (isp) flash with read-while-write capa bilities, 4k bytes eeprom, 16k bytes sram, up to 35 general purpose i/o lines, 32 general purpose working registers, real time counter (rtc), 6 flexible timer/counters with compare modes and pwm, usart, a byte oriented 2-wire serial interface, a 8 channel, 10 bit analog to digital converter (adc) with an optional differential input stage with programmable gain, programmable watchdog timer with internal oscillato r, a spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming and 6 software selectable po wer saving modes. the idle mode stops the cpu while allowing the sram , timer/counters, spi port, and interrupt system to continue functioning. the power -down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, th e asynchronous timer continues to run, allowing the user to maintain a timer base whi le the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching n oise during adc conversions. in standby mode, the rc oscillator is running while th e rest of the device is sleeping. this allows very fast start-up combined with low power c onsumption. in extended standby mode, both the main rc oscillator and the asynchron ous timer continue to run. typical supply current of the microcontroller with cpu clock set to 16mhz and the radio transceiver for the most important states is shown in the figure 3-2 below . figure 3-2 radio transceiver and microcontroller (16mhz) supp ly current 16,6ma 4,7ma 4,1ma 250na 18,6ma 0 5 10 15 20 deep sleep sleep trx_off rx_listen tx_act radio transceiver state i(devdd,evdd) [ma] 1.8v 3.0v 3.6v the transmit output power is set to maximum. if the radio transceiver is in sleep mode the current is dissipated by the avr microcontrolle r only. in deep sleep mode all major digital blocks with no data retention requirements are disconnected from main supply providing a very smal l leakage current. watchdog timer, mac symbol counter and 32.768khz oscillator can be configured to continue to run. the device is manufactured using atmel?s high-densi ty nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system 5 8266c-mcu wireless-08/11 ATMEGA128RFA1 trough an spi serial interface, by a conventional n onvolatile memory programmer, or by on on-chip boot program running on the avr core. th e boot program can use any interface to download the application program in th e application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8 bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel ATMEGA128RFA1 is a powerful microcontroller that pr ovides a highly flexible and cost effective solution to many embedded control applica tions. the ATMEGA128RFA1 avr is supported with a full suit e of program and system development tools including: c compiler, macro asse mblers, program debugger/simulators, in-circuit emulators, and eval uation kits. 3.2 pin descriptions 3.2.1 evdd external analog supply voltage. 3.2.2 devdd external digital supply voltage. 3.2.3 avdd regulated analog supply voltage (internally generat ed). 3.2.4 dvdd regulated digital supply voltage (internally genera ted). 3.2.5 dvss digital ground. 3.2.6 avss analog ground. 3.2.7 port b (pb7...pb0) port b is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port b output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also provides functions of various special f eatures of the ATMEGA128RFA1. 3.2.8 port d (pd7...pd0) port d is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port d output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also provides functions of various special f eatures of the ATMEGA128RFA1. 3.2.9 port e (pe7...pe0) port e is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port e output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also provides functions of various special f eatures of the ATMEGA128RFA1. 6 8266c-mcu wireless-08/11 ATMEGA128RFA1 3.2.10 port f (pf7...pf0) port f is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port f output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. port f also provides functions of various special f eatures of the ATMEGA128RFA1. 3.2.11 port g (pg5?pg0) port g is a 6-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port g output buffers have symmetrical dr ive characteristics with both high sink and source capability. however the driver stre ngth of pg3 and pg4 is reduced compared to the other port pins. the output voltage drop (v oh , v ol ) is higher while the leakage current is smaller. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activat ed. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also provides functions of various special f eatures of the ATMEGA128RFA1. 3.2.12 avss_rfp avss_rfp is a dedicated ground pin for the bi-direc tional, differential rf i/o port. 3.2.13 avss_rfn avss_rfn is a dedicated ground pin for the bi-direc tional, differential rf i/o port. 3.2.14 rfp rfp is the positive terminal for the bi-directional , differential rf i/o port. 3.2.15 rfn rfn is the negative terminal for the bi-directional , differential rf i/o port. 3.2.16 rstn reset input. a low level on this pin for longer tha n the minimum pulse length will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. 3.2.17 rston reset output. a low level on this pin indicates a r eset initiated by the internal reset sources or the pin rstn. 3.2.18 xtal1 input to the inverting 16mhz crystal oscillator amp lifier. in general a crystal between xtal1 and xtal2 provides the 16mhz reference clock of the radio transceiver. 3.2.19 xtal2 output of the inverting 16mhz crystal oscillator am plifier. 3.2.20 aref reference voltage output of the a/d converter. in g eneral this pin is left open. 3.2.21 tst programming and test mode enable pin. if pin tst is not used pull it to low. 3.2.22 clki input to the clock system. if selected, it provides the operating clock of the microcontroller. 3.3 unused pins floating pins can cause power dissipation in the di gital input stage. they should be connected to an appropriate source. in normal opera tion modes the internal pull-up 7 8266c-mcu wireless-08/11 ATMEGA128RFA1 resistors can be enabled (in reset all gpio are con figured as input and the pull-up resistors are still not enabled). bi-directional i/o pins shall not be connected to g round or power supply directly. the digital input pins tst and clki must be connect ed. if unused pin tst can be connected to avss while clki should be connected to dvss. output pins are driven by the device and do not flo at. power supply pins respective ground supply pins are connected together internall y. xtal1 and xtal2 shall never be forced to supply vol tage at the same time. 3.4 compatibility to atmega1281/2561 the basic avr feature set of the ATMEGA128RFA1 is d erived from the atmega1281/2561. address locations and names of the implemented modules and registers are unchanged as long as it fits the targ et application of a very small and power efficient radio system. in addition, several new features were added. backward compatibility of the ATMEGA128RFA1 to the atmega1281/2561 is provided in most cases. however some incompatibilities betwe en the microcontrollers exist. 3.4.1 port a and port c port a and port c are not implemented. the associat ed registers are available but will not provide any port control. remaining ports are k ept at their original address location to not require changes of existing software package s. 3.4.2 external memory interface the alternate pin function ?external memory interfa ce? using port a and port c is not implemented due to the missing ports. the large internal data memory (sram) does not requ ire an external memory and the associated parallel interface. it keeps the system radiation (emc) at a very small level to provide very high sensitivity at the antenna inp ut. 3.4.3 high voltage programming mode alternate pin function bs2 (high voltage programmin g) of pin pa0 is mapped to a different pin. entering the parallel programming mo de is controlled by the tst pin. 3.4.4 avr oscillators and external clock the avr microcontroller can utilize the high perfor mance crystal oscillator of the 2.4ghz transceiver connected to the pins xtal1 and xtal2. an external clock can be applied to the microcontroller using the clock inpu t clki. 3.4.5 analog frontend the ATMEGA128RFA1 has a new a/d converter. software compatibility is basically assured. nevertheless to benefit from the higher co nversion speeds and the better performance some changes are required. 4 resources a comprehensive set of development tools and applic ation notes, and datasheets are available for download on http://www.atmel.com . 8 8266c-mcu wireless-08/11 ATMEGA128RFA1 5 about code examples this documentation contains simple code examples th at briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handl ing in c is compiler dependent. please confirm with the c compiler documentation for more details. these code examples assume that the part specific h eader file is included before compilation. for i/o registers located in extended i/o map, "in", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined wi th "sbrs", "sbrc", "sbr", and "cbr". 6 data retention and endurance 6.1 data retention the data retention of the non-volatile memories is ? over 10 years at 125c 6.2 endurance of the code memory (flash) the endurance of the code memory (flash) is ? 125c ? 1,000 write/erase cycles ? 85c ? 2,000 write/erase cycles 6.3 endurance of the data memory (eeprom) the endurance of the entire data memory (eeprom) is ? 125c ? 1,000 write/erase cycles ? 85c ? 2,000 write/erase cycles ? 25c ? 5,000 write/erase cycles 9 8266c-mcu wireless-08/11 ATMEGA128RFA1 7 avr cpu core 7.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. th e cpu must therefore be able to access memories, perform calculation, control perip herals, and handle interrupts. 7.2 architectural overview figure 7-1 .block diagram of the avr architecture flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n in order to maximize performance and parallelism, t he avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in ever y clock cycle. the program memory is in-system reprogrammable flash memory. 10 8266c-mcu wireless-08/11 ATMEGA128RFA1 the fast-access register file contains 32 x 8-bit g eneral purpose working registers with a single clock cycle access time. this allows singl e-cycle arithmetic logic unit (alu) operation. in a typical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-b it x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations be tween registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncondi tional jump and call instructions, able to directly address the whole address space. m ost avr instructions have a single 16-bit word format. every program memory address co ntains a 16- or 32-bit instruction. program flash memory space is divided in two sectio ns, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that wri tes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively alloc ated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in t he reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all l inear and regular memory maps. a flexible interrupt module has its control registe rs in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o me mory can be accessed directly, or as the data space locations following those of the reg ister file, 0x20 - 0x5f. in addition, the ATMEGA128RFA1 has extended i/o space from 0x60 - 0x1ff in sram where only the st/sts/std and ld/lds/ldd instructions can be u sed. 7.3 alu ? arithmetic logic unit the high-performance avr alu operates in direct con nection with all the 32 general purpose working registers. within a single clock cy cle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categori es ? arithmetic, logical, and bit functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed descriptio n. 11 8266c-mcu wireless-08/11 ATMEGA128RFA1 7.4 status register the status register contains information about the result of the most recently executed arithmetic instruction. this information can be use d for altering program flow in order to perform conditional operations. note that the statu s register is updated after all alu operations, as specified in the instruction set ref erence. this will in many cases remove the need for using the dedicated compare ins tructions, resulting in faster and more compact code. the status register is not autom atically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 7.4.1 sreg ? status register bit 7 6 5 4 3 2 1 0 $3f ($5f) i t h s v n z c sreg read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? i - global interrupt enable the global interrupt enable bit must be set (one) f or the interrupts to be enabled. the individual interrupt enable control is then perform ed in separate control registers. if the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable sett ings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. ? bit 6 ? t - bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t bit as source and destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h - half carry flag the half carry flag h indicates a half carry in som e arithmetic operations. see the instruction set description for detailed informatio n. ? bit 4 ? s - sign bit the s-bit is always an exclusive or between the neg ative flag n and the two's complement overflow flag v. see the instruction set description for detailed information. ? bit 3 ? v - two's complement overflow flag the two's complement overflow flag v supports two's complement arithmetics. see the instruction set description for detailed informatio n. ? bit 2 ? n - negative flag the negative flag n indicates a negative result aft er the different arithmetic and logic operations. see the instruction set description for detailed information. ? bit 1 ? z - zero flag the zero flag z indicates a zero result after the d ifferent arithmetic and logic operations. see the instruction set description for detailed in formation. ? bit 0 ? c - carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for detailed information. note that the status register is not automatically 12 8266c-mcu wireless-08/11 ATMEGA128RFA1 stored when entering an interrupt routine and resto red when returning from an interrupt routine. this must be handled by software. 7.5 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required performance and flexibility, t he following input/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result inpu t ? two 8-bit output operands and one 8-bit result inp ut ? two 8-bit output operands and one 16-bit result in put ? one 16-bit output operand and one 16-bit result in put figure 7-1 below shows the structure of the 32 general purpose work ing registers in the cpu. figure 7-1. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instru ctions. as shown in figure 7-1 above on page 12, each register is also assigned a data memory address, mapping them directly into the firs t 32 locations of the user data space. although not being physically implemented as sram locations, this memory organization provides great flexibility in access o f the registers, as the x-, y- and z- pointer registers can be set to index any register in the file. 7.5.1 the x-register, y-register, and z-register the registers r26...r31 have some added functions t o their general purpose usage. these registers are 16-bit address pointers for ind irect addressing of the data space. the three indirect address registers x, y, and z ar e defined as described in figure 7-2 on page 13. 13 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 7-2. the x-, y-, z-registers in the different addressing modes these address reg isters have functions as fixed displacement, automatic increment, and automatic de crement (see the instruction set reference for details). 7.6 stack pointer the stack is mainly used for storing temporary data , for storing local variables and for storing return addresses after interrupts and subro utine calls. the stack pointer register always points to the top of the stack. not e that the stack is implemented as growing from higher memory locations to lower memor y locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack are a where the subroutine and interrupt stacks are located. this stack space in t he data sram must be defined by the program before any subroutine calls are execute d or interrupts are enabled. the stack pointer must be set to point above 0x0200. th e initial value of the stack pointer is the last address of the internal sram. the stack pointer is decremented by one when data i s pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the st ack pointer is incremented by one when data is popped from the stack with the pop ins truction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. when the flash memory exceeds 128kbyte one addition al cycle is required. in this case the stack pointer is decremented by three when the return address is pushed onto the stack with subroutine call or interrupt and is incremented by three when data is popped from the stack with return from subroutine r et or return from interrupt reti. 7.6.1 sph ? stack pointer high bit 7 6 5 4 3 2 1 0 $3e ($5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph read/write rw rw rw rw rw rw rw rw initial value 0 0 1 0 0 0 0 1 the avr stack pointer is implemented as two 8-bit r egisters spl and sph in the i/o space. the number of bits actually used is implemen tation dependent. note that the data space in some implementations of the avr archi tecture is so small that only spl is needed. in this case, the sph register will not be present. ? bit 7:0 ? sp15:8 - stack pointer high byte 14 8266c-mcu wireless-08/11 ATMEGA128RFA1 7.6.2 spl ? stack pointer low bit 7 6 5 4 3 2 1 0 $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 the avr stack pointer is implemented as two 8-bit r egisters spl and sph in the i/o space. the number of bits actually used is implemen tation dependent. note that the data space in some implementations of the avr archi tecture is so small that only spl is needed. in this case, the sph register will not be present. ? bit 7:0 ? sp7:0 - stack pointer low byte 7.6.3 rampz ? extended z-pointer register for elpm/ spm bit 7 6 5 4 3 2 1 0 $3b ($5b) res5 res4 res3 res2 res1 res0 rampz1 rampz0 rampz read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 for elpm/spm instructions, the z-pointer is a conca tenation of rampz, zh, and zl. note that lpm is not affected by the rampz setting. ? bit 7:2 ? res5:0 - reserved for compatibility with future devices, be sure to w rite these bits to zero. ? bit 1:0 ? rampz1:0 - extended z-pointer value these two bits represent the msb's of the z-pointer . table 7-2 rampz register bits register bits value description rampz1:0 0 default value of z-pointer msb's. for elpm/spm instructions, the z-pointer is a conca tenation of rampz, zh, and zl, as shown in figure 7-3 below . note that lpm is not affected by the rampz settin g. figure 7-3. the z-pointer used by elpm and spm the actual number of bits is implementation depende nt. unused bits in an implementation will always read as zero. for compat ibility with future devices, be sure to write these bits to zero. 15 8266c-mcu wireless-08/11 ATMEGA128RFA1 7.7 instruction execution timing figure 7-4. the parallel instruction fetches and instruction e xecutions clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu figure 7-5 below shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register ope rands is executed, and the result is stored back to the destination register. figure 7-5. single cycle alu operation total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 7.8 reset and interrupt handling the avr provides several different interrupt source s. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits whic h must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are pro grammed. this feature improves software security. see the section "memory programming" on page 465 for details. the lowest addresses in the program memory space ar e by default defined as the reset and interrupt vectors. the complete list of v ectors is shown in "interrupts" on page 212 . the list also determines the priority levels of t he different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. th e interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcucr). refer to "interrupts" on page 212 for more information. the reset vector can also be moved to the start of the boot flash se ction by programming the bootrst fuse, see "memory programming" on page 465 . when an interrupt occurs, the global interrupt enab le i-bit is cleared and all interrupts are disabled. the user software can write logic one to the i-bit to enable nested 16 8266c-mcu wireless-08/11 ATMEGA128RFA1 interrupts. all enabled interrupts can then interru pt the current interrupt routine. the i-bit is automatically set when a return from interrupt i nstruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the int errupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared . if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the f lag is cleared by software. similarly, if one or more interrupt conditions occur while the gl obal interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be execu ted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the int errupt will not be triggered. when the avr exits from an interrupt, it will alway s return to the main program and execute one more instruction before any pending int errupt is served. note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interr upt routine. this must be handled by software. when using the cli instruction to disable interrupt s, the interrupts will be immediately disabled. no interrupt will be executed after the c li instruction, even if it occurs simultaneously with the cli instruction. the follow ing example shows how this can be used to avoid interrupts during the timed eeprom wr ite sequence. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 18 8266c-mcu wireless-08/11 ATMEGA128RFA1 8 avr memories this section describes the different memories in th e ATMEGA128RFA1. the avr architecture has two main memory spaces, the data m emory and the program memory space. in addition, the ATMEGA128RFA1 features an e eprom memory for data storage. all three memory spaces are linear and reg ular. 8.1 in-system reprogrammable flash program memory the ATMEGA128RFA1 contains 128k bytes on-chip in-sy stem reprogrammable flash memory for program storage, see figure 8-6 below . since all avr instructions are 16 or 32 bits wide, the flash is 16 bit wide. for softwar e security, the flash program memory space is divided into two sections, boot program se ction and application program section. the flash memory has an endurance of at least 2000 write/erase cycles. the ATMEGA128RFA1 program counter (pc) is 16 bits wide, thus addressing the required program memory locations. the operation of boot pro gram section and associated boot lock bits for software protection are describe d in detail in "boot loader support ? read-while-write self-programming" on page 451 . "memory programming" on page 465 contains a detailed description on flash data seri al downloading using the spi pins or the jtag interface. constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory instruction descripti on and elpm ? extended load program memory instruction description). timing diagrams for instruction fetch and execution are presented in "instruction execution timing" on page 15 . figure 8-6. program flash memory map boot flash section program memory application flash section $0000 8.2 sram data memory figure 8-7 on page 19 shows how the ATMEGA128RFA1 sram memory is organized. the ATMEGA128RFA1 is a complex microcontroller wit h more peripheral units than can be supported within the 64 location reserved in the opcode for the in and out instructions. for the extended i/o space from $060 ? $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the first data memory locations address both the re gister file, the i/o memory, extended i/o memory, and the internal data sram. th e first 32 locations address the register file, the next 64 location the standard i/ o memory, then 416 locations of extended i/o memory and the following locations add ress the internal data sram. 19 8266c-mcu wireless-08/11 ATMEGA128RFA1 the five different addressing modes for the data me mory cover: direct, indirect with displacement, indirect, indirect with pre-decrement , and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space . the indirect with displacement mode reaches 63 addr ess locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are de cremented or incremented. the 32 general purpose working registers, 64 i/o re gisters, and the internal data sram in the ATMEGA128RFA1 are all accessible through all these addressing modes. the register file is described in "general purpose register file" on page 12 . figure 8-7. data memory map 32 registers 64 i/o registers internal sram (16k x 8) $0000 - $001f $0020 - $005f $41ff $ffff $0060 - $01ff data memory 416 ext i/o reg. $0200 8.2.1 data memory access times this section describes the general access timing co ncepts for internal memory access. access to the internal data sram is performed in tw o clk cpu cycles as described in figure 8-8 on page 20. 20 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 8-8. on-chip data sram access cycles clk wr rd datadata address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 8.3 eeprom data memory the ATMEGA128RFA1 contains 4k kbytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the access between the eeprom and the cpu is described in the following, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi, jtag and paralle l data downloading to the eeprom, see "serial downloading" on page 479 , "programming via the jtag interface" on page 483 , and "programming the eeprom" on page 493 respectively. 8.3.1 eeprom read write access the eeprom access registers are accessible in the i /o space, see "eeprom register description" on page 24. the write access time for the eeprom is given in table 8-3 below . a self-timing function, however, lets the user software detect wh en the next byte can be written. if the user code contains instructions that write the eepr om, some precautions must be taken. in heavily filtered power supplies, dvdd is likely to rise or fall slowly on power- up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see "preventing eeprom corruption" on page 24 for details on how to avoid problems in th ese situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. see the description of the eeprom control register for details on this, "eeprom register description" on page 24. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. when the eeprom is written , the cpu is halted for two clock cycles before the next instruction is executed. the calibrated oscillator is used to time the eepro m accesses. the following table lists the typical programming time for eeprom acces s from the cpu. table 8-3. eeprom programming time symbol typical programming time eeprom write (from cpu) 4.5 ms eeprom erase (from cpu) 8.5 ms 21 8266c-mcu wireless-08/11 ATMEGA128RFA1 the following code examples show assembly and c fun ctions for programming the eeprom with separate and combined (atomic) erase/wr ite operations respectively. the examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during e xecution of these functions. the examples also assume that no flash boot loader is p resent in the software. if such code is present, the eeprom write function must als o wait for any ongoing spm command to finish. assembly code example eeprom_write: ; wait for completion of previous erase/write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write is controlled with r20 and r21 ldi r20, (1< 25 8266c-mcu wireless-08/11 ATMEGA128RFA1 8.4.3 eedr ? eeprom data register bit 7 6 5 4 3 2 1 0 $20 ($40) eedr7:0 eedr read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 for the eeprom write operation, the eedr register c ontains the data to be written to the eeprom in the address given by the eear registe r. for the eeprom read operation, the eedr contains the data read out from the eeprom at the address given by eear. ? bit 7:0 ? eedr7:0 - eeprom data 8.4.4 eecr ? eeprom control register bit 7 6 5 4 3 2 1 0 $1f ($3f) res1 res0 eepm1 eepm0 eerie eempe eepe eere eecr read/write r r rw rw rw rw rw rw initial value 0 0 x x 0 0 x 0 ? bit 7:6 ? res1:0 - reserved ? bit 5:4 ? eepm1:0 - eeprom programming mode the eeprom programming mode bit setting defines whi ch programming action will be triggered when writing eepe. it is possible to prog ram data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. while eepe is set, any write to eepm1:0 will be ignored. during reset, the eepm1:0 bits will be res et to 0 unless the eeprom is busy programming. table 8-4 eepm register bits register bits value description 0x00 erase and write in one operation (atomic operation) 0x01 erase only 0x02 write only eepm1:0 0x03 reserved for future use ? bit 3 ? eerie - eeprom ready interrupt enable writing eerie to one enables the eeprom ready inter rupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the e eprom ready interrupt generates a constant interrupt when eepe is cleared. ? bit 2 ? eempe - eeprom master write enable the eempe bit determines whether setting eepe to on e causes the eeprom to be written. when eempe is set, setting eepe within fou r clock cycles will write data to the eeprom at the selected address if eempe is zero, se tting eepe will have no effect. when eempe has been written to one by software, har dware clears the bit to zero after four clock cycles. see the description of the eepe bit for an eeprom write procedure. ? bit 1 ? eepe - eeprom programming enable 26 8266c-mcu wireless-08/11 ATMEGA128RFA1 the eeprom write enable signal eepe is the write st robe to the eeprom. when address and data are correctly set up, the eepe bit must be written to one to write the value into the eeprom. the eempe bit must be writte n to one before a logical one is written to eepe, otherwise no eeprom write takes pl ace. the following procedure should be adopted when writing the eeprom (the orde r of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until spmen in spmcsr becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writi ng a zero to eepe in eecr. 6. within four clock cycles after setting eempe, wr ite a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is c ompleted before initiating a new eeprom write. step 2 is only relevant if the softwa re contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. caution: an interrupt between step 5 and step 6 wil l make the write cycle fail, since the eeprom master write enable will time-out. if an int errupt routine accessing the eeprom is interrupting another eeprom access, the e ear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all steps to avoid these problems. when the write access time has elapsed, the eepe bi t is cleared by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere - eeprom read enable the eeprom read enable signal eere is the read stro be to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read acc ess takes one instruction and the requested data is available immediately. when t he eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a w rite operation is in progress, it is neither possible to read the eeprom nor to change t he eear register. 8.5 i/o memory the input/output (i/o) space definition of the atme ga128rfa1 is shown in "register summary" on page 498 . all ATMEGA128RFA1 i/os and peripherals are placed i n the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std in structions, transferring data between the 32 general purpose working registers an d the i/o space. i/o registers within the address range 0x00 ? 0x1f are directly b it-accessible using the sbi and cbi instructions. in these registers, the value of sing le bits can be checked by using the sbis and sbic instructions. refer to the avr instru ction set for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 ? 0x3f must be used. when addressing i/o registers as data space u sing ld and st instructions, 27 8266c-mcu wireless-08/11 ATMEGA128RFA1 0x20 must be added to these addresses. the atmega12 8rfa1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 ? 0x1ff in sram, only the st/sts/std and ld/ld s/ldd instructions can be used. for compatibility with future devices, reserved bit s may not be modified. reserved registers and i/o memory addresses should never be written. some of the status flags are cleared by writing a l ogical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing s uch status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the control registers of i/o and peripherals are ex plained in later sections. 8.6 general purpose i/o registers the ATMEGA128RFA1 contains three general purpose i/ o registers. these registers can be used for storing any information, and they a re particularly useful for storing global variables and status flags. general purpose i/o registers within the address range 0x00 ? 0x1f are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 8.6.1 gpior0 ? general purpose io register 0 bit 7 6 5 4 3 2 1 0 $1e ($3e) gpior07:00 gpior0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the three general purpose i/o registers can be used for storing any information. ? bit 7:0 ? gpior07:00 - general purpose i/o register 0 value 8.6.2 gpior1 ? general purpose io register 1 bit 7 6 5 4 3 2 1 0 $2a ($4a) gpior17:10 gpior1 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the three general purpose i/o registers can be used for storing any information. ? bit 7:0 ? gpior17:10 - general purpose i/o register 1 value 8.6.3 gpior2 ? general purpose i/o register 2 bit 7 6 5 4 3 2 1 0 $2b ($4b) gpior27:20 gpior2 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 28 8266c-mcu wireless-08/11 ATMEGA128RFA1 the three general purpose i/o registers can be used for storing any information. ? bit 7:0 ? gpior27:20 - general purpose i/o register 2 value 8.7 other port registers the inherited control registers of missing ports lo cated in the i/o space are kept in the ATMEGA128RFA1. they can be used as general purpose i/o registers for storing any information. registers placed in the address range 0x00 ? 0x1f are directly bit- accessible using the sbi, cbi, sbis and sbic instru ctions. 8.7.1 porta ? port a data register bit 7 6 5 4 3 2 1 0 $02 ($22) porta7:0 porta read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the porta register can be used as a general purpose i/o register for storing any information. ? bit 7:0 ? porta7:0 - port a data register value 8.7.2 ddra ? port a data direction register bit 7 6 5 4 3 2 1 0 $01 ($21) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ddra register can be used as a general purpose i/o register for storing any information. ? bit 7:0 ? dda7:0 - port a data direction register v alue 8.7.3 pina ? port a input pins address bit 7 6 5 4 3 2 1 0 $00 ($20) pina7:0 pina read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the pina register is reserved for interal use and c annot be used as a general purpose i/o register. ? bit 7:0 ? pina7:0 - port a input pins 29 8266c-mcu wireless-08/11 ATMEGA128RFA1 8.7.4 portc ? port c data register bit 7 6 5 4 3 2 1 0 $08 ($28) portc7:0 portc read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the portc register can be used as a general purpose i/o register for storing any information. ? bit 7:0 ? portc7:0 - port c data register value 8.7.5 ddrc ? port c data direction register bit 7 6 5 4 3 2 1 0 $07 ($27) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ddrc register can be used as a general purpose i/o register for storing any information. ? bit 7:0 ? ddc7:0 - port c data direction register v alue 8.7.6 pinc ? port c input pins address bit 7 6 5 4 3 2 1 0 $06 ($26) pinc7:0 pinc read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the pinc register is reserved for interal use and c annot be used as a general purpose i/o register. ? bit 7:0 ? pinc7:0 - port c input pins 30 8266c-mcu wireless-08/11 ATMEGA128RFA1 9 low-power 2.4 ghz transceiver 9.1 features ? high performance rf-cmos 2.4 ghz radio transceiver targeted for ieee 802.15.4?, zigbee? , ipv6 / 6lowpan, rf4ce, sp100, wirelesshart? and ism applications ? outstanding link budget (103.5 db): o receiver sensitivity -100 dbm o programmable output power from -17 dbm up to +3.5 d bm ? ultra-low current consumption: o trx_off = 0.4 ma o rx_on = 12.5 ma o busy_tx = 14.5 ma (at max. transmit power of +3.5 dbm) ? optimized for low bom cost and ease of production: o few external components necessary (crystal, capacit ors and antenna) o excellent esd robustness ? easy to use interface: o registers and frame buffer access from software o dedicated radio transceiver interrupts ? radio transceiver features: o 128 byte fifo (sram) for data buffering o integrated rx/tx switch o fully integrated, fast settling pll to support freq uency hopping o battery monitor o fast wake-up time < 0.25 ms ? special ieee 802.15.4 2006 hardware support: o fcs computation and clear channel assessment (cca) o rssi measurement, energy detection and link quality indication ? mac hardware accelerator: o automated acknowledgement, csma-ca and frame retransmission o automatic address filtering o automated fcs check ? extended feature set hardware support: o aes 128 bit hardware accelerator o rx/tx indication (external rf front-end control) o rx antenna diversity o supported psdu data rates: 250 kb/s, 500 kb/s, 1 mb /s and 2 mb/s o true random number generation for security applicat ions ? compliant to ieee 802.15.4-2006, ieee 802.15.4-2003 and rf4ce ? compliant to en 300 328/440, fcc-cfr-47 part 15, ar ib std-66, rss-210 31 8266c-mcu wireless-08/11 ATMEGA128RFA1 the ATMEGA128RFA1 features a low-power 2.4 ghz radi o transceiver designed for industrial and consumer zigbee/ieee 802.15.4, 6lowp an, rf4ce and high data rate 2.4 ghz ism band applications. the radio transceive r is a true peripheral block of the avr microcontroller. all rf-critical components exc ept the antenna, crystal and de- coupling capacitors are integrated on-chip. therefo re, the ATMEGA128RFA1 is particularly suitable for applications like: ? 2.4 ghz ieee 802.15.4 and zigbee systems ? 6lowpan and rf4ce systems ? wireless sensor networks ? industrial control, sensing and automation (sp100, wirelesshart) ? residential and commercial automation ? health care ? consumer electronics ? pc peripherals 9.2 general circuit description this radio transceiver is part of a system-on-chip solution with an avr ? microcontroller. it comprises a complex peripheral component contain ing the analog radio, digital modulation and demodulation including time and freq uency synchronization and data buffering. the number of external components for th e transceiver operation is minimized such that only the antenna, the crystal a nd decoupling capacitors are required. the bidirectional differential antenna pi ns (rfp, rfn) are used for transmission and reception, thus no external antenn a switch is needed. the transceiver block diagram of the ATMEGA128RFA1 is shown in figure 9-9 below . figure 9-9. transceiver block diagram avreg lna pll pa ppf bpf limiter rx adc agc ext. pa and power control configuration registers c interface rssi data interrupts address control dig3/4 rfp rfn tx data control logic antenna diversity ftn, batmon xosc xtal1 xtal2 analog domain digital domain aes dig1/2 ad rx bbp frame buffer tx bbp dvreg 32 8266c-mcu wireless-08/11 ATMEGA128RFA1 the received rf signal at pins rfn and rfp is diffe rentially fed through the low-noise amplifier (lna) to the rf filter (ppf) to generate a complex signal, driving the integrated channel filter (bpf). the limiting ampli fier provides sufficient gain to drive the succeeding analog-to-digital converter (rx adc) and generates a digital rssi signal. the rx adc output signal is sampled by the digital base band receiver (rx bbp). the transmit modulation scheme is offset-qpsk (o-qp sk) with half-sine pulse shaping and 32-length block coding (spreading) according to [1] on page 101 and [2] on page 101 . the modulation signal is generated in the digital transmitter (tx bbp) and applied to the fractional-n frequency synthesis (pll), to e nsure the coherent phase modulation required for demodulation of o-qpsk signals. the fr equency-modulated signal is fed to the power amplifier (pa). a differential pin pair dig3/dig4 can be enabled to control an external rf front-end. the two on-chip low-dropout voltage regulators (a|d vreg) provide the analog and digital 1.8v supply. an internal 128-byte ram for rx and tx (frame buffe r) buffers the data to be transmitted or received. the configuration of the reading and writing of the frame buffer is controlled via the microcontroller interface. the transceiver further contains comprehensive hard ware-mac support (extended operating mode) and a security engine (aes) to impr ove the overall system power efficiency and timing. the 128-bit aes engine can b e accessed in parallel to all phy operational transactions and states using the micro controller interface, except during transceiver power down state. for applications not necessarily targeting ieee 802 .15.4 compliant networks, the radio transceiver also supports alternative data rates up to 2 mb/s. for long-range applications or to improve the relia bility of an rf connection the rf performance can further be improved by using an ext ernal rf front-end or antenna diversity. both operation modes are supported by th e radio transceiver with dedicated control pins without the interaction of the microco ntroller. additional features of the extended feature set, se e section "radio transceiver extended feature set" on page 86 , are provided to simplify the interaction between radio transceiver and microcontroller. 9.3 transceiver to microcontroller interface this section describes the internal interface betwe en the transceiver module and the microcontroller. unlike all other avr i/o modules, the transceiver module can operate asynchronously to the controller. the transceiver r equires an accurate 16mhz crystal clock for operation, but the controller can run at any frequency within its operating limits. note that the on-chip debug system (see section "using the on-chip debug system" on page 439 ) must be disabled for the best rf performance of t he radio transceiver. 9.3.1 transceiver configuration and data access 9.3.1.1 register access all transceiver registers are mapped into i/o space of the controller. due to the asynchronous interface a register access can take u p to three transceiver clock cycles. depending on the controller clock speed, program ex ecution wait cycles are generated. 33 8266c-mcu wireless-08/11 ATMEGA128RFA1 that means if the controller runs with about 16mhz or faster, at least three wait cycles are generated, but if the controller runs with abou t 4mhz, no wait cycles are inserted. a register access is only possible, if the transceive r clock is available. therefore the transceiver must be enabled (prr1 register) and not in sleep state. 9.3.1.2 frame buffer access the 128-byte frame buffer can hold the phy service data unit (psdu) data of one ieee 802.15.4 compliant rx or one tx frame of maxim um length at a time. a detailed description of the frame buffer can be found in sec tion "frame buffer" on page 78 . an introduction to the ieee 802.15.4 frame format can be found in section "introduction ? ieee 802.15.4-2006 frame format" on page 62 . the frame buffer is located within the controller i /o address space above of the transceiver register set. the first byte of the fra me buffer can be accessed with the symbolical address trxfbst and the last byte can be accessed with the symbolical address trxfbend. random access to single frame byt es is possible with ?trxfbst + byte index? or ?trxfbend ? byte index?. in contra st to the transceiver register access, the frame buffer allows single cycle read/w rite operations for all controller clock speeds. the content of the frame buffer is only overwritten by a new received frame or a frame buffer write access. the frame buffer usage is different between receive d and transmitted frames. therefore it is not possible to retransmit a receiv ed frame without modifying the frame buffer. on received frames, the frame length byte is not st ored in the frame buffer, but can be accessed over the tst_frame_length register. during frame receive, the link quality indication (lqi) value (refer to "link quality indication (lqi)" on page 73 ) is appended to the frame data in the frame buffer. for frame transmission, the first byte of the frame buffer must contain the frame length information followed by the frame data. the tst_fra me_length register does not need to be written in this case. a detailed description of the frame buffer usage fo r receive and transmit frames can be found in figure 9-31 on page 79 . notes: 1. the frame buffer is shared between rx and tx; th erefore, the frame data are overwritten by new incoming frames. if the tx frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile. 2. to avoid overwriting during receive, dynamic fra me buffer protection can be enabled. for details about this feature refer to section "dynamic frame buffer protection" on page 92 . 3. it is not possible to retransmit received frames without inserting the frame length information at the beginning of the frame buffer. that requires a complete read out of the received frame and rewriting the modified frame to the frame buffe r. 4. for exceptions, e.g. receiving acknowledgement f rames in extended operating mode (tx_aret) refer to section "tx_aret_on ? transmit with automatic retry and csm a-ca retry" on page 58 . 9.3.1.3 transceiver pin register trxpr the transceiver pin register trxpr is located in th e controller clock domain and is accessible even if the transceiver is in sleep stat e. this register provides access to the pin functionality, known from the rf231 devices (tw o chip solution). 34 8266c-mcu wireless-08/11 ATMEGA128RFA1 the register (trxrst) can be used to reset the tran sceiver without resetting the controller. after the reset bit was set, it is clea red immediately. a second configuration bit (slptr) is used to contr ol frame transmission or sleep and wakeup of the transceiver. this bit is not cleared automatically. the function of the slptr bit relates to the curren t state of the transceiver module and is summarized in table 9-1 below . the radio transceiver states are explained in det ail in section "operating modes" on page 36 . table 9-1. slptr multi-functional configuration bit transceiver status function slptr bit description pll_on tx start ?0? ?1? starts frame transmission tx_aret_on tx start ?0? ?1? starts tx_aret transaction trx_off sleep ?0? ?1? takes the radio transceiver into sleep state sleep wakeup ?1? ?0? takes the radio transceiver back into trx_off state; in states pll_on and tx_aret_on, bit slptr is used to initiate a tx transaction. here bit slptr is sensitive on the transition from ?0? to ?1? only. the bit should be cleared before the frame transmission is finished. after initiating a state change by a ?0? to ?1? tra nsition at bit slptr in radio transceiver states trx_off, rx_on or rx_aack_on, the radio tran sceiver remains in the new state as long as the bit is logical ?1? and returns to the preceding state if the bit is set to ?0?. sleep state the sleep state is used when radio transceiver func tionality is not required, and thus the receiver module can be powered down to reduce t he overall power consumption. when the radio transceiver is in trx_off state the microcontroller forces the transceiver to sleep by setting slptr = ?1?. the tr ansceiver awakes when the microcontroller releases bit slptr. 9.3.2 interrupt logic 9.3.2.1 overview the transceiver module differentiates between eight interrupt events. internally all pending interrupt are stored in a separate bit of t he interrupt status register (irq_status). each interrupt is enabled by setting the corresponding bit in the interrupt mask register (irq_mask). if an irq is en abled an interrupt service routine must be defined to handle the irq. a pending irq is cleared automatically if an interrupt service routine is called. it is also pos sible to handle irqs manually by polling the irq_status register. if an irq occurred, the ap propriate irq_status register bit is set. the irq can be cleared by writing ?1? t o the register bit. it is recommended to clear the corresponding status bit before enabling an interrupt. interrupts are not cleared automatically when the e vent that caused them vanishes. more information about interrupt handling by the co ntroller can be found in section "interrupts" on page 212 . the supported interrupts for the basic operating mo de are summarized in table 9-2 on page 35. 35 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-2. interrupt description in basic operating mode irq vector number/ priority (1) irq name description section 64 trx24_awake indicates radio transceiver reached trx_off state reset, or sleep states "trx_off ? clock state" on page 37 63 trx24_tx_end indicates the completion of a frame transmission "frame transmit procedure" on page 85 62 trx24_xah_ami indicates address matching "frame filtering" on page 55 61 trx24_cca_ed_done indicates the end of a cca or ed measurement "energy detection (ed)" on page 69 60 trx24_rx_end indicates the completion of a frame reception "frame transmit procedure" on page 85 59 trx24_rx_start indicates the start of a psdu rec eption. the trx_state changes to busy_rx, the phr is ready to be read from frame buffer "frame receive procedure" on page 85 58 trx24_pll_unlock indicates pll unlock. if the ra dio transceiver is in busy_tx / busy_tx_aret state, the pa is turned off immediately "interrupt handling" on page 84 57 trx24_pll_lock indicates pll lock "interrupt handling" on page 84 note: 1. the lowest irq number has the highest prio rity. during startup from sleep or reset, the radio trans ceiver issues an trx24_awake interrupt when it enters state trx_off. if the microcontroller initiates an energy-detect ( ed) or clear-channel-assessment (cca) measurement, the completion of the measuremen t is indicated by interrupt trx24_cca_ed_done, refer to sections "energy detection (ed)" on page 69 and "clear channel assessment (cca)" on page 71 for details. after reset all interrupts are disabled. during rad io transceiver initialization it is recommended to enable awake to be notified once the trx_off state is entered. note that the trx24_awake interrupt can usually not be seen when the transceiver enters trx_off state after reset, because register irq_mask is reset to mask all interrupts. in this case, state trx_off is normally entered before the microcontroller could modify the register. the interrupt handling in extended operating mode i s described in section "interrupt handling" on page 60 . 9.3.3 radio transceiver identification the ATMEGA128RFA1 transceiver module can be identif ied by four registers (part_num, version_num, man_id_0, man_id_1). one re gister contains a unique part number and one register the correspondi ng version number. two additional registers contain the jtag manufacture id. the tran sceiver identification registers are provided for compatibility to the transceiver only device. a unique device identification is also possible wit h the three avr signature bytes. for details about accessing this information refer to "signature bytes" on page 468 . 36 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4 operating modes 9.4.1 basic operating mode this section summarizes all states to provide the b asic functionality of the 2.4ghz radio transceiver, such as receiving and transmitting fra mes, the power up sequence and radio transceiver sleep. the basic operating mode i s designed for ieee 802.15.4 and ism applications; the corresponding radio transceiv er states are shown in figure 9-12 below . figure 9-12. basic operating mode state diagram (for timing refe r to table 9-3 on page 43 ) 2 s l p t r = 1 s l p t r = 0 p l l _ o n r x _ o n p l l _ o n t r x _ o f f (c lo c k s ta te ) x o s c = o n r x _ o n s l e e p (s le e p s ta te ) x o s c = o f f f o r c e _ t r x _ o f f (a ll s ta te s e x c e p t s l e e p ) s h r d e te c te d f ra m e e n d f ra m e e n d b u s y _ t x (t ra n s m it s ta te ) p l l _ o n (p l l s ta te ) t x _ s t a r t o r t r x _ o f f t r x _ o f f 3 4 5 7 6 8 9 1 1 1 0 1 2 1 3 t r x r s t = 0 f o r c e _ p l l _ o n (a ll s ta te s e x c e p t s l e e p , t r x _ o f f ) 1 4 s l p t r = 1 l e g e n d : b lu e : r e g is te r w rite to t r x _ s t a t e r e d : c o n tro l s ig n a ls v ia r e g is te r t r x p r g re e n : e v e n t b a s ic o p e ra tin g m o d e s ta te s s ta te tra n s itio n n u m b e r r x _ o n (r x l is te n s ta te ) b u s y _ r x (r e c e iv e s ta te ) r e s e t (fro m a ll s ta te s ) t r x r s t = 1 x note: 1. state transition numbers correspond to table 9-3 on page 43. 9.4.1.1 state control the radio transceiver states are controlled either by writing commands to bits trx_cmd of register trx_state, or directly by the t wo control bits slptr and trxrst of the trxpr register. a successful state ch ange can be verified by reading the radio transceiver status from register trx_stat us. if trx_status = 0x1f (state_transition_in_progress) the radio transceiver is on a state transition. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress. 37 8266c-mcu wireless-08/11 ATMEGA128RFA1 bit slptr is a multifunctional bit (refer to sectio n "transceiver pin register trxpr" on page 33 for more details). dependent on the radio transceiv er state, a ?0? to ?1? transition on slptr causes the following state tran sitions: ? trx_off sleep ? pll_on busy_tx whereas resetting bit slptr to ?0? causes the follo wing state transitions: ? sleep trx_off bit trxrst causes a reset of all radio transceiver registers and forces the radio transceiver into trx_off state. for all states except sleep, the state change comma nds force_trx_off or trx_off lead to a transition into trx_off state. if the radio transceiver is in active receive or transmit states (busy_*), the command fo rce_trx_off interrupts these active processes, and forces an immediate transitio n to trx_off. in contrast a trx_off command is stored until an active state (re ceiving or transmitting) has been finished. after that the transition to trx_off is p erformed. for a fast transition from receive or active transm it states to pll_on state the command force_pll_on is provided. in contrast to fo rce_trx_off this command does not disable the pll and the analog vol tage regulator avreg. it is not available in states sleep, and reset. the completion of each requested state-change shall always be confirmed by reading the bits trx_status of register trx_status. 9.4.1.2 basic operating mode description 9.4.1.2.1 sleep ? sleep state in radio transceiver sleep state, the entire radio transceiver is disabled. no circuitry is operating. the radio transceiver?s current consumpt ion is reduced to leakage current only. this state can only be entered from state trx _off, by setting the bit slptr = ?1?. setting slptr = ?0? returns the radio transceiver t o the trx_off state. during radio transceiver sleep the register contents remains val id while the content of the frame buffer and the security engine (aes) are cleared. trxrst = ?1? in sleep state returns the radio trans ceiver to trx_off state and thereby sets all registers to their reset values. 9.4.1.2.2 trx_off ? clock state this state is reached immediately after power on or reset. in trx_off the crystal oscillator is running. the digital voltage regulato r is enabled, thus the radio transceiver registers, the frame buffer and security engine (ae s) are accessible (see section "frame buffer" on page 78 and "security module (aes)" on page 93 ). slptr and trxrst in register trxpr can be used for state control (see "state control" on page 36 for details). the analog front-end is disa bled during trx_off. entering the trx_off state from radio transceiver s leep, or reset state is indicated by the trx24_awake interrupt. 38 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.1.2.3 pll_on ? pll state entering the pll_on state from trx_off state first enables the analog voltage regulator (avreg). after the voltage regulator has been settled the pll frequency synthesizer is enabled. when the pll has been settl ed at the receive frequency to a channel defined by bits channel of register phy_cc_ cca a successful pll lock is indicated by issuing a trx24_pll_lock interrupt. if an rx_on command is issued in pll_on state, the receiver is immediately enabled. if the pll has not been settled before the state ch ange nevertheless takes place. even if the register bits trx_status of register trx_sta tus indicates rx_on, actual frame reception can only start once the pll has loc ked. the pll_on state corresponds to the tx_on state in ieee 802.15.4. 9.4.1.2.4 rx_on and busy_rx ? rx listen and receive state in rx_on state the receiver blocks and the pll freq uency synthesizer are enabled. the receive mode is internally separated into the r x_on and busy_rx states. there is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on. in both stat es the receiver and the pll frequency synthesizer are enabled. during rx_on state the receiver listens for incomin g frames. after detecting a valid synchronization header (shr), the receiver automati cally enters the busy_rx state. the reception of a valid phy header (phr) generates an trx24_rx_start interrupt and receives and demodulates the psdu data. during psdu reception the frame data are stored con tinuously in the frame buffer until the last byte was received. the completion of the f rame reception is indicated by an trx24_rx_end interrupt and the radio transceiver re enters the state rx_on. at the same time the bits rx_crc_valid of register phy_rss i are updated with the result of the fcs check (see "frame check sequence (fcs)" on page 67). received frames are passed to the frame filtering u nit, refer to section "frame filtering" on page 55. if the content of the mac addressing fiel ds of a frame (refer to ieee 802.15.4 section 7.2.1) matches to the expecte d addresses, which is further dependent on the addressing mode, an address match interrupt (trx24_xah_ami) is issued, refer to "interrupt logic" on page 34 . the expected address values are to be stored in the registers short-address, pan-id and i eee-address. frame filtering is available in basic and extended operating mode, ref er to section "frame filtering" on page 55. leaving state rx_on is only possible by writing a s tate change command to bits trx_cmd of register trx_state. 9.4.1.2.5 busy_tx ? transmit state a transmission can only be initiated in state pll_o n. there are two ways to start a transmission: ? setting bit slptr of register trxpr to ?1?. the bi t should be cleared before the frame has been transmitted. this mode is for legacy operation and should be replaced by the tx_start command below. ? tx_start command to bits trx_cmd of register trx_s tate. either of these causes the radio transceiver into t he busy_tx state. 39 8266c-mcu wireless-08/11 ATMEGA128RFA1 during the transition to busy_tx state, the pll fre quency shifts to the transmit frequency. the actual transmission of the first dat a chip of the shr starts after 16 s to allow pll settling and pa ramp-up, see figure 9-16 on page 41. after transmission of the shr, the frame buffer content is transmitted. i n case the phr indicates a frame length of zero, the transmission is aborted. after the frame transmission has completed, the rad io transceiver automatically turns off the power amplifier, generates a trx24_tx_end i nterrupt and returns into pll_on state. 9.4.1.2.6 reset state the reset state is used to set back the state machi ne and to reset all registers of the radio transceiver to their default values. a reset forces the radio transceiver into the trx_o ff state. a reset is initiated by a ATMEGA128RFA1 main reset (see "resetting the avr" on page 178 ) or a radio transceiver reset (see "transceiver pin register trxpr" on page 33 ). during radio transceiver reset the trxpr register i s not cleared and therefore the application software has to set the slptr bit to ?0 ?. 9.4.1.3 interrupt handling all interrupts provided by the radio transceiver ar e supported in basic operating mode (see table 9-2 on page 35 ). required interrupts must be enabled by writing to r egister irq_mask and the global interrupt enable flag must be set. for a general ex planation of the interrupt handling refer to "reset and interrupt handling" on page 15 and "interrupt logic" on page 34 . for example, interrupts are provided to observe the status of the rx and tx operations. on receive the trx24_rx_start interrupt indicates t he detection of a valid phr, the trx24_xah_ami interrupt an address match and the tr x24_rx_end interrupt the completion of the frame reception. on transmit the trx24_tx_end interrupt indicates th e completion of the frame transmission. figure 9-13 on page 40 shows an example for a transmit/receive transaction between two devices and the related interrupt events in bas ic operating mode. device 1 transmits a frame containing a mac header (in this example of length 7), payload and valid fcs. the frame is received by device 2 which generates the interrupts during the processing of the incoming frame. the received fram e is stored in the frame buffer. if the received frame passes the address filter (re fer to section "frame filtering" on page 55) an address match trx24_xah_ami interrupt i s issued after the reception of the mac header (mhr). in basic operating mode the trx24_rx_end interrupt is issued at the end of the received frame. in extended operating mode (refer t o "extended operating mode" on page 44) the interrupt is only issued if the receiv ed frame passes the address filter and the fcs is valid. further exceptions are explained in "extended operating mode" on page 44. processing delay t irq is a typical value (see chapter "digital interface timing characteristics" on page 516 ). 40 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-13. timing of trx24_rx_start, trx24_xah_ami, trx24_tx_ end and trx24_rx_end interrupts in basic operating mode 1 2 8 1 6 0 1 9 2 0 1 9 2 + ( 9 + m ) * 3 2 - 1 6 t i m e [ s ] rx (device 2) t r x 2 4 _ r x _ s t a r t t i r q r x _ o n r x _ o n i r q t r x _ s t a t e i n t e r r u p t l a t e n c y t r x 2 4 _ r x _ e n d t r x 2 4 _ x a h _ a m i t i r q t i r q b u s y _ r x t r x 2 4 _ t x _ e n d tx (device1) p l l _ o n b u s y _ t x p l l _ o n i r q s l p t r t r x _ s t a t e t y p . p r o c e s s i n g d e l a y 1 6 s frame on air p r e a m b l e s f d p h r m s d u 4 1 1 m n u m b e r o f o c t e t s f r a m e c o n t e n t m h r 7 f c s 2 9.4.1.4 basic operating mode timing the following paragraphs depict state transitions a nd their timing properties. timing figures are explained in table 9-3 on page 43 and section "digital interface timing characteristics" on page 516. 9.4.1.4.1 wake-up procedure the wake-up procedure from radio transceiver sleep state is shown in figure 9-14 below . this figure implies, that the microcontroller is already running and hence, the digital voltage regulator is enabled. if the microc ontroller clock source is set to transceiver clock, the crystal oscillator is also r unning, which reduces the radio transceiver wake-up time further. for information a bout the wake-up timing of the microcontroller, depending on the different clock s ource options, refer to "system clock and clock options" on page 148 . in order to calculate the total wake-up delay from microcontroller sleep mode (see "power management and sleep modes" on page 157 ), the microcontroller wake-up time, including the voltage regulator ramp-up and t he radio transceiver wake-up time has to be added. figure 9-14. wake-up procedure from transceiver sleep state 0 event state block 100 400 time [s] tim e t tr2 trx_off trx24_aw ake irq slptr = 0 sleep 200 xosc startup xosc enabled ftn the radio transceiver sleep state is left by releas ing bit slptr to ?0?. this restarts the xosc if it is not already running. after t tr2 = 215 s + 25 s = 240 s (see table 9-3 on page 43) the radio transceiver enters trx_off state . if the xosc is already running, the radio transceiver enters trx_off state after 25 s. 41 8266c-mcu wireless-08/11 ATMEGA128RFA1 during this wake-up procedure the calibration of th e filter-tuning network (ftn) is performed. entering trx_off state is signaled by th e trx24_awake interrupt, if enabled. 9.4.1.4.2 pll_on and rx_on states the transition from trx_off to pll_on and rx_on mod e is shown in figure 9-15 below . figure 9-15. transition from trx_off to pll_on and rx_on state 0 event state block 100 time [s] time t tr4 trx24_pll_lock irq trx_off avreg command pll_on pll rx pll_on rx_on t tr8 rx_on note: 1. if trx_cmd = rx_on in trx_off state rx_on state is entered immediately, even if the pll has not settled. 2. if the avr adc module is enabled, the avreg is a lready started and thus the state transition time t tr4 is reduced. entering the commands pll_on or rx_on in trx_off st ate initiates a ramp-up sequence of the internal 1.8v voltage regulator for the analog domain (avreg), if avreg is not already enabled by the avr adc module. rx_on state can be entered any time from pll_on state regardless whether the p ll has already locked as indicated by the trx24_pll_lock interrupt. 9.4.1.4.3 busy_tx and rx_on states the transition from pll_on to busy_tx state and sub sequent to rx_on state is shown in figure 9-16 below . figure 9-16. pll_on to busy_tx to rx_on timing tim e [ s] 0 x 16 x + 32 tim e t tr 11 t tr 10 com m and r x_o n state block pll_o n rx_o n busy_tx event slptr pa pll pa, tx rx pll or com m and tx_start starting from pll_on state it is assumed that the p ll is already locked. a transmission is initiated either by writing ?1? to bit slptr or by command tx_start. the pll settles to the transmit frequency and the p a is enabled. 42 8266c-mcu wireless-08/11 ATMEGA128RFA1 t tr10 = 16 s after initiating the transmission, the rad io transceiver changes into busy_tx state and the internally generated shr is t ransmitted. after that the psdu data are transmitted from the frame buffer. after completing the frame transmission, indicated by the trx24_tx_end interrupt, the pll settles back to the receive frequency withi n t tr11 = 32 s in state pll_on. if during tx_busy the radio transmitter is programm ed to change to a receive state it automatically proceeds the state change to rx_on st ate after finishing the transmission. 9.4.1.4.4 reset procedure the radio transceiver reset procedure is shown in figure 9-17 below . figure 9-17. reset procedure x e v e n t s ta te b lo c k t im e [ s ] t r x r s t t r x _ o f f x + 4 0 [t r x 2 4 _ a w a k e ir q ] 0 v a rio u s t im e 3 x a v r c lo c k t t r 1 3 > t1 1 x o s c , d v r e g e n a b le d x o s c , d v r e g e n a b le d x + 1 0 f t n note: 1. timing parameter t tr13 = 37 s refers to table 9-3 on page 43; t 11 refers to "digital interface timing characteristics" on page 516 . 2. if trxrst is set during radio transceiver sleep state, the xosc startup delay is extended by the xosc startup time. trxrst = ?1? resets all radio transceiver registers to their default values. the radio transceiver reset is released automatical ly after 3 avr clock cycles and the wake-up sequence without restarting xosc and dvreg, nevertheless an ftn calibration cycle is performed, refer to "automatic filter tuning (ftn)" on page 84. after that the trx_off state is entered. figure 9-17 above illustrates the radio transceiver reset procedure i f the radio transceiver is in any state but not in sleep state. if the radio transceiver was in sleep state, the sl ptr bit in the trxpr register must be cleared prior to clearing the trxrst bit in orde r to enter the trx_off state. otherwise the radio transceiver enters the sleep st ate immediately. if the radio transceiver was in sleep state and the transceiver clock is not selected as the microcontroller clock source, the xosc is enabl ed before entering trx_off state. if register trx_status indicates state_transition_i n_progress during system initialization until the radio transceiver r eaches trx_off, do not try to initiate a further state change while the radio transceiver is in this state. note that before accessing the radio transceiver mo dule the trx24_awake event should be checked. 43 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.1.4.5 state transition timing summary the transition numbers correspond to table 9-3 below . see measurement setup in "basic application schematic" on page 495. table 9-3. radio transceiver state transition timing no symbol transition time [s], (typ) comments 1 t tr2 sleep trx_off 240 depends on crystal oscillator setup (cl = 10 pf) trx_off state indicated by trx24_awake interrupt 2 t tr3 trx_off sleep 35 1 / f clkm for f clkm > 250 khz 3 t tr4 trx_off pll_on 110 depends on external capacitor at avdd ( 1 f nom) 4 t tr5 pll_on trx_off 1 5 t tr6 trx_off rx_on 110 depends on external capacitor at avdd (1 f nom) 6 t tr7 rx_on trx_off 1 7 t tr8 pll_on rx_on 1 8 t tr9 rx_on pll_on 1 transition time is also valid for tx_aret _on, rx_aack_on 9 t tr10 pll_on busy_tx 16 when setting bit slptr or trx_cmd = tx_start, the f irst symbol transmission is delayed by 16 s (pll settli ng and pa ramp up). 10 t tr11 busy_tx pll_on 32 pll settling time from tx_busy to pll_on state 11 t tr12 all modes trx_off 1 using trx_cmd = force_trx_off (see register trx_state), not valid for sleep state 12 t tr13 reset trx_off 37 not valid for sleep state 13 t tr14 various states pll_on 1 using trx_cmd = force_pll_on (see register trx_state), not valid for sleep, reset and trx_off the state transition timing is calculated based on the timing of the individual blocks shown in table 9-8 on page 52. the worst case values include maximum ope rating temperature, minimum supply voltage, and device par ameter variations. table 9-8. analog block initialization and settling time no symbol block time [s], (typ) time [s], (max) comments 15 t tr15 xosc 215 1000 leaving sleep state, depends on crystal q factor an d load capacitor 16 t tr16 ftn 25 ftn tuning time, fixed 17 t tr17 dvreg 60 1000 depends on external bypass capacitor at dvdd (cb3 = 1 f nom., 10 f worst case), depends on v devdd 18 t tr18 avreg 60 1000 depends on external bypass capacitor at avdd (cb1 = 1 f nom., 10 f worst case) , depends on v evdd 19 t tr19 pll, initial 110 155 pll settling time trx_off pll_on, including 60 s avreg settling time 20 t tr20 pll, settling 11 24 settling time between channel switch 21 t tr21 pll, cf cal 35 pll center frequency calibration, refer to "calibration loops" on page 83 22 t tr22 pll, dcu cal 6 pll dcu calibration, refer to "calibration loops" on page 83 23 t tr23 pll, rx tx 16 maximum pll settling time rx tx 44 8266c-mcu wireless-08/11 ATMEGA128RFA1 no symbol block time [s], (typ) time [s], (max) comments 24 t tr24 pll, tx rx 32 maximum pll settling time tx rx 25 t tr25 rssi, update 2 rssi update period in receive states, refer to "reading rssi" on page 69 26 t tr26 ed 140 ed measurement period, refer to "measurement description" on page 70 27 t tr27 shr, sync 96 typical shr synchronization period, refer to "measurement description" on page 70 28 t tr28 cca 140 cca measurement period, refer to "configuration and cca request" on page 72 29 t tr29 random value 1 random value update period, refer to "random number generator" on page 86 9.4.2 extended operating mode the extended operating mode is a hardware mac accel erator and goes beyond the basic radio transceiver functionality provided by t he basic operating mode. it handles time critical mac tasks requested by the ieee 802.1 5.4 standard or by hardware such as automatic acknowledgement, automatic csma-ca and retransmission. this results in a more efficient ieee 802.15.4 software mac impl ementation including reduced code size and may allow operating at lower microcontroll er clock rates. the extended operating mode is designed to support ieee 802.15.4-2006 compliant frames; the mode is backward compatible to ieee 802 .15.4-2003 and supports non ieee 802.15.4 compliant frames. this mode comprises the following procedures: automatic acknowledgement (rx_aack) divides into th e tasks: ? frame reception and automatic fcs check; ? configurable addressing fields check; ? interrupt indicating address match; ? interrupt indicating frame reception, if it passes address filtering and fcs check; ? automatic ack frame transmission (if the received frame passed the address filter and fcs check and if an ack is required by the fram e type and ack request); ? support of slotted acknowledgment using slptr bit for frame start. automatic csma-ca and retransmission (tx_aret) divi des into the tasks: ? csma-ca including automatic cca retry and random b ack-off; ? frame transmission and automatic fcs field generat ion; ? reception of ack frame (if an ack was requested); ? automatic frame retry if ack was expected but not received; ? interrupt signaling with transaction status. automatic fcs check and generation (refer to "frame check sequence (fcs)" on page 67) is used by the rx_aack and tx_aret modes. in rx_aac k mode an automatic fcs check is always performed for incomin g frames. an ack received in tx_aret mode within the time req uired by ieee 802.15.4 is accepted if the fcs is valid and if the sequence nu mber of the ack matches the sequence number of the previously transmitted frame . dependent on the value of the 45 8266c-mcu wireless-08/11 ATMEGA128RFA1 frame pending subfield in the received acknowledgem ent frame the transaction status is set according to table 9-16 on page 59. the state diagram including the extended operating mode states is shown in figure 9- 18 below . yellow marked states represent the basic operatin g mode; blue marked states represent the extended operating mode. figure 9-18. extended operating mode state diagram 2 s l p t r = 1 l e g e n d : b lu e : r e g iste r w rite to t r x _ s t a t e r ed : c o n tro l sig n a ls via r e g iste r t r x p r g re e n : e ve nt b a sic o p e ra ting m o d e s ta te s e xte n de d o p e ra tin g m o d e s ta te s s l p t r = 0 p l l _ o n r x _ o n p l l _ o n t r x _o f f (c lo c k s ta te ) x o s c = o n r x _ o n s l e e p (s le e p s ta te ) x o s c = o ff f o r c e _ t r x _ o f f (all m o d e s e xce p t s l e e p ) f ra m e e n d f ra m e e n d b u s y _ t x (t ra n s m it s ta te ) r x _ o n (r x l is te n s ta te ) b u s y _ r x (r e c e iv e s ta te ) t r x _ o f f t r x _ o f f 3 4 5 7 6 8 9 11 10 b u s y _r x _a a c k b u s y _t x _a r e t s h r d e tec te d t ran s - a c tio n f in is h e d tx_aret_on pll_on s l p t r = 1 o r t x _ s t a r t f ra m e e n d p l l _ o n r x _ a a c k _ o n t x _ a r e t _ o n r x _ a a c k _ o n f rom / t o t r x _o f f f rom / t o t r x _o f f t r x r s t = 0 1 2 1 3 f o r c e _ p l l _ o n 1 4 s l p t r = 1 o r t x _ s t a r t s h r d e te c te d t x _ a r e t _ o n r x _a a c k _ o n p l l _ o n (p l l s ta te ) see notes r e s e t (fro m a ll sta te s) t r x r s t = 1 t r x _ o f f t r x _ o f f note: 1. state transition numbers correspond to table 9-3 on page 43. 46 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.2.1 state control the extended operating mode states rx_aack and tx_a ret are controlled via the bits trx_cmd of register trx_state, which receives the state transition commands. the states are entered from trx_off or pll_on state as illustrated in figure 9-18 on page 45. the completion of each state change comman d shall always be confirmed by reading the trx_status register. rx_aack - receive with automatic ack a state transition to rx_aack_on from pll_on or trx _off is initiated by writing the command rx_aack_on to the register bits trx_cmd. th e state change can be confirmed by reading register trx_status, those cha nges to rx_aack_on or busy_rx_aack on success. busy_rx_aack is returned i f a frame is currently being received. the rx_aack state is left by writing command trx_of f or pll_on to the register bits trx_cmd. if the radio transceiver is within a frame receive or acknowledgment procedure (busy_rx_aack) the state change is execut ed after finish. alternatively, the commands force_trx_off or force_pll_on can be u sed to cancel the rx_aack transaction and change into radio transceiv er state trx_off or pll_on respectively. tx_aret - transmit with automatic retry and csma-ca retry similarly, a state transition to tx_aret_on from pl l_on or trx_off is initiated by writing command tx_aret_on to register bits trx_cmd . the radio transceiver is in the tx_aret_on state after trx_status register chan ges to tx_aret_on. the tx_aret transaction is started with writing ?1? to the slptr bit of the trxpr register or writing the command tx_start to register bits tr x_cmd. tx_aret state is left by writing the command trx_of f or pll_on to the register bits trx_cmd. if the radio transceiver is within a csma- ca, a frame-transmit or an acknowledgment procedure (busy_tx_aret) the state c hange is executed after finish. alternatively, the command force_trx_off or force_pll_on can be used to instantly terminate the tx_aret transaction and change into radio transceiver states trx_off or pll_on, respectively. note that a state change request from trx_off to rx _aack_on or tx_aret_on internally passes the state pll_on to initiate the radio transceiver. thus the readiness to receive or transmit data is delayed accordingly. it is recommended to use interrupt trx24_pll_lock as an indicator. 9.4.2.2 configuration the use of the extended operating mode is based on basic operating mode functionality. only features beyond the basic radio transceiver functionality are described in the following sections. for details on the basic operating mode refer to section "basic operating mode" on page 36. when using the rx_aack or tx_aret modes, the follow ing registers needs to be configured. rx_aack configuration steps: ? short address, pan-id and ieee address (register s hort_aadr_0, short_addr_1, pan_id_0, pan_id_1, ieee_addr_0 ? iee e_addr_7) ? configure rx_aack properties (register xah_ctrl_0, csma_seed_1) o handling of frame version subfield 47 8266c-mcu wireless-08/11 ATMEGA128RFA1 o handling of pending data indicator o characterize as pan coordinator o handling of slotted acknowledgement ? additional frame filtering properties (register xa h_ctrl_1, csma_seed_1) o promiscuous mode o enable or disable automatic ack generation o handling of reserved frame types the addresses for the address match algorithm are t o be stored in the appropriate address registers. additional control of the rx_aac k mode is done with registers xah_ctrl_1 and csma_seed_1. as long as a short address has not been set, only b roadcast frames and frames matching the ieee address can be received. configuration examples for different device operati ng modes and handling of various frame types can be found in section "description of rx_aack configuration bits" on page 50. tx_aret configuration steps: ? leave register bit tx_auto_crc_on = 1 register tr x_ctrl_1 ? configure csma-ca o max_frame_retries register xah_ctrl_0 o max_csma_retries register xah_ctrl_0 o csma_seed registerscsma_seed_0, csma_seed_1 o max_be, min_be register csma_be ? configure cca (see section "configuration and cca request" on page 72 ) max_frame_retries (register xah_ctrl_0) defines the maximum number of frame retransmissions. the register bits max_csma_retries (register xah_ct rl_0) configure the number of csma-ca retries after a busy channel is detected . the csma_seed_0 and csma_seed_1 registers define a random seed for the back- off-time random-number generator of the radio trans ceiver. the max_be and min_be register bits (register csma_ be) set the maximum and minimum csma back-off exponent (according to [1] on page 101 ) . 9.4.2.3 rx_aack_on ? receive with automatic ack the general functionality of the rx_aack procedure is shown in figure 9-19 on page 49. the gray shaded area is the standard flow of a rx_a ack transaction for ieee 802.15.4 compliant frames (refer to section "configuration of ieee scenarios" on page 51). all other procedures are exceptions for s pecific operating modes or frame formats (refer to section "configuration of non ieee 802.15.4 compliant scena rios" on page 53). the frame filtering operation is described in detai l in section "frame filtering" on page 55. in rx_aack_on state, the radio transceiver listens for incoming frames. after detecting shr and a valid phr, the radio transceive r parses the frame content of the mac header (mhr) as described in section "phy header (phr)" on page 62. 48 8266c-mcu wireless-08/11 ATMEGA128RFA1 generally, at nodes, configured as a normal device or pan coordinator, a frame is not indicated if the frame filter does not match and th e fcs is invalid. otherwise, the trx_24_rx_end interrupt is issued after the complet ion of the frame reception. the microcontroller can then read the frame. an excepti on applies if promiscuous mode is enabled (see section "configuration of ieee scenarios" on page 51). in that case a trx_24_rx_end interrupt is issued even if the fcs f ails. if the content of the mac addressing fields of the received frame (refer to ieee 802.15.4 section 7.2.1) matches one of the con figured addresses, dependent on the addressing mode, an address match interrupt (tr x24_xah_ami) is issued (refer to section "frame filtering" on page 55). the expected address values are to be st ored in registers short-address, pan-id and ieee-address. f rame filtering as described in section "frame filtering" on page 55 is also valid for basic operating mode. during reception the radio transceiver parses bit[5 ] (ack request) of the frame control field of the received data or the mac command frame to check if an ack reply is expected. in that case and if the frame passes the third level of filtering (see ieee 802.15.4-2006, section 7.5.6.2), the radio tra nsceiver automatically generates and transmits an ack frame. after the ack transmission is finished, a trx24_tx_end interrupt is generated. the content of the frame pending subfield of the ac k response is set by bit aack_set_pd of register csma_seed_1 when the ack fr ame is sent in response to a data request mac command frame, otherwise this su bfield is set to ?0?. the sequence number is copied from the received frame. optionally, the start of the transmission of the ac knowledgement frame can be influenced by register bit aack_ack_time. default v alue (according to standard ieee 802.15.4, page 54) is 12 symbol times after th e reception of the last symbol of a data or mac command frame. if the bit aack_dis_ack of register csma_seed_1 is set, no acknowledgement frame is sent even if an acknowledgment frame was r equested. this is useful for operating the mac hardware accelerator in promiscuo us mode (see section "configuration of non ieee 802.15.4 compliant scena rios" on page 53). the status of the rx_aack operation is indicated by the bits trac_status of register trac_status. during the operations described above the radio tra nsceiver remains in busy_rx_aack state. 49 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-19. flow diagram of rx_aack reserved frames trx_state = rx_aack_on shr detected trx_state = busy_rx_aack scanning mhr frame reception frame filtering ack requested (see note 3) wait 12 symbol periods transmit ack trx_state = rx_aack_on n y n y generate trx24_rx_start interrupt aack_prom_mode == 1 generate trx24_xah_ami interrupt y generate trx24_rx_end interrupt frame reception note 3: additional conditions: - ack requested & - ack_dis_ack==0 & - frame_version<=aack_fvn_mode slotted operation == 0 y aack_ack_time == 0 y wait 2 symbol periods wait 6 symbol periods slptr bit = 1 n n generate trx24_rx_end interrupt n y n aack_ack_time == 0 y wait 2 symbol periods n fcs valid (see note 2) y n aack_upld_res_ft == 1 fcs valid generate trx24_rx_end interrupt y y n n n note 2: fcs check is omitted for promiscous mode fcf[2:0] > 3 n y y promiscuous mode note 1: frame filtering, promiscuous mode and reserved frames: - a radio transceiver in promiscuous mode, or configured to receive reser ved frames handles received frames passi ng the third level of filtering - for details refer to the description of promiscuous mode and reserved frame types (see note 1) generatetrx24_tx_end interrupt 50 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.2.3.1 description of rx_aack configuration bits overview the following table summarizes all register bits wh ich affect the behavior of a rx_aack transaction. for address filtering it is fu rther required to setup address registers to match to the expected address. configuration and address bits are to be set in trx _off or pll_on state prior to switching to rx_aack mode. a graphical representation of various operating mod es is illustrated in figure 9-19 on page 49. table 9-5. overview of rx_aack configuration bits register name register bits description short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 set node addresses rx_safe_mode 7 protect buffer after frame receive aack_prom_mode 1 support promiscuous mode aack_ack_time 2 change auto acknowledge start time aack_upld_res_ft 4 enable reserved frame type recep tion, needed to receive non-standard compliant frames aack_fltr_res_ft 5 filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames slotted_operation 0 if set, acknowledgment transmis sion has to be triggered by register bit slptr aack_i_am_coord 3 if set, the device is a pan coord inator aack_dis_ack 4 disable generation of acknowledgment aack_set_pd 5 set frame pending subfield in frame c ontrol field (fcf), refer to section "overview" on page 67 aack_fvn_mode 7:6 controls the ack behavior, depend ing on fcf frame version number the usage of the rx_aack configuration bits for var ious operating modes of a node is explained in the following sections. configuration bits not mentioned in the following two sections should be set to their reset values . all registers mentioned in table 9-5 above are described in section "register summary" on page 61. note, that the general behavior of the extended fea ture set settings: ? oqpsk_data_rate (psdu data rate) ? sfd_value (alternative sfd value) ? ant_div (antenna diversity) ? rx_pdt_level (blocking frame reception of lower p ower signals) are completely independent from rx_aack mode (see "radio transceiver extended feature set" on page 86 ) . each of these operating modes can be combined with the rx_aack mode. 51 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.2.3.2 configuration of ieee scenarios normal device the table 9-6 below shows a typical rx_aack configuration of an ieee 8 02.15.4 device operated as a normal device rather than a pa n coordinator or router. table 9-6. configuration of ieee 802.15.4 devices register name register bits description short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 set node addresses rx_safe_mode 7 0 : disable frame protection 1 : enable frame protection slotted_operation 0 0 : if transceiver works in unslotted mode 1 : if transceiver works in slotted mode aack_fvn_mode 7:6 controls the ack behavior, depend ing on fcf frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames 0x01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2006 0x10 : acknowledges only frames with version number 0 or 1 or 2 0x11 : acknowledges all frames, independent of the fcf frame version number notes: 1. if no short address has been configured b efore the device has been assigned one by the pan-coordinator, only frames directed to eit her the broadcast address or the ieee address are received. 2. in ieee 802.15.4-2003 standard the frame version subfield did not yet exist but was marked as reserved. according to this standard, reserved fields have to be set to zero. on the other hand, ieee 802.15.4-2003 stan dard requires ignoring reserved bits upon reception. thus, there is a cont radiction in the standard which can be interpreted in two ways: a) if a network should only allow access to nodes w hich use the ieee 802.15.4-2003, then aack_fvn_mode should be se t to 0. b) if a device should acknowledge all frames indepe ndent of its frame version, aack_fvn_mode should be set to 3. however, this can result in conflicts with co-existing ieee 802.15.4-2006 standard compliant n etworks. the same holds for pan coordinators as described be low. pan-coordinator table 9-7 on page 52 shows the rx_aack configuration for a pan coordinator. 52 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-7. configuration of a pan coordinator register name register bits description short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 set node addresses rx_safe_mode 7 0 : disable frame protection 1 : enable frame protection slotted_operation 0 0 : if transceiver works in unslotted mode 1 : if transceiver works in slotted mode aack_i_am_coord 3 1 : device is pan coordinator aack_set_pd 5 0 : frame pending subfield is not set in fcf 1 : frame pending subfield is set in fcf aack_fvn_mode 7:6 controls the ack behavior, depend s on fcf frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames 0x01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2006 0x10 : acknowledges only frames with version number 0 or 1 or 2 0x11 : acknowledges all frames, independent of the fcf frame version number promiscuous mode the promiscuous mode is described in ieee 802.15.4- 2006, section 7.5.6.5. this mode is further illustrated in radio transceiver extended feature set on page 86 . according to ieee 802.15.4-2006 when in promiscuous mode, the mac sub layer shall pass received frames with correct fcs to the next higher layer without further processing. that implies that frames should never be acknowledg ed. only second level filter rules as defined by ieee 8 02.15.4-2006, section 7.5.6.2, are applied to the received frame. table 9-8 below shows the typical configuration of a device operat ing in promiscuous mode. table 9-8. configuration of promiscuous mode register name register bits description short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 each address shall be set: 0x00 aack_prom_mode 1 1 : enable promiscuous mode aack_dis_ack 4 1 : disable generation of acknowledgment 53 8266c-mcu wireless-08/11 ATMEGA128RFA1 register name register bits description aack_fvn_mode 7:6 controls the ack behavior, depend s on fcf frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames 0x01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2006 0x10 : acknowledges only frames with version number 0 or 1 or 2 0x11 : acknowledges all frames, independent of the fcf frame version number second level of filtering according to ieee 802.15. 4-2006, section 7.5.6.2, is applied to a received frame if the radio transceiver is in pro miscuous mode. however, a trx24_rx_end interrupt is issued even if the fcs is invalid. thus it is necessary to read bit rx_crc_valid of register phy_rssi after th e trx24_rx_end interrupt in order to verify the reception of a frame with a val id fcs. if a device, operating in promiscuous mode, receive s a frame with a valid fcs which in addition passed the third level filtering according to ieee 802.15.4-2006, section 7.5.6.2, an acknowledgement frame would be transmit ted. according to the definition of the promiscuous mode a received frame shall not be acknowledged even if it is requested. thus bit aack_dis_ack of register csma_s eed_1 has to be set to 1. in all receive modes a trx24_ami interrupt is issue d, when the received frame matches the node?s address according to the filter rules described in section "frame filtering" on page 55. alternatively, in rx_on state of the basic operatin g mode when a valid phr is detected a trx24_rx_start interrupt is generated an d the frame is received. the end of the frame reception is signalized with a trx 24_rx_end interrupt. at the same time the bit rx_crc_valid of register phy_rssi is u pdated with the result of the fcs check (see "overview" on page 67 ). the rx_crc_valid bit must be checked in order to dismiss corrupted frames according to the definition of the promiscuous mode. 9.4.2.3.3 configuration of non ieee 802.15.4 compli ant scenarios sniffer table 9-9 below shows a rx_aack configuration to setup a sniffer d evice. other rx_aack configuration bits should be set to their r eset values (see table 9-5 on page 50). all frames received are indicated by a trx24_r x_start and trx24_rx_end interrupt. bit rx_crc_valid of register phy_rssi is updated after frame reception with the result of the fcs check (see "overview" on page 67 ). the rx_crc_valid bit needs to be checked in order to dismiss corrupted f rames. table 9-9. configuration of a sniffer device register name register bits description aack_prom_mode 1 1 : enable promiscuous mode aack_dis_ack 4 1 : disable generation of acknowledgment this operating mode is similar to the promiscuous m ode. 54 8266c-mcu wireless-08/11 ATMEGA128RFA1 reception of reserved frames frames with reserved frame types (see section table 9-16 on page 64 ) can also be handled in rx_aack mode. this might be required whe n implementing proprietary, non-standard compliant protocols. it is an extensio n of the address filtering in rx_aack mode. received frames are either handled si milar to data frames or may be allowed to completely bypass the address filter. table 9-10 below shows the required configuration for a node to rece ive reserved frames and figure 9-19 on page 49 shows the corresponding flow chart. table 9-10. rx_aack configuration to receive reserved frame typ es register name register bits description short_addr_0/1 pan_addr_0/1 ieee_addr_0 ? ieee_addr_7 set node addresses rx_safe_mode 7 0 : disable frame protection 1 : enable frame protection aack_upld_res_ft 4 1 : enable reserved frame type reception aack_fltr_res_ft 5 filter reserved frame types like data frame type, see note below 0 : disable 1 : enable slotted_operation 0 0 : if transceiver works in un-slotted mode 1 : if transceiver works in slotted mode aack_i_am_coord 3 0 : device is not pan coordinator 1 : device is pan coordinator aack_dis_ack 4 0 : enable generation of acknowledgment 1 : disable generation of acknowledgment aack_fvn_mode 7:6 controls the ack behavior, depend s on fcf frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to ieee 802.15.4-2003 frames 0x01 : acknowledges only frames with version number 0 or 1, i.e. frames according to ieee 802.15.4-2006 0x10 : acknowledges only frames with version number 0 or 1 or 2 0x11 : acknowledges all frames, independent of the fcf frame version number there are two different options for handling reserv ed frame types. 1. aack_upld_res_ft = 1, aack_flt_res_ft = 0: any non-corrupted frame with a reserved frame type is indicated by a trx24_rx_end interrupt. no further address filterin g is applied on those frames. a trx24_ami interrupt is never generated and the ac knowledgment subfield is ignored. 2. aack_upld_res_ft = 1, aack_flt_res_ft = 1: 55 8266c-mcu wireless-08/11 ATMEGA128RFA1 if aack_flt_res_ft = 1 any frame with a reserved fr ame type is filtered by the address filter similar to a data frame as described in the standard. consequently, a trx24_ami interrupt is generated upon address match . a trx24_rx_end interrupt is only generated if the address matched and the frame was not corrupted. an acknowledgment is only send, when the ack request subfield was set in the received frame and a trx24_rx_end interr upt occurred. note that it is not allowed to set aack_fltr_res_ft = 1 and have register bit aack_fltr_res_ft set to 0. short acknowledgment frame (ack) start timing the bit aack_ack_time of register xah_ctrl_1 define s the symbol time between frame reception and transmission of an acknowledgme nt frame. table 9-11. overview of rx_aack configuration bits register name register bit description aack_ack_time 2 0 : standard compliant acknowledgement timing of 12 symbol periods. in slotted acknowledgement operatio n mode, the acknowledgment frame transmission can be triggered 6 symbol periods after reception of the f rame earliest. 1 : reduced acknowledgment timing of 2 symbol periods (32 s). note that this feature can be used in all scenarios , independent of other configurations. however, shorter acknowledgment timing is especiall y useful when using high data rate modes to increase battery lifetime and to impr ove the overall data throughput; see "high data rate modes" on page 87 for details. 9.4.2.4 frame filtering frame filtering is an evaluation whether or not a r eceived frame is dedicated for this node. to accept a received frame and to generate an address match interrupt (trx24_ami) a filtering procedure as described in i eee 802.15.4-2006 chapter 7.5.6.2. (third level of filtering) is applied to the frame. the radio transceiver?s rx_aack mode accepts only frames that satisfy all of the followi ng requirements (quote from ieee 802.15.4-2006, 7.5.6.2): 1. the frame type subfield shall not contain a rese rved frame type. 2. the frame version subfield shall not contain a r eserved value. 3. if a destination pan identifier is included in t he frame, it shall match macpanid or shall be the broadcast pan identifier (0xffff). 4. if a short destination address is included in th e frame, it shall match either macshortaddress or the broadcast address (0xffff). otherwise, if an extended destination address is included in the frame, it sh all match aextendedaddress. 5. if the frame type indicates that the frame is a beacon frame, the source pan identifier shall match macpanid unless macpanid is equal to 0xffff, in which case the beacon frame shall be accepted regardless of the source pan identifier. 6. if only source addressing fields are included in a data or mac command frame, the frame shall be accepted only if the device is the p an coordinator and the source pan identifier matches macpanid. the radio transceiver requires two additional rules : 1. the frame type indicates that the frame is not a n ack frame (refer to table 9-6 on page 51). 56 8266c-mcu wireless-08/11 ATMEGA128RFA1 2. at least one address field must be configured. address match, indicated by the trx24_ami interrupt is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: if (destination addressing mode = 0 or 1) and (sour ce addressing mode = 0) no trx24_ami interrupt is generated, refer to figure 9-26 on page 64 . this effectively causes all acknowledgement frames not to be announc ed which otherwise always pass the filter regardless of whether they are intended for this device or not. for backward compatibility to ieee 802.15.4-2003 th ird level filter rule 2 (frame version) can be disabled by the bits aack_fvn_mode of register csma_seed_1. frame filtering is available in extended and basic operating mode (see section "basic operating mode" on page 36); a frame passing the frame filtering gene rates an trx24_ami interrupt, if enabled. note: 1. filter rule 1 is affected by register bits aack_fltr_res_ft and aack_upld_res_ft (see register "xah_ctrl_1 ? transceiver acknowledgment frame control register 1" on page 12 1 ). 2. filter rule 2 is affected by register bits aack_ fvn_mode (see register "csma_seed_1 ? transceiver acknowledgment frame con trol register 2" on page 130 ). 9.4.2.4.1 rx_aack slotted operation ? slotted ackno wledgement the radio transceiver supports slotted acknowledgem ent operation according to ieee 802.15.4-2006, section 5.5.4.1. in rx_aack mode with bit slotted_operation of regis ter xah_ctrl_0 set, the transmission of an acknowledgement frame has to be controlled by the microcontroller. if an ack frame has to be transmitted the radio tra nsceiver expects writing slptr=1 to actually start the transmission. this waiting state is signaled 6 symbol periods after the reception of the last symbol of a data or mac comma nd frame by bits trac_status of register xah_ctrl_0, which are set to success_wa it_for_ack in that case. in networks using slotted operation the start of the a cknowledgment frame and thus the exact timing must be provided by the microcontrolle r. a timing example of an rx_aack transaction with bit slotted_operation of register xah_ctrl_0 set is shown in the next figure . the acknowledgement frame is ready to transmit 6 symbol times after the receptio n of the last symbol of a data or mac command frame. the transmission of the acknowledgem ent frame is initiated by the microcontroller by writing slptr=1 and starts 16s (t tr10 ) later. the interrupt latency t irq is specified in section "digital interface timing characteristics" on page 516 . 57 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-10. example timing of an rx_aack transaction for slotted operat ion rx/tx frame on air r x _a a c k _o n t r x_ st at e f ram e t ype r x _a ac k_o n r x/tx r x tx t r x 24_r x _e n d ir q r x t yp . processing d elay t ir q 51 2 0 7 04 tim e [ s] 64 1 026 d ata fram e (length = 10, a c k = 1) a c k f ram e s f d 96 s (6 sym bols) s lp tr t t r 1 0 t x r x s lp t r a c k transm ission initiated by m icrocontroller b u s y _r x _aa c k r x w aiting period signaled by register bits t r a c _s t a t u s t ir q t r x 24_t x _e n d if bit aack_ack_time of register xah_ctrl_1 is set, an acknowledgment frame can be sent already 2 symbol times after the reception of the last symbol of a data or mac command frame. 9.4.2.4.2 rx_aack mode timing a timing example of an rx_aack transaction is shown in the next figure. in this example a data frame of length 10 with an ack reque st is received. the radio transceiver changes to state busy_rx_aack after sfd detection. the completion of the frame reception is indicated by a trx24_rx_end interrupt. interrupts trx24_rx_start and trx24_ami are disabled in this e xample. the ack frame is automatically transmitted after a default wait peri od of 12 symbols (192 s), bit aack_ack_time = 0 (reset value). the interrupt late ncy t irq is specified in section "digital interface timing characteristics" on page 516 . figure 9-11. example timing of an rx_aack transaction rx/tx frame on air r x _a a c k _o n b u s y _r x _a a c k t r x _s t a t e f ram e t ype r x _a a c k _o n r x /t x r x tx tr x 24 _r x _e n d ir q r x t yp. p rocessing d elay t ir q 512 0 7 04 tim e [ s] 6 4 1 088 d ata f ram e (length = 10, a c k = 1) a c k f ram e s f d 192 s (12 sym bols) tr x 24_ tx _e n d t ir q if bit aack_ack_time of register xah_ctrl_1 is set, an acknowledgment frame is sent already 2 symbol times after the reception of the last symbol of a data or mac command frame. 58 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.4.2.5 tx_aret_on ? transmit with automatic retry and csma-ca retry figure 9-12. flow diagram of tx_aret t r x _ s t a t e = t x _ a r e t _ o n cs m a _ rctr = 0 t r x _ s t a t e = t x _ a r e t _ o n n y f a ilu re s u c ce ss n y fra m e _ rctr = 0 t ra n s m it f ra m e fra m e _ rc tr = fra m e _ rctr + 1 y n n y t r a c _ s t a t u s = n o _ a c k t r a c _ s t a t u s = s u c c e s s t r a c _ s t a t u s = c h a n n e l _ a c c e s s _ f a il u r e is su e t r x 2 4 _ t x _ e n d in te rru p t c c a r e su lt a c k re q u e ste d a c k va lid t r a c _ s t a t u s = s u c c e s s _ d a t a _ p e n d in g y n r e c e iv e a c k u n til tim e o u t y n t r x _ s t a t e = b u s y _ t x _ a r e t t r a c _ s t a t u s = in v a l id max_csm a_retries < 7 y n c sm a _ rctr > max_csma_retries y n o te 1 : if m a x _ c s m a _ r e t r ie s = 7 n o re try is p e rfo rm e d (s e e n o te 1 ) r a n d o m b a c k -o ff c sm a _ rc tr = c sm a _ rctr + 1 c c a s ta rt t x fra m e _ rc tr > m a x _ f r a m e _ r e t r ie s d a ta p e n d in g n 59 8266c-mcu wireless-08/11 ATMEGA128RFA1 overview the implemented tx_aret algorithm is shown in figure 9-12 on page 58. in tx_aret mode, the radio transceiver first execut es the csma-ca algorithm, as defined by ieee 802.15.4?2006, section 7.5.1.4, ini tiated by a transmit start event. if the channel is idle a frame is transmitted from the frame buffer. if the acknowledgement frame is requested the radio transc eiver additionally checks for an ack reply. a trx24_tx_end interrupt indicates the completion o f the tx_aret transmit transaction. description configuration and address bits are to be set in trx _off or pll_on state prior to switching to tx_aret mode. it is further recommende d to transfer the psdu data to the frame buffer in advance. the transaction is sta rted by either writing slptr=1 as described in section "transceiver pin register trxpr" on page 33 or writing a tx_start command to register trx_state. if the csma-ca detects a busy channel, it is retrie d as specified by bits max_csma_retries of register xah_ctrl_0. in case th at csma-ca does not detect a clear channel after max_csma_retries it ab orts the tx_aret transaction, issues a trx24_tx_end interrupt and sets the value of the trac_status register bits to channel_access_failure. during transmission of a frame the radio transceive r parses bit 5 (ack request) of the mac header (mhr) frame control field of the psdu da ta (psdu octet #1) to be transmitted to check if an ack reply is expected. if an ack is expected the radio transceiver automat ically switches into receive mode to wait for a valid ack reply. after receiving an ack frame the frame pending subfield of that frame is parsed and the status register bits t rac_status are updated accordingly (see table 9-16 below ). this receive procedure does not overwrite the frame buffer content. transmit data in the frame bu ffer is not changed during the entire tx_aret transaction. received frames other t han the expected ack frame are discarded. if no valid ack is received or after timeout of 54 symbol periods (864 s), the radio transceiver retries the entire transaction (includi ng csma-ca) until the maximum number of retransmissions as set by the bits max_fr ame_retries in register xah_ctrl_0 is exceeded. after that, the microcontroller may read the value of the bits trac_status of register trx_state to verify whether the transaction was suc cessful or not. the register bits are set according to the following cases: table 9-16. interpretation of the trac_status register bits value name description 0 success the transaction was responded by a valid ack, or, if no ack is requested, after a successful frame transmission 1 success_data_pending equivalent to success; indic ates pending frame data according to the mhr frame control field of the received ack response 3 channel_access_failure channel is still busy after max_csma_retries of csma-ca 60 8266c-mcu wireless-08/11 ATMEGA128RFA1 value name description 5 no_ack no acknowledgement frames were received during all retry attempts 7 invalid entering tx_aret mode sets trac_status = 7 note that if no ack is expected (according to the c ontent of the received frame in the frame buffer), the radio transceiver issues a trx24 _tx_end interrupt directly after the frame transmission has been completed. the valu e of the bits trac_status of register trx_state is set to success. a value of max_csma_retries = 7 initiates an immedi ate tx_aret transaction without performing csma-ca. this is required to sup port slotted acknowledgement operation. further the value max_frame_retries is i gnored and the tx_aret transaction is performed only once. a timing example of a tx_aret transaction is shown in figure 9-13 below . figure 9-13. example timing of a tx_aret transaction rx/tx frame on air tx_aret_on busy_tx_aret trx_state frametype tx_aret_on rx/tx rx rx_end irq typ. processing delay 16 s 672 0 x time [s] 128 x+352 slptr tx t irq data frame (length = 10, ack=1) ack frame 32 s t csm a-ca tx csma-ca rx note: 1. t csma-ca defines the random csma-ca processing time. here an example data frame of length 10 with an ack request is transmitted, see table 9-13 on page 61. after the transmission the radio transcei ver switches to receive mode and expects an acknowledgement response. during the whole transaction including frame transmit, wait for ack and ack receive the ra dio transceiver status register trx_status signals busy_tx_aret. a successful reception of the acknowledgment frame is indicated by the trx24_tx_end interrupt. the status register trx_sta tus changes back to tx_aret_on. the tx_aret status register trac_status changes as well to trac_status = success or trac_status = success_data _pending if the frame pending subfield of the received ack frame wa s set to 1. 9.4.2.6 interrupt handling the interrupt handling in the extended operating mo de is similar to the basic operating mode (see section "interrupt handling" on page 39). the microcontroller enables interrupts by setting the appropriate bit in regist er irq_mask. for rx_aack and tx_aret the following interrupts ( table 9-13 on page 61) inform about the status of a frame reception and transmiss ion: 61 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-13. interrupt handling in extended operating mode mode interrupt description trx24_rx_start indicates a phr reception trx24_ami issued at address match rx_aack trx24_rx_end signals completion of rx_aack transact ion if successful - a received frame must pass the address filter; - the fcs is valid tx_aret trx24_tx_end signals completion of tx_aret transaction both trx24_pll_lock entering rx_aack_on or tx_aret_ on state from trx_off state, the trx24_pll_lock interrupt signals that the transaction can be started rx_aack for rx_aack it is recommended to enable the trx24_r x_end interrupt. this interrupt is issued only if a frame passes the fram e filtering (see section "frame filtering" on page 55) and has a valid fcs. this is different to basic operating mode (see section "basic operating mode" on page 36). the use of the other interrupts is optional. on reception of a valid phr a trx24_rx_start interr upt is issued. the trx24_ami interrupt indicates an address match (see filter ru les in section "frame filtering" on page 55). the completion of a frame reception with a valid fcs is indicated by the trx24_rx_end interrupt. thus it can happen that a trx24_rx_start and/or a t rx24_ami interrupt are issued, but no trx24_rx_end interrupt. the end of an acknowledgment transmission is confir med by a trx24_tx_end interrupt. tx_aret in tx_aret interrupt trx24_tx_end is only issued af ter completing the entire tx_aret transaction. acknowledgement frames do not issue a trx24_rx_star t, trx24_ami or a trx24_rx_end interrupt. all other interrupts as described in section table 9-2 on page 35 are also available in extended operating mode. 9.4.2.7 register summary the following registers ( table 9-14 below ) are to be configured to control the extended operating mode: table 9-14. register summary register name description trx_status radio transceiver status, cca result trx_state radio transceiver state control, tx_aret status trx_ctrl_1 tx_auto_crc_on phy_cc_cca cca mode control, table 9-21 on page 71 cca_thres cca threshold settings, see "overview" on page 71 xah_ctrl_1 rx_aack control 62 8266c-mcu wireless-08/11 ATMEGA128RFA1 register name description ieee_addr7 ?. ieee_addr0 pan_id1 pan_id0 short_addr1 short_addr0 address filter configuration short address, pan-id and ieee address xah_ctrl_0 tx_aret control, retries value control csma_seed_0 csma-ca seed value csma_seed_1 csma-ca seed value, rx_aack control csma_be csma-ca back-off exponent control 9.5 functional description 9.5.1 introduction ? ieee 802.15.4-2006 frame forma t figure 9-14 below provides an overview of the physical layer (phy) f rame structure as defined by ieee 802.15.4. figure 9-15 on page 63 shows the frame structure of the medium access control (mac) layer. figure 9-14. ieee 802.15.4 frame format - phy-layer frame struct ure (ppdu) 9.5.1.1 phy protocol layer data unit (ppdu) 9.5.1.1.1 synchronization header (shr) the shr consists of a four-octet preamble field (al l zero), followed by a single byte start-of-frame delimiter (sfd) which has the predef ined value 0xa7. during transmit, the shr is automatically generated by the radio tra nsceiver, thus the frame buffer shall contain phr and psdu only. the transmission of the shr requires 160 s (10 sym bols). as the frame buffer access is normally faster than the over-air data rate, thi s allows the application software to initiate a transmission without having transferred the full frame data already. instead it is possible to subsequently write the frame content. during frame reception, the shr is used for synchro nization purposes. the matching sfd determines the beginning of the phr and the fol lowing psdu payload data. 9.5.1.1.2 phy header (phr) the phy header is a single octet following the shr. the least significant 7 bits denote the frame length of the following psdu, while the m ost significant bit of that octet is reserved, and shall be set to 0 for ieee 802.15.4 c ompliant frames. 63 8266c-mcu wireless-08/11 ATMEGA128RFA1 on receive the phr is returned as the first octet d uring frame buffer read access. even though the standard only defines frame lengths 127 bytes, the radio transceiver is able to transmit and receive frame length values >127. for ieee 802.15.4 compliant operation bit 8 has to be masked by software. the r eception of a valid phr is signaled by a trx24_rx_start interrupt. on transmit the phr has to be written first to the frame buffer. 9.5.1.1.3 phy payload (phy service data unit, psdu) the psdu has a variable length between 0 and amaxphypacketsize (127, maximum psdu size in octets) whereas the last two octets ar e used for the frame check sequence (fcs). the length of the psdu is signaled by the frame length field (phr) as described in table 9-15 below . the psdu contains the mac protocol layer data unit (mpdu). received frames with a frame length field set to 0x 00 (invalid phr) are not by an interrupt. table 9-15 below summarizes the type of payload versus the frame le ngth value. table 9-15. frame length field - phr frame length value payload 0 - 4 reserved 5 mpdu (acknowledgement) 6 ? 8 reserved 9 - amaxphypacketsize mpdu 9.5.1.2 mac protocol layer data unit (mpdu) figure 9-15 below shows the frame structure of the mac layer. figure 9-15. ieee 802.15.4 frame format - mac-layer frame struct ure (mpdu) 9.5.1.2.1 mac header (mhr) fields the mac header consists of the frame control field (fcf), a sequence number, and the addressing fields (which are of variable length and can even be empty in certain situations). 64 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.5.1.2.2 frame control field (fcf) the fcf consists of 16 bits, and occupies the first two octets of either the mpdu or the psdu, respectively. figure 9-26. ieee 802.15.4-2006 frame control field (fcf) bit [2:0] : describe the frame type. table 9-16 below summarizes frame types defined by ieee 802.15.4, section 7.2.1.1.1. table 9-16. frame control field ? frame type subfield frame control field bit assignments frame type value b 2 b 1 b 0 value description 000 0 beacon 001 1 data 010 2 acknowledge 011 3 mac command 100 ? 111 4 ? 7 reserved this subfield is used for address filtering by the third level filter rules. only frame types 0 ? 3 pass the third level filter rules (refer to s ection "frame filtering" on page 55 ). automatic address filtering of the radio transceive r is enabled when using the rx_aack mode (refer to "rx_aack_on ? receive with automatic ack" on page 4 7 ). a reserved frame (frame type value > 3) can be rece ived if bit aack_upld_res_ft of register xah_ctrl_1 is set. for details refer to ch apter "configuration of non ieee 802.15.4 compliant scenarios" on page 53 . address filtering is also provided in basic operating mode as explained in "basic operating mode" on page 36 . bit 3 : indicates whether security processing applies to this frame. bit 4 : is the ?frame pending? subfield. this field can b e set in an acknowledgment frame (ack) in response to a data request mac comma nd frame. this bit indicates that the node, which transmitted the ack, has more data to send to the node receiving the ack. for acknowledgment frames automatically generated b y the radio transceiver, this bit is set according to the content of bit aack_set_pd of register csma_seed_1 if the received frame was a data request mac command frame . bit 5 : forms the ?acknowledgment request? subfield. if t his bit is set within a data or mac command frame that is not broadcast, the recipi ent shall acknowledge the reception of the frame within the time specified by ieee 802.15.4 (i.e. within 192 s for non beacon-enabled networks). the radio transceiver parses this bit during rx_aac k mode and transmits an acknowledgment frame if necessary. in tx_aret mode this bit indicates if an acknowledg ement frame is expected after transmitting a frame. if this is the case, the rece iver waits for the acknowledgment frame, otherwise the tx_aret transaction is finishe d. 65 8266c-mcu wireless-08/11 ATMEGA128RFA1 bit 6 : the ?intra-pan? subfield indicates that in a fram e, where both, the destination and source addresses are present, the pan-id of the sou rce address filed is omitted. in rx_aack mode this bit is evaluated by the address f ilter logic of the radio transceiver. bit [11:10] : the ?destination addressing mode? subfield descri bes the format of the destination address of the frame. the values of the address modes are summarized in table 9-17 below according to ieee 802.15.4: table 9-17. frame control field ? destination and source addres sing mode frame control field bit assignments addressing mode b 11 b 10 b 15 b 14 value description 00 0 pan identifier and address fields are not pres ent 01 1 reserved 10 2 address field contains a 16-bit short address 11 3 address field contains a 64-bit extended addre ss if the destination address mode is either 2 or 3 (i .e. if the destination address is present), it always consists of a 16-bit pan-id fir st followed by either the 16-bit or 64-bit address as defined by the mode. bit [13:12] : the ?frame version? subfield specifies the versio n number corresponding to the frame. these register bits are reserved in ieee -802.15.4-2003. this subfield shall be set to 0 to indicate a frame compatible with ieee 802.15.4-2003 and 1 to indicate an ieee 802.15.4-2006 frame. all other subfield values shall be reserved for future use. the bit aack_fvn_mode of register csma_seed_1 contr ols the rx_aack behavior of frame acknowledgements. this register d etermines if, depending on the frame version number, a frame is acknowledged or no t. this is necessary for backward compatibility to ieee 802.15.4-2003 and fo r future use. even if frame version numbers 2 and 3 are reserved, it can be handled by the radio transceiver. for details refer to "csma_seed_1 ? transceiver acknowledgment frame con trol register 2" on page 130 . see ieee 802.15.4-2006, section 7.2.3 for details o n frame compatibility. table 9-18. frame control field ? frame version subfield frame control field bit assignments frame version b 13 b 12 value description 00 0 frames are compatible with ieee 802.15.4-2003 01 1 frames are compatible with ieee 802.15.4-2006 10 2 reserved 11 3 reserved bit [15:14] : the ?source addressing mode? subfield, with simil ar meaning as ?destination addressing mode? (refer to table 9-17 above ). the subfields of the fcf (bits 0?2, 3, 6, 10?15) af fect the address filter logic of the radio transceiver while executing a rx_aack operati on (see "rx_aack_on ? receive with automatic ack" on page 47 ). 66 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.5.1.2.3 frame compatibility between ieee 802.15.4 -2003 and ieee 802.15.4-2006 all unsecured frames according to ieee 802.15.4-200 6 are compatible with unsecured frames compliant with ieee 802.15.4-2003 with two e xceptions: a coordinator realignment command frame with the ?channel page? f ield present (see ieee 802.15.4- 2006 7.3.8) and any frame with a mac payload field larger than amaxmacsafepayloadsize octets. compatibility for secured frames is shown in the fo llowing table, which identifies the security operating modes for ieee 802.15.4-2006. table 9-19. frame control field ? security and frame version frame control field bit assignments security enabled b 3 frame version b 13 b 12 description 0 00 no security. frames are compatible between ieee 802.15.4-2003 and ieee 802.15.4-2006. 0 01 no security. frames are not compatible between ieee 802.15.4-2003 and ieee 802.15.4-2006. 1 00 secured frame formatted according to ieee 802.15.4-2003. this frame type is not supported in ieee 802.15.4-2006. 1 01 secured frame formatted according to ieee 802.15.4-2006 9.5.1.2.4 sequence number the one-octet sequence number following the fcf ide ntifies a particular frame, so that duplicated frame transmissions can be detected. whi le operating in rx_aack mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame. 9.5.1.2.5 addressing fields the addressing fields of the mpdu are used by the r adio transceiver for address matching indication. the destination address (if pr esent) is always first, followed by the source address (if present). each address field con sists of the intra pan-id and a device address. if both addresses are present and t he ?intra pan-id compression? subfield in the fcf is set to one, the source intra pan-id is omitted. note that in addition to these general rules ieee 8 02.15.4 further restricts the valid address combinations for the individual possible ma c frame types. for example the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed fo r acknowledgment frames. the address filter in the radio transceiver has been de signed to apply to ieee 802.15.4 compliant frames. it can be configured to handle ot her frame formats and exceptions. 9.5.1.2.6 auxiliary security header field the auxiliary security header specifies information required for security processing and has a variable length. this field determines how th e frame is actually protected (security level) and which keying material from the mac secur ity pib is used (see ieee 802.15.4-2006, 7.6.1). this field shall be pre sent only if the security enabled 67 8266c-mcu wireless-08/11 ATMEGA128RFA1 subfield b3 is set to one (see section "frame compatibility between ieee 802.15.4- 2003 and ieee 802.15.4-2006" on page 66). for details of its structure see ieee 802.15.4-2006, 7.6.2 auxiliary security header . 9.5.1.2.7 mac service data unit (msdu) this is the actual mac payload. it is usually struc tured according to the individual frame type. a description can be found in ieee 802.15.4-2 006, chapter 5.5.3.2. 9.5.1.2.8 mac footer (mfr) fields the mac footer consists of a two-octet frame checks um (fcs). for details refer to the following section "frame check sequence (fcs)" below . 9.5.2 frame check sequence (fcs) the frame check sequence (fcs) is characterized by: ? indicate bit errors based on a cyclic redundancy c heck (crc) of 16 bit length; ? uses international telecommunication union (itu) c rc polynomial; ? automatically evaluated during reception; ? can be automatically generated during transmission . 9.5.2.1 overview the fcs is intended for use at the mac layer to det ect corrupted frames at a first level of filtering. it is computed by applying an itu crc polynomial to all transferred bytes following the length field (mhr and msdu fields). t he frame check sequence has a length of 16 bit and is located in the last two byt es of a frame (mac footer, see figure 9-15 on page 63). the radio transceiver applies an fcs check on each received frame. the result of the fcs check is stored in bit rx_crc_valid of register phy_rssi. on transmit the radio transceiver generates and app ends the fcs bytes during the frame transmission. this behavior can be disabled b y setting the bit tx_auto_crc_on = 0 in register trx_ctrl_1. 9.5.2.2 crc calculation the crc polynomial used in ieee 802.15.4 networks i s defined by 1 ) ( 5 12 16 16 + + + = x x x x g the fcs shall be calculated for transmission using the following algorithm: let 1 2 2 1 1 0 ) ( ? ? ? ? + + + + = k k k k b x b x b x b x m k be the polynomial representing the sequence of bits for which the checksum is to be computed. multiply m(x) by x 16 giving the polynomial 16 ) ( ) ( x x m x n ? = divide ) ( x n modulo 2 by the generator polynomial g 16 (x) to obtain the remainder polynomial 15 14 14 1 15 0 ... ) ( r x r x r x r x r + + + + = the fcs field is given by the coefficients of the r emainder polynomial, r(x) . 68 8266c-mcu wireless-08/11 ATMEGA128RFA1 example: consider a 5 octet ack frame. the mhr field consist s of 0100 0000 0000 0000 0101 0110. the leftmost bit (b 0 ) is transmitted first in time. the fcs is in this case 0010 0111 1001 1110. the leftmost bit (r 0 ) is transmitted first in time. 9.5.2.3 automatic fcs generation the automatic fcs generation is performed with regi ster bit tx_auto_crc_on = 1 (reset value). this allows the radio transceiver to autonomously compute the fcs. for a frame with a frame length specified as n (3 n 127), the fcs is calculated on the first n -2 octets in the frame buffer and the resulting fcs field is transmitted in place of the last two octets from the frame buffer. if the automatic fcs generation of the radio transc eivers is enabled, the frame buffer write access can be stopped right after mac payload . there is no need to write fcs dummy bytes. in rx_aack mode, when a received frame needs to be acknowledged, the fcs of the ack frame is always automatically generated by the radio transceiver, independent of the tx_auto_crc_on setting. example: a frame transmission of length five with tx_auto_cr c_on set, is started with a frame buffer write access of five bytes (the last t wo bytes can be omitted). the first three bytes are used for fcs generation; the last t wo bytes are replaced by the internally calculated fcs. 9.5.2.4 automatic fcs check an automatic fcs check is applied on each received frame with a frame length n 2. the bit rx_crc_valid of register phy_rssi is set if the fcs of a received frame is valid. the register bit is updated when issuing a t rx24_rx_end interrupt and remains valid until a new frame reception causes the next t rx24_rx_end interrupt. in rx_aack mode, the radio transceiver rejects the frame and the trx24_rx_end interrupt is not issued if the fcs of the received frame is not valid. in tx_aret mode, the fcs and the sequence number of an ack are automatically checked. the ack is not accepted if one of those is not correct. 9.5.3 received signal strength indicator (rssi) the received signal strength indicator is character ized by: ? minimum rssi level is -90 dbm (rssi_base_val); ? dynamic range is 81 db; ? minimum rssi value is 0; ? maximum rssi value is 28. 9.5.3.1 overview the rssi is a 5-bit value indicating the receive po wer in the selected channel in steps of 3 db. no attempt is made to distinguish ieee 802 .15.4 signals from others. only the 69 8266c-mcu wireless-08/11 ATMEGA128RFA1 received signal strength is evaluated. the rssi pro vides the basis for an ed measurement. see section "energy detection (ed)" below for details. 9.5.3.2 reading rssi in basic operating mode the rssi value is valid in any receive state, and is updated every t tr25 = 2 s to register phy_rssi. it is not recommended to read the rssi value when u sing the extended operating mode. the automatically generated ed value should t hen be used (see section "energy detection (ed)" below ). 9.5.3.3 data interpretation the rssi value is a 5-bit value indicating the rece ive power in steps of 3 db and with a range of 0- 28. an rssi value of 0 indicates a receiver rf input po wer of p rf < -90 dbm. for an rssi value in the range of 1 to 28, the rf input power c an be calculated as follows: p rf = rssi_base_val + 3 ? (rssi - 1) [dbm] figure 9-17. mapping between rssi value and received input power -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 rssi receiver input power p rf [dbm] measured ideal 9.5.4 energy detection (ed) the energy detection (ed) module is characterized b y: ? 85 unique energy levels defined; ? 1 db resolution. 9.5.4.1 overview the receiver ed measurement is used by the network layer as part of a channel selection algorithm. it is an estimation of the rec eived signal power within the bandwidth of an ieee 802.15.4 channel. no attempt is made to identify or decode signals on the channel. the ed value is calculated by averaging rs si values over eight symbols (128 s). 70 8266c-mcu wireless-08/11 ATMEGA128RFA1 for high data rate modes the automated ed measureme nt duration is reduced to 32 s as described in "high data rate modes" on page 87 . the measurement period in these modes is still 128 s for manually initiated ed measurements as long as the receiver is in rx_on state. 9.5.4.2 measurement description there are two ways to initiate an ed measurement: ? manually, by writing an arbitrary value to registe r phy_ed_level, or ? automatically, after detection of a valid shr of a n incoming frame. for manually initiated ed measurements the radio tr ansceiver needs to be in one of the states rx_on or busy_rx. the end of the ed measurem ent is indicated by a trx24_cca_ed_done interrupt. the automatic ed measurement is started if a shr is detected. the end of the automatic measurement is not signaled by an interru pt. the measurement result is stored after t tr26 = 140 s (128 s measurement duration and processing delay) in register phy_ed_level. thus by using basic operating mode a valid ed value from the currently received frame is accessible 108 s after the trx24_rx_start inter rupt and remains valid until the next incoming frame generates a new trx24_rx_start interrupt or until another ed measurement is initiated. when using the extended operating mode it is recomm ended to mask the trx24_rx_start interrupt. hence the interrupt canno t be used as timing reference. a successful frame reception is signalized by the t rx24_rx_end interrupt. the minimum time span between a trx24_rx_end interrupt and a following sfd detection is t tr27 = 96 s due to the length of the shr. the ed value needs to be read within 224 s including the ed measurement time aft er the trx24_rx_end interrupt. otherwise it could be overwritten by the result of the next measurement cycle. this is important for time critical applications or if the trx24_rx_start interrupt is not used to indicate the reception of a frame. the values of the register phy_ed_level are: table 9-20. register bit phy_ed_level interpretation phy_ed_level description 0xff reset value 0x00 ? 0x53 ed measurement result of the last ed mea surement note: 1. it is not recommended to manually initiate an ed measurement when using the extended operating mode. 9.5.4.3 data interpretation the phy_ed_level is an 8-bit register. the ed value of the radio transceiver has a valid range from 0x00 to 0x53 with a resolution of 1 db. all other values do not occur. a value of 0xff indicates the reset value. a value of phy_ed_level = 0 indicates that the measured energy is less than -90 dbm (see param eter rssi_base_val in section "receiver characteristics" on page 517 ). due to environmental conditions (temperature, voltage, semiconductor parameters etc.) the calcula ted ed value has a maximum tolerance of 5 db, this is to be considered as con stant offset over the measurement range. an ed value of 0 indicates an rf input power of p rf -90 dbm. for an ed value in the range of 0 to 83, the rf input power can be calcula ted as follows: 71 8266c-mcu wireless-08/11 ATMEGA128RFA1 p rf = -90 + ed [dbm] figure 9-18. mapping between values in phy_ed_level and received input power -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 10 20 30 40 50 60 70 80 90 register phy_ed_level value receiver input power p rf [dbm] measured ideal 9.5.4.4 interrupt handling the trx24_cca_ed_done interrupt is issued at the en d of a manually initiated ed measurement. note that an ed request should only be initiated in one of the receive states. otherwise the radio transceiver generates a trx24_cca_ed_done interrupt but no ed measurement was performed. 9.5.5 clear channel assessment (cca) the main features of the clear channel assessment ( cca) module are: ? all 4 modes are available as defined by ieee 802.1 5.4-2006 in section 6.9.9; ? adjustable threshold for energy detection algorith m. 9.5.5.1 overview a cca measurement is used to detect a clear channel . four modes are specified by ieee 802.15.4-2006: table 9-21. cca mode overview cca mode description 1 energy above threshold . cca shall report a busy medium upon detecting any e nergy above the ed threshold. 2 carrier sense only . cca shall report a busy medium only upon the detect ion of a signal with the modulation and spreading characteristics of an ieee 802.15.4 compliant signal. the signal strength may be above or below the ed th reshold. 72 8266c-mcu wireless-08/11 ATMEGA128RFA1 cca mode description 0, 3 carrier sense with energy above threshold . cca shall report a busy medium using a logical comb ination of - detection of a signal with the modulation and spre ading characteristics of this standard and - energy above the ed threshold. where the logical operator may be configured as eit her or (mode 0) or and (mode 3). 9.5.5.2 configuration and cca request the cca modes are configurable via register phy_cc_ cca. usimg the basic operating mode, a cca request can b e initiated manually by setting cca_request = 1 of register phy_cc_cca, if the radi o transceiver is in any rx state. the current channel status (cca_status) and the cca completion status (cca_done) are accessible in register trx_status. the cca evaluation is done over eight symbol period s and the result is accessible t tr28 = 140 s (128 s measurement duration and processi ng delay) after the request. the end of a manually initiated cca measurement is indicated by a trx24_cca_ed_done interrupt. the sub-register cca_ed_thres of register cca_thres defines the received power threshold of the ?energy above threshold? algorithm . the threshold is calculated by rssi_base_val + 2 ? cca_ed_thres [dbm]. any receive d power above this level is interpreted as a busy channel. note that it is not recommended to manually initiat e a cca measurement when using the extended operating mode. 9.5.5.3 data interpretation the current channel status (cca_status) and the cca completion status (cca_done) are accessible in register trx_status. n ote, register bits cca_done and cca_status are cleared in response to a cca_req uest. the completion of a measurement cycle is indicated by cca_done = 1. if the radio transceiver detected no signal (idle channel) durin g the measurement cycle, the cca_status bit is set to 1. when using the ?energy above threshold? algorithm, any received power above cca_ed_thres level is interpreted as a busy channel . the ?carrier sense? algorithm reports a busy channel when detecting an ieee 802.1 5.4 signal above the rssi_base_val (see parameter rssi_base_val in "transceiver electrical characteristics" on page 516 ). the radio transceiver is also able to detect sig nals below this value, but the detection probability decreases with the signal power. 9.5.5.4 interrupt handling the trx24_cca_ed_done interrupt is issued at the en d of a manually initiated cca measurement. note: a cca request should only be initiated in the receive states of basic operating mode. otherwise the radio transceiver generates a trx24_c ca_ed_done interrupt and sets the register bit cca_done = 1 even if no cca m easurement was performed. 73 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.5.5.5 measurement time the response time for a manually initiated cca meas urement depends on the receiver state. in rx_on state the cca measurement is done over eig ht symbol periods and the result is accessible 140 s after the request (see section "configuration and cca request" on page 72). in busy_rx state the cca measurement duration depen ds on the cca mode and the cca request relative to the reception of an shr. th e end of the cca measurement is indicated by a trx24_cca_ed_done interrupt. the var iation of a cca measurement period in busy_rx state is described in table 9-22 below . table 9-22. cca measurement period and access in busy_rx state cca mode request within ed measurement (1) request after ed measurement energy above threshold . 1 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. carrier sense only . 2 cca result is immediately available after request. carrier sense with energy above threshold (and) . 3 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. carrier sense with energy above threshold (or) . 0 cca result is available after finishing automated ed measurement period. cca result is immediately available after request. note: 1. after receiving the shr an automated ed me asurement is started with a length of 8 symbol periods (psdu rate 250 kb/s), refer to sec tion "energy detection (ed)" on page 69. this automated ed measurement must be fin ished to provide a result for the cca measurement. only one automated ed meas urement per frame is performed. it is recommended to perform cca measurements in rx _on state only. to avoid accidental switching to busy_rx state the shr detec tion can be disabled by setting bit rx_pdt_dis of register rx_syn. refer to section "receiver (rx)" on page 75 for details. the receiver remains in rx_on state to per form a cca measurement until the register bit rx_pdt_dis is set back to continue the frame reception. in this case the cca measurement duration is 8 symbol periods. 9.5.6 link quality indication (lqi) according to ieee 802.15.4 the lqi measurement is a characterization of the strength and/or quality of a received packet. the measuremen t may be implemented using receiver ed, a signal-to-noise ratio estimation or a combination of these methods. the use of the lqi result by the network or application layers is not specified in this standard. lqi values shall be an integer ranging fr om 0x00 to 0xff. the minimum and maximum lqi values (0x00 and 0xff) should be associ ated with the lowest and highest quality compliant signals, respectively, an d lqi values in between should be uniformly distributed between these two limits. 9.5.6.1 overview the lqi measurement of the radio transceiver is imp lemented as a measure of the link quality which can be described with the packet erro r rate (per) of this link. a lqi value 74 8266c-mcu wireless-08/11 ATMEGA128RFA1 can be associated with an expected packet error rat e. the per is the ratio of erroneous received frames to the total number of received fra mes. a per of zero indicates no frame error whereas at a per of one no frame was re ceived correctly. the radio transceiver uses correlation results of m ultiple symbols within a frame to determine the lqi value. this is done for each rece ived frame. the minimum frame length for a valid lqi value is two octets psdu. lq i values are integers ranging from 0 to 255. the following figure shows an example of a conditio nal packet error rate when receiving a certain lqi value. figure 9-19. conditional packet error rate versus lqi 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 50 100 150 200 250 per lqi the values are taken from received frames of psdu l ength of 20 octets on transmission channels with reasonable low multipath delay spreads. if the transmission channel characteristic has a higher multipath delay spread than assumed in the example, the per is slightly higher for a certain l qi value. since the packet error rate is a statistical value, the per shown in figure 9-19 above is based on a huge number of transactions. a reliable estimation of the packe t error rate cannot be based on a single or a small number of lqi values. 9.5.6.2 request a lqi measurement the lqi byte can be obtained after a frame has been received by the radio transceiver. one additional byte is automatically attached to th e received frame containing the lqi value. this information can also be read via frame buffer read access, see "user accessible frame content" on page 79 . the lqi byte can be read after the trx24_rx_end interrupt. 9.5.6.3 data interpretation according to ieee 802.15.4 a low lqi value is assoc iated with low signal strength and/or high signal distortions. signal distortions are mainly caused by interference signals and/or multipath propagation. high lqi valu es indicate a sufficient high signal power and low signal distortions. 75 8266c-mcu wireless-08/11 ATMEGA128RFA1 note that the received signal power as indicated by the received signal strength indication (rssi) value or energy detection (ed) va lue of the radio transceiver do not characterize the signal quality and the ability to decode a signal. as an example, a received signal with an input powe r of about 6 db above the receiver sensitivity likely results in a lqi value close to 255 for radio channels with very low signal distortions. for higher signal power the lqi value becomes independent of the actual signal strength. this is because the packet error rate for these scenarios tends towards zero and further increased signal strength i.e. increasing the transmission power does not decrease the error rate any further. in this case rssi or ed can be used to evaluate the signal strength and the link m argin. zigbee networks often require the identification of the ?best? routing between two nodes. both the lqi and the rssi/ed can be used for this, dependent on the optimization criteria. if a low packet error rate ( corresponding to high throughput) is the optimization criteria then the lqi value should be taken into consideration. if a low transmission power or the link margin is the optimi zation criteria then the rssi/ed value is also helpful. combinations of lqi, rssi and ed are possible for r outing decisions. as a rule of thumb rssi and ed values are useful to differentiat e between links with high lqi values. transmission links with low lqi values shou ld be discarded for routing decisions even if the rssi/ed values are high. this is because rssi and ed do not say anything about the possibility to decode a sign al. it is only an information about the received signal strength whereas the source can be an interferer. 9.6 module description 9.6.1 receiver (rx) 9.6.1.1 overview the receiver is split into an analog radio front-en d and a digital base band processor (rx bbp) according to the following figure. the dig ital base band processor and the control engine are connected to the frame buffer an d control registers which are located in the microcontroller i/o memory space (se e "i/o memory" on page 26 and "transceiver to microcontroller interface" on page 32 ). figure 9-20. receiver block diagram ln a ppf bpf lim iter r x adc ag c r ssi r fp r fn analog d om ain d igital d om ain rx bbp fram e buffer lo c ontrol c i/f registers $01ff $0180 $017f $0140 i/o m em ory space the differential rf signal is amplified by a low no ise amplifier (lna), filtered (ppf) and down converted to an intermediate frequency by a mi xer. channel selectivity is performed using an integrated band pass filter (bpf ). a limiting amplifier (limiter) provides sufficient gain to overcome the dc offset of the succeeding analog-to-digital 76 8266c-mcu wireless-08/11 ATMEGA128RFA1 converter (rx adc) and generates a digital rssi sig nal. the adc output signal is sampled and processed further by the digital base b and receiver (rx bbp). the rx bbp performs additional signal filtering and signal synchronization. the frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. the receiver is designed to handle frequency and symbol rate deviations up to 120 ppm caused by combined receiver and transmitter deviations. for details re fer to chapter "general rf specifications" on page 516 . finally the signal is demodulated and the data are stored in the frame buffer. in basic operating mode (see "basic operating mode" on page 36 ), the reception of a frame is indicated by a trx24_rx_start interrupt. a ccordingly its end is signalized by a trx24_rx_end interrupt. based on the quality o f the received signal a link quality indicator (lqi) is calculated and appended to the frame. for details refer to. additional signal processing is applied to the fram e data to provide further status information like ed value (register phy_ed_level) a nd fcs correctness (register phy_rssi). beyond these features the extended operating mode o f the radio transceiver supports address filtering and pending data indication. for details refer to "extended operating mode" on page 44. 9.6.1.2 frame receive procedure the frame receive procedure including the radio s s etup for reception and reading psdu data from the frame buffer is described in "frame receive procedure" on page 85. 9.6.1.3 configuration in basic operating mode the receiver is enabled by writing command rx_on to the trx_cmd bits of register trx_state in the states tr x_off or pll_on. similarly in extended operating mode the receiver is enabled for rx_aack operation from the states trx_off or pll_on by writing the command rx_ aack_on. there is no additional configuration required to receive ieee 8 02.15.4 compliant frames when using the basic operating mode. however, the frame recept ion in the extended operating mode requires further register configurations. for details refer to "extended operating mode" on page 44 . the receiver has an outstanding sensitivity perform ance of -100 dbm. at certain environmental conditions or for high data rate mode s (see "high data rate modes" on page 87) it may be useful to manually decrease this sensitiv ity. this is achieved by adjusting the detector threshold of the synchroniza tion header using the rx_pdt_level bits of register rx_syn. received sign als with a rssi value below the threshold do not activate the demodulation proc ess. furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. a dynamic frame buffer protection is enabled with r egister bit rx_safe_mode (trx_ctrl_2) set (refer to "dynamic frame buffer protection" on page 92 ). after a frame has been received, the buffer is protected fo r new incoming frames and the receiver remains in rx_on or rx_aack_on state until the rx_safe_mode bit is cleared by the controller. the frame buffer content is only protected if the fcs is valid. a static frame buffer protection is enabled with bi t rx_pdt_dis of register rx_syn set. the receiver remains in rx_on or rx_aack_on st ate and no further shr is detected until the register bit rx_pdt_dis is set b ack. 77 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.6.2 transmitter (tx) 9.6.2.1 overview the transmitter consists of a digital base band pro cessor (tx bbp) and an analog front end as shown in the following figure. figure 9-21. transmitter block diagram pll ? tx m odulation pa ext. r f front-end and output power c ontrol d ig3/4 r fp r fn tx d ata analog d om ain tx bbp control buf d igital dom ain fram e buffer c i/f r egisters i/o m em ory space $01ff $017f $0180 $0140 the tx bbp reads the frame data from the frame buff er and performs the bit-to- symbol and symbol-to-chip mapping as specified by i eee 802.15.4 in section 6.5.2. the o-qpsk modulation signal is generated and fed i nto the analog radio front end. the fractional-n frequency synthesizer (pll) conver ts the baseband transmit signal to the rf signal which is amplified by the power ampli fier (pa). the pa output is internally connected to bidirectional differential antenna pin s (rfp, rfn) so that no external antenna switch is needed. 9.6.2.2 frame transmit procedure the frame transmit procedure including writing psdu data in the frame buffer and initiating a transmission is described in section "frame transmit procedure" on page 85 . the controller must ensure to provide valid frame d ata before starting the frame transmission. for save operation, it is recommended to write the complete frame into the frame buffer before starting the frame transmis sion. 9.6.2.3 configuration the maximum output power of the transmitter is typi cally +3.5 dbm. the output power can be configured via the tx_pwr bits of register p hy_tx_pwr. the output power of the transmitter can be controlled over a 20 db rang e. a transmission can be started from pll_on or tx_are t_on state by writing ?1? to bit slptr of the trxpr register or by writing tx_start command to the trx_cmd bits of register trx_state. 9.6.2.4 tx power ramping the pa buffer and pa are enabled sequentially to op timize the output power spectral density (psd). a timing example using default setti ngs illustrates the sequence in the next figure. in this example the transmission is in itiated with the rising edge of the slptr bit. the radio transceiver state changes from pll_on to busy_tx. the modulation starts 16 s after slptr. 78 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-22. tx power ramping 0 6 8 10 slptr trx_state pll_o n 2 12 14 16 18 length [ s] pa buffer 4 pa pa_buf_lt pa_lt m odulation 1 1 1 1 1 1 0 0 0 bu sy_tx when using an external rf front-end (refer to "rx/tx indicator" on page 91 ) it may be required to adjust the startup time of the external pa relative to the internal building blocks to optimize the overall psd. this can be ach ieved using register bits pa_buf_lt and pa_lt of register phy_tx_pwr. 9.6.3 frame buffer the radio transceiver contains a 128 byte dual port sram. one port of the frame buffer is directly connected to the controller i/o space. therefore random access to single frame bytes is possible. the other port connects to the internal transmitter and receiver modules. both ports are independent and simultaneou sly accessible for data communication. the frame buffer uses the controller i/o address sp ace 0x180 to 0x1ff for rx and tx operation of the radio transceiver and can keep one ieee 802.15.4 rx or one tx frame of maximum length at a time. frame buffer access is only possible if the radio t ransceiver is enabled (prtrx24 bit in the power reduction register prr1 is not set) and n ot in sleep state. 9.6.3.1 data management data in the frame buffer (received data or data to be transmitted) remain valid as long as: ? no new frame or other data are written into the bu ffer; ? no new frame is received (in any busy_rx state); ? no state change into radio transceiver sleep state is made; ? no radio transceiver reset (see bit trxrst in "trxpr ? transceiver pin register" on page 171 ) or system reset took place; ? bit prtrx24 in register "prr1 ? power reduction register 1" on page 169 is not set; by default there is no protection of the frame buff er against overwriting. if a frame is received during a frame buffer read access of a pre viously received frame, the stored data might be overwritten. finally the application software should check the t ransferred frame data integrity by a fcs check. the state of the radio transceiver should be change d to pll_on state after reception to protect the frame buffer content against overwritin g with new, incoming frames. this can be achieved by writing immediately the command pll_on to the trx_cmd bits of register trx_state after receiving the frame indica ted by a trx24_rx_end interrupt. 79 8266c-mcu wireless-08/11 ATMEGA128RFA1 alternatively dynamic frame buffer protection can b e used to protect received frames against overwriting. for details refer to "dynamic frame buffer protection" on page 92 . both procedures do not protect the frame buffer fro m overwriting by the application software. in extended operating mode during tx_aret operation (see "tx_aret_on ? transmit with automatic retry and csma-ca retry" on page 58 ) the radio transceiver switches to receive if an acknowledgement of a prev iously transmitted frame was requested. during this period received frames are e valuated but not stored in the frame buffer. this allows the radio transceiver to wait f or an acknowledgement frame and retry the frame transmission without writing the fr ame data to the frame buffer again. a radio transceiver state change except a transitio n to radio transceiver sleep state or a radio transceiver reset does not affect the frame buffer content. the frame buffer is powered off and the stored data gets lost if the radio transceiver is forced into radio transceiver sleep state. access conflicts may occur when reading and writing data simultaneously at the two independent ports of the frame buffer tx/rx bbp and controller interface. 9.6.3.2 user accessible frame content the radio transceiver supports an ieee 802.15.4 com pliant frame format as shown in the following figure. figure 9-31. transceiver frame structure preamble sequence sfd phr (1) payload lqi (2) fcs 0 4 5 6 y + 3 y + 5 y + 6 frame access shr not accesible rx: frame buffer content phy generated length [octets] duration 4 octets / 128 s 1 y octets / y ? 32 s ( y <= 128) 1 tx: frame buffer content notes: 1. stored into frame buffer for tx operation 2. stored into frame buffer during frame reception. a frame comprises two sections. the radio transceiv er internally generated shr field and the user accessible part are stored in the fram e buffer. the shr contains the preamble and the sfd field. the variable frame sect ion contains the phr and the psdu including the fcs (see "overview" on page 67 ). the frame buffer content differs depending on the d irection of the communication (receive or transmit). to access the data follow th e procedures described in "radio transceiver usage" on page 84 . during frame reception, the payload and the link qu ality indicator (lqi) value of a successfully received frame are stored in the frame buffer. the radio transceiver appends the lqi value to the frame data after the l ast received octet. information of the frame length is not stored in the frame buffer. the frame length information is located in register tst_rx_length. the shr (except the sfd used to generate the last o ctet of the shr) can generally not be read by the application software. 80 8266c-mcu wireless-08/11 ATMEGA128RFA1 the phr and the psdu need to be stored in the frame buffer for frame transmission. the phr byte is the first byte in the frame buffer (address 0x180) and must be calculated based on the phr and the psdu. the maxim um frame size supported by the radio transceiver is 128 bytes. if the tx_auto_ crc_on bit is set in register phy_tx_pwr, the fcs field of the psdu is replaced b y the automatically calculated fcs during frame transmission. there is no need to write the fcs field when using the automatic fcs generation. manipulating individual bytes of the frame buffer i s simply possible by accessing the appropriate buffer address. the minimum frame length supported by the radio tra nsceiver for non ieee 802.15.4 compliant frames is one byte (frame length field + 1 byte of data). 9.6.4 battery monitor (batmon) the main features of the battery monitor are: ? configurable voltage threshold range from 1.7v to 3.675v ? generates an interrupt when supply voltage drops b elow the threshold 9.6.4.1 overview the battery monitor (batmon) detects and indicates a low supply voltage of evdd. this is done by comparing the voltage of evdd with a configurable, internal threshold voltage. a simplified schematic of the batmon with the most important input and output signals is shown in the following figure. figure 9-24. simplified schematic of batmon batmon_hr batmon_vth 4 evdd threshold voltage batmon_ok ?1? batmon_irq for input-to-output mapping see batmon register dac + - d q clear 9.6.4.2 configuration the battery monitor can be configured using the bat mon register. register subfield batmon_vth sets the threshold voltage. it is config urable with a resolution of 75 mv in the upper voltage range (batmon_hr = 1) and with a resolution of 50 mv in the lower voltage range (batmon_hr = 0). 9.6.4.3 data interpretation the bit batmon_ok of register batmon monitors the c urrent value of the battery voltage: ? if batmon_ok = 0 then the battery voltage is lower than the threshold voltage; ? if batmon_ok = 1 then the battery voltage is highe r than the threshold voltage; 81 8266c-mcu wireless-08/11 ATMEGA128RFA1 the value batmon_ok should be read out to verify th e current supply voltage value after setting a new threshold. note: the battery monitor is inactive during sleep states. refer to status register trx_status for details. 9.6.4.4 interrupt handling a supply voltage drop below the configured threshol d value is indicated by the bat_low interrupt. the bat_low status bit as well as the batlow_en bit is located in the batmon register. if batlow_en =0, no irq is issued, but the status flag is set if the battery low event occurs. the interrupt is only issued if batmon_ok changes f rom 1 to 0 and the event is stored until the irq handler is called or the bat_low irq is cleared manually by writing ?1? to the bat_low status flag. no interrupt is generated when: ? the battery voltage is below the default 1.8v thre shold at power up (batmon_ok was never 1) or ? a new threshold is set which is still above the cu rrent supply voltage (batmon_ok remains 0). noise or temporary voltage drops may generate unwan ted interrupts when the battery voltage is close to the programmed threshold voltag e. to avoid this: ? disable the bat_low interrupt with the batlow_en b it in the batmon register and treat the battery as empty or ? set a lower threshold value. 9.6.5 crystal oscillator (xosc) the main features of the crystal oscillator are: ? amplitude controlled 16 mhz generation; ? 215 s typical settling time after leaving sleep s tate; ? configurable trimming with a capacitance array; 9.6.5.1 overview the crystal oscillator generates the reference freq uency for the radio transceiver. all other internally generated frequencies of the radio transceiver are derived from this unique frequency. the overall system performance is therefore critically determined by the accuracy of the crystal reference frequency. th e external components of the crystal oscillator should be selected carefully and the rel ated board layout should be done with caution as described in section "application circuits" on page 495. the register xosc_ctrl provides access to the contr ol signals of the oscillator. two operating modes are supported. it is recommended to use the integrated oscillator setup as described in figure 9-25 on page 82. nevertheless a reference frequency can be fed to the internal circuitry by using an extern al clock reference as shown in figure 9-26 on page 83. 9.6.5.2 integrated oscillator setup the output frequency of the internal oscillator dep ends on the load capacitance between the crystal pins xtal1 and xtal2. the total load capacitance c l must be equal to the specified load capacitance of the crys tal itself. it consists of the external capacitors cx and parasitic capacitances connected to the xtal nodes. 82 8266c-mcu wireless-08/11 ATMEGA128RFA1 the following figure shows all parasitic capacitanc es, such as pcb stray capacitances and the pin input capacitance summarized to c par . figure 9-25. simplified xosc schematic with external components cx cx 16mhz xtal2 xtal1 evdd c trim c trim c par c par ic internal pcb xtal_trim[3:0] evdd v evdd xtal_trim[3:0] additional internal trimming capacitors c trim are available. any value in the range from 0 pf to 4.5 pf with a 0.3 pf resolution is selectab le using xtal_trim of register xosc_ctrl. to calculate the total load capacitance, the following formula can be used c l = 0.5 ? (cx + c trim + c par ). the trimming capacitors provide the possibility to reduce frequency deviations caused by variations of the production process or by toler ances of external components. note that the oscillation frequency can only be reduced by increasing the trimming capacitance. the frequency deviation caused by one step of c trim decreases with increasing values of the crystal load capacitor. an amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal type s. enabling the crystal oscillator after leaving sleep state causes a slightly higher curren t during the amplitude build-up phase to guarantee a short start-up time. the curre nt is reduced to the amount necessary for a robust oscillation during stable op eration. this also keeps the drive level of the crystal low. crystals with a higher load capacitance are general ly less sensitive to parasitic pulling effects caused by variations of external components or board and circuit parasitics. on the other hand a larger crystal load capacitance re sults in a longer start-up time and a higher steady state current consumption. 9.6.5.3 external reference frequency setup when using an external reference frequency, the sig nal must be connected to pin xtal1 as indicated in figure 9-26 on page 83 and the bits xtal_mode of register xosc_ctrl need to be set to the external oscillator mode. the oscillation peak-to- peak amplitude shall between 100 mv and 500 mv, the optimum range is between 400 mv and 500 mv. pin xtal2 should not be wired 83 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-26. setup for using an external frequency reference xtal2 xtal1 ic internal pcb 16 mhz 9.6.6 frequency synthesizer (pll) the main features of the phase-locked loop are: ? generate rx/tx frequencies for all 2.4 ghz channel s of ieee 802.15.4; ? autonomous calibration loops for stable operation within the operating range; ? two pll-interrupts for status indication; ? fast pll settling to support frequency hopping; 9.6.6.1 overview the pll generates the rf frequencies for the radio transceiver. during receive operation the frequency synthesizer works as a loca l oscillator for the receive frequency of the radio transceiver. during transmit operation the voltage-controlled oscillator (vco) is directly modulated to generate the rf tran smit signal. the frequency synthesizer is implemented as a fractional-n pll. two calibration loops ensure correct pll functional ity within the specified operating limits. 9.6.6.2 frequency agility when the pll is enabled during state transition fro m trx_off to pll_on the settling time is typically t tr4 = 110 s including the settling time of the analog voltage regulator (avreg) and the pll self calibration (refer to table 9-8 on page 43 table 9-8). a lock of the pll is indicated with a trx24_pll_lock inter rupt. switching between 2.4 ghz ism band channels in pll_ on or rx_on states is typically done within t tr20 = 11 s. this makes the radio transceiver highly s uitable for frequency hopping applications. the pll frequency is changed to the transmit freque ncy within t tr23 = 16 s after starting the transmit procedure and before starting the transmission. after the transmission the pll settles back to the receive fr equency within t tr24 = 32 s. this frequency step does not generate a trx24_pll_lock o r trx24_pll_unlock interrupt within these time spans. 9.6.6.3 calibration loops due to temperature, supply voltage and part-to-part variations of the radio transceiver the vco characteristics diverge. two automated cont rol loops are implemented to ensure a stable operation: center frequency (cf) tu ning and delay cell (dcu) calibration. both calibration loops are initiated a utomatically when the pll is enabled during state transition from trx_off to pll_on. the center frequency calibration is additionally initiated when the pll changes to a ce nter frequency of another channel. it is recommended to initiate the calibration loops manually if the pll operates for a long time on the same channel e.g. more than 5 min or the operating temperature 84 8266c-mcu wireless-08/11 ATMEGA128RFA1 changes significantly. both calibration loops can b e initiated manually by setting pll_cf_start = 1 of register pll_cf and pll_dcu_sta rt = 1 of register pll_dcu. the device must be in pll_on or rx_on stat e to start the calibration. the completion of the center frequency tuning is indica ted by a trx24_pll_lock interrupt. both calibration loops may be run simultaneously. 9.6.6.4 interrupt handling two different interrupts indicate the pll status. t he trx24_pll_lock interrupt indicates that the pll has locked. the trx24_pll_un lock interrupt indicates an unexpected unlock condition. a trx24_pll_lock interrupt is supposed to occur in the following situations: ? state change from trx_off to pll_on / rx_on/ rx_ aack_on/ tx_aret_on; ? channel change in states pll_on / rx_on/ rx_aack_o n/ tx_aret_on; any other occurrences of pll interrupts indicate er roneous behavior and require checking of the actual device status. the state transition from busy_tx to pll_on after s uccessful transmission does not generate a trx24_pll_lock interrupt within the sett ling period. 9.6.6.5 rf channel selection the pll is designed to support 16 channels in the 2 .4 ghz ism band with channel spacing of 5 mhz according to ieee 802.15.4. the ce nter frequency of these channels is defined as follows: f c = 2405 + 5 ( k ? 11) in [mhz], for k = 11, 12 ... 26 where k is the channel number. the channel k is selected by the channel bits of register phy_cc _ca. 9.6.7 automatic filter tuning (ftn) the ftn is incorporated to compensate device tolera nces for temperature, supply voltage variations as well as part-to-part variatio ns of the radio transceiver. the filter- tuning result is used to correct the transfer funct ion of the analog baseband filter and the time constant of the pll loop-filter (refer to "general circuit description" on page 31 ). an ftn calibration cycle is initiated automatically when entering the radio transceiver trx_off state from the sleep or reset state. although receiver and transmitter are very robust a gainst these variations, it is recommended to initiate the ftn manually if the rad io transceiver does not use the sleep state. a calibration cycle is to be initiated in states trx_off, pll_on or rx_on if necessary. this applies in particular to t he high data rate modes with a much higher sensitivity to variations of the bpf tr ansfer function. the recommended calibration interval is 5 min or less. 9.7 radio transceiver usage this section describes the basic procedures to rece ive and transmit frames with the radio transceiver. 85 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.7.1 frame receive procedure a frame reception comprises of two actions: the phy listens for a frame, receives and demodulates the frame to the frame buffer and signa lizes its reception to the application software. the application software read s the available frame data from the frame buffer after or during the progress of the fr ame reception. while in state rx_on or rx_aack_on the radio transc eiver searches for incoming frames on the selected channel. first a trx24_rx_st art interrupt indicates the detection of an ieee 802.15.4 compliant frame assum ing the appropriate interrupts are enabled. the frame reception is completed when issu ing the trx24_rx_end interrupt. different frame buffer read access scenarios are re commended for: ? non-time critical applications: read access starts after the trx24_rx_end interrupt; ? time-critical applications: read access starts aft er the trx24_rx_start interrupt; the controller must ensure to read valid frame buff er contents. reading frame data before frame reception is finished can lead to inva lid data, if buffer regions are accessed which are not yet updated with the new fra me. while receiving a frame the data needs to be primar ily stored in the frame buffer before reading it. this is ensured by accessing the first frame buffer byte at least 32 s after the trx24_rx_start interrupt. it is recommended for operations considered to be n ot time-critical to wait for the trx24_rx_end interrupt before starting a frame buff er read access. the following figure illustrates the frame receive procedure usin g the trx24_rx_end interrupt. figure 9-27. transactions between radio transceiver and microcon troller during receive transceiver microcontroller irq issued (rx_start) irq issued (rx_end) read frame data (frame buffer access) read tst_frame_length register (register access) critical protocol timing could require starting the frame buffer read access after the trx24_rx_start interrupt. the first byte of the fra me data can be read 32 s after the trx24_rx_start interrupt. the application softw are must ensure to read slower than the frame is received. otherwise a frame buffe r under-run occurs and the frame data may be not valid. 9.7.2 frame transmit procedure a frame transmission comprises of the two actions f rame buffer write access and transmission of the frame buffer content. both acti ons can be run in parallel if required by critical protocol timing. figure 9-28 on page 86 illustrates the frame transmit procedure by consecu tively writing and transmitting the frame. the frame transmission is initiated writing slptr or writing 86 8266c-mcu wireless-08/11 ATMEGA128RFA1 command tx_start to register trx_state after a fram e buffer write access and while the radio transceiver is in state pll_on or t x_aret_on. the trx24_tx_end interrupt indicates the completion of the transacti on. figure 9-28. transaction between radio transceiver and microcont roller during transmit transceiver microcontroller write frame data (frame buffer access) write trx_cmd = tx_start, or write slptr (register access) irq issued (tx_end) alternatively a frame transmission can be started f irst, followed by the frame buffer write access (psdu data) as shown in figure 9-29 below . this is applicable for time critical applications. a transmission is initiated either by writing slptr or by writing the tx_start command to the trx_cmd bits of register trx_state. the radio transceiver then starts transmitting the shr which is internally gen erated. this first phase requires 16 s for pll settling an d 160 s for shr transmission. the phr must be available in the frame buffer before th is time elapses. furthermore the frame buffer must be filled faster than the frame i s transmitted to prevent a buffer under-run. figure 9-29. time optimized frame transmit procedure write frame data (frame buffer access) write trx_cmd = tx_start, or write slptr (register access) transceiver microcontroller irq issued (tx_end) 9.8 radio transceiver extended feature set 9.8.1 random number generator the radio transceiver incorporates a 2-bit, noise o bserving, true random number generator to be used to: ? generate random seeds for csma-ca algorithm (see "extended operating mode" on page 44 ); 87 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? generate random values for aes key generation (see "security module (aes)" on page 93 ); the values are stored in bits rnd_value of register phy_rssi. the random number is updated every t tr29 = 1 s in basic operation mode receive states with locked pll. note, if the pll is not locked or unlocks in receiv e states, the rnd_value is zero. 9.8.2 high data rate modes the main features of the high data rate modes are: ? high data rate communication up to 2 mb/s; ? support of basic and extended operating mode; ? support of other features of the extended feature set; 9.8.2.1 overview the radio transceiver also supports alternative dat a rates higher than 250 kb/s for applications beyond ieee 802.15.4 compliant network s. the selection of a data rate does not affect the re maining functionality. thus it is possible to run all features and operating modes of the radio transceiver in various combinations. the data rate can be selected by writing bits oqpsk _data_rate of register trx_ctrl_2. the high data rate modes occupy the same rf channel bandwidth as the ieee 802.15.4 ? 2.4 ghz 250 kb/s standard mode. the sensitivity of the receiver is reduced due to the decreased spreading factor. the following table shows typical values of the sensitivity for different data rates. table 9-23. high data rate sensitivity high data rate sensitivity comment 250 kb/s -100 dbm per 1%, psdu length of 20 octets 500 kb/s -96 dbm per 1%, psdu length of 20 octets 1000 kb/s -94 dbm per 1%, psdu length of 20 octets 2000 kb/s -86 dbm per 1%, psdu length of 20 octets by default there is no header based signaling of th e data rate within a transmitted frame. thus nodes using a data rate other than the default ieee 802.15.4 data rate of 250 kb/s are to be consistently configured in advan ce. the configurable start of frame delimiter (sfd) could be alternatively used as an i ndicator of the phy data rate (see "configurable start-of-frame delimiter (sfd)" on page 92). 9.8.2.2 high data rate packet structure higher data rate modulation is restricted to only t he payload octets in order to allow appropriate frame synchronization. the shr and the phr field are transmitted with the ieee 802.15.4 compliant data rate of 250 kb/s (refe r to "introduction ? ieee 802.15.4- 2006 frame format" on page 62 ). a comparison of the general packet structure for di fferent data rates with an example psdu length of 80 octets is shown in figure 9-30 on page 88. 88 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-30. high data rate frame structure 250 kb/s 0 time [s] 192 sfd phr 832 1472 2752 500 kb/s sfd phr 1000 kb/s sfd phr 2000 kb/s sfd phr 512 fcs fcs psdu: 80 octets psdu: 80 octets psdu: 80 octets psdu: 80 octets the effective data rate is smaller than the selecte d data rate due to the overhead caused by the shr, the phr and the fcs. the overhea d depends further on the length of the psdu. a graphical representation of t he effective data rate is shown in the following figure: figure 9-31. effective data rate ?b? for high data rate mode 0 200 400 600 800 1000 1200 1400 1600 0 20 40 60 80 100 120 psdu length in octets b [kbps] 2000 1000 500 250 2000 kbps 1000 kbps 500 kbps 250 kbps therefore high data rate transmission and reception is useful for large psdu lengths due to the higher effective data rate or to reduce the power consumption of the system. furthermore the active on-air time using high data rate modes is significantly reduced. 9.8.2.3 high data rate frame buffer access the frame buffer access to read or write frames for high data rate communication is similar to the procedure described in "frame buffer" on page 78 . however the last byte in the frame buffer after the psdu data is the ed v alue rather than the lqi value. 9.8.2.4 high data rate energy detection according to ieee 802.15.4 the ed measurement durat ion is 8 symbol periods. for frames operated at higher data rates the automated ed measurement duration is reduced to 32 s to take the reduced frame length i nto account ( "energy detection (ed)" on page 69 ). 89 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.8.2.5 high data rate mode options receiver sensitivity control the different data rates between ppdu header (shr a nd phr) and phy payload (psdu) cause a different sensitivity between header and payload. this can be adjusted by defining sensitivity threshold levels of the rec eiver. the receiver does not receive frames with an rssi level below the defined sensiti vity threshold level (register bits rx_pdt_level > 0). under these operating conditions the receiver current consumption is reduced by 500 a (refer to chapter "current consumption specifications" on page 518 ). a description of the settings to control the sensit ivity threshold with register rx_syn can be found in section "rx_syn ? transceiver receiver sensitivity control register" on page 120 . reduced acknowledgment timing on higher data rates the ieee 802.15.4 compliant ac knowledgment frame response time of 192 s significantly reduces the effective data rate of the network. to minimize this influence in extended operating mode rx_aack ( see section "rx_aack_on ? receive with automatic ack" on page 47 ), the acknowledgment frame response time can be reduced to 32 s. figure 9-32 below illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000 kb/s and a psdu length of 80 symbols. the psdu length of the acknowledgment fram e is 5 octets according to ieee 802.15.4. figure 9-32. high data rate aack timing 0 time [s] 192 512 aack_ack_time = 0 psdu: 80 octets sfd phr sfd phr 704 916 32 s psdu: 80 octets sfd phr sfd phr 192 s 544 aack_ack_time = 1 ack ack the acknowledgment time is reduced from 192 s to 3 2 s if bit aack_ack_time of register xah_ctrl_1 is set. 9.8.3 antenna diversity the main features of the antenna diversity implemen tation are: ? improves signal path robustness between nodes; ? self-contained antenna diversity algorithm of the radio transceiver; ? direct register based antenna selection; 9.8.3.1 overview the receive signal strength may vary and affect the link quality even for small changes of the antenna location due to multipath propagatio n effects between network nodes. these fading effects can result in an increased err or floor or loss of the connection between devices. antenna diversity can be applied to reduce the effe cts of multipath propagation and fading hence improving the reliability of a rf conn ection between network nodes. 90 8266c-mcu wireless-08/11 ATMEGA128RFA1 antenna diversity uses two antennas to switch to th e most reliable rf signal path. this is done by the radio transceiver during rx_listen a nd rx_aack_on state without interaction of the application software. both anten nas should be carefully separated from each other to ensure highly independent receiv e signals. antenna diversity can be used in basic and extended operating modes and can also be combined with other features and operating modes like high data rate mode and rx/tx indication. 9.8.3.2 antenna diversity application example a block diagram for an application using an antenna switch is shown in the following figure. figure 9-33. external antenna diversity ? block diagram 10 9 8 7 2 1 14 15 dig2 dig4 avss rfp rfn avss dig3 dig1 balun ant0 ant1 rf- switch b1 sw 1 ... ... generally, the antenna diversity algorithm is enabl ed with bit ant_div_en=1 in register ant_div. for the external antenna diversit y the control of the antenna switch (sw1) must be enabled by bit ant_ext_sw_en of regis ter ant_div. under this condition the control pins dig1 and dig2 are config ured as outputs. dig1 and dig2 are used to feed the antenna switch signal and its inverse to the differential inputs of the rf switch (sw1). the selected antenna is indicated by bit ant_sel of register ant_div. the antenna selection continues searching for new frames on bot h antennas after the frame reception is completed. however the register bit an t_sel maintains its previous value (from the last received frame) until a new shr has been found and the selection algorithm locked into one antenna again. then the r egister bit ant_sel is updated. the antenna defined by the ant_ctrl bits of registe r ant_div is selected for transmission. if for example the same antenna as se lected for reception is to be used for transmission, the antenna must be set using the ant_ctrl bits based on the value read from the ant_sel bit. it is recommended to rea d bit ant_sel after the trx24_rx_start interrupt. the autonomous search and selection allows the use of antenna diversity during reception even if the application software currentl y does not control the radio transceiver for instance in extended operating mode . 91 8266c-mcu wireless-08/11 ATMEGA128RFA1 an application software defined selection of a cert ain antenna can be done by disabling the automatic antenna diversity algorithm (ant_div_ en = 0) and selecting one antenna using register bit ant_ctrl. if the radio transceiver is not in a receive or tra nsmit state, it is recommended to disable register bit ant_ext_sw_en and to set the port pins dig1 and dig2 to output low (ddg1 = 1, portg1 = 0, ddf2 = 1, portf2 = 0) in ord er to reduce the power consumption or avoid leakage current of the externa l rf switch especially during sleep modes. 9.8.3.3 antenna diversity with extended operation m odes a combination of extended operation mode and antenn a diversity is allowed. while the radio transceiver is in rx_aack_on state, it switches to an antenna with a reliable signal. the receive antenna selection is a lso used for transmission of an automatic acknowledge frame. while the radio transceiver is in tx_aret state, th e selected antenna is automatically changed for every frame transmission retry. 9.8.3.4 antenna diversity sensitivity control the detection threshold of the receiver has to be a djusted due to a different receive algorithm used by the antenna diversity algorithm. it is recommended to set bits pdt_thres of register rx_ctrl to 3. 9.8.4 rx/tx indicator the main features are: ? rx/tx indicator to control an external rf front-en d; ? application software independent rf front-end cont rol; ? provide tx timing information; 9.8.4.1 overview while ieee 802.15.4 is a low-cost, low-power standa rd, solutions supporting higher transmit output power are occasionally desirable. a differential control pin pair can indicate that the radio transceiver is currently in transmit mode to simplify the control of an optional external rf front-end. the control of an external rf front-end is done via the digital control pins dig3/dig4. the function of this pin pair is enabled with bit p a_ext_en of register trx_ctrl_1. pin dig3 is set to low level and dig4 to high level while the transmitter is turned off. the two pins change the polarity when the radio tra nsceiver starts transmitting. this differential pin pair can be used to control pa, ln a and rf switches. if the radio transceiver is not in a receive or tra nsmit state, it is recommended to disable register bit pa_ext_en and to set the port pins dig 3 and dig4 to output low (ddg0 = 1, portg0 = 0, ddf3 = 1, portf3 = 0) in order to re duce the power consumption or avoid leakage current of external rf switches and o ther building blocks especially during sleep modes. 9.8.4.2 external rf-front end control the setup time of the external power amplifier (pa) relative to the internal building blocks should be adjusted when using an external rf front-end including a power amplifier to optimize the overall power spectral de nsity (psd) mask. 92 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-34. tx power ramping control for rf front-ends 0 6 8 10 trx_state slptr pll_o n 2 12 14 16 18 length [s] pa buffer 4 pa pa_buf_lt pa_lt dig 3 dig 4 m odulation 1 1 1 1 1 1 0 0 0 bu sy_tx the start-up sequence of the individual building bl ocks of the internal transmitter is shown in the previous figure. the transmission is a ctually initiated by writing ?1? to slptr. the radio transceiver state changes from pll _on to busy_tx and the pll settles to the transmit frequency within 16 s (par ameter ttr23 at page 43). the modulation starts 16 s (parameter ttr10 at page 43) after the slptr=1. t he pa buffer and the internal pa are enabled during this time. the control of an external pa is done via the diffe rential pin pair dig3 and dig4. dig3 = h / dig4 = l indicates that the transmission starts and can be used to enable an external pa. the timing of pins dig3/dig4 can be adjusted relative to the start of the frame and the activation of the internal pa buffer. this is controlled using the register bits pa_buf_lt and pa_lt. for details refer to figure 9-22 on page 78 . 9.8.5 rx frame time stamping to determine the exact timing of an incoming frame e.g. for beaconing networks, the symbol counter should be used. sfd time stamping is enabled by setting bit sctse of the symbol counter control register sccr0. the a ctual 32 bit symbol counter value is captured in the sfd time stamp register sc tsr at the time, the sfd has been received. for details see section "sfd and beacon timestamp generation" on page 137 . 9.8.6 configurable start-of-frame delimiter (sfd) the sfd is a field indicating the end of the shr an d the start of the packet data. the length of the sfd is 1 octet (2 symbols). this octe t is used for byte synchronization only and is not included in the frame buffer. the value of the sfd could be changed if it is need ed to operate non ieee 802.15.4 compliant networks. an ieee 802.15.4 compliant netw ork node does not synchronize to frames with a different sfd value. the register sfd_value contains the one octet start -of-frame delimiter (sfd) to synchronize to a received frame. it is not recommen ded to set the low-order 4 bits to 0 due to the way the shr is formed. 9.8.7 dynamic frame buffer protection the ATMEGA128RFA1 continues the reception of incomi ng frames as long as it is in any receive state. when a frame was successfully re ceived and stored into the frame buffer, the following frame will overwrite the fram e buffer content again. to relax the timing requirements for a frame buffer read access the dynamic frame buffer 93 8266c-mcu wireless-08/11 ATMEGA128RFA1 protection prevents that a new valid frame passes t o the frame buffer until the buffer protection bit is cleared (rx_safe_mode = 0). a received frame is automatically protected against overwriting: ? in basic operating mode, if its fcs is valid ? in extended operating mode, if an trx24_rx_end int errupt is generated the dynamic frame buffer protection is enabled, if register bit rx_safe_mode (register trx_ctrl_2, see "trx_ctrl_2 ? transceiver control register 2" on pa ge 113 ) is set and the radio transceiver state is rx_on o r rx_aack_on. note that dynamic frame buffer protection only prev ents write accesses from the air interface not from the application software. the ap plication software may still modify the frame buffer content. 9.8.8 security module (aes) the security module (aes) is characterized by: ? hardware accelerated encryption and decryption; ? compatible with aes-128 standard (128 bit key and data block size); ? ecb (encryption/decryption) mode and cbc (encrypti on) mode support; ? stand-alone operation, independent of other blocks ; ? uses 16mhz crystal clock of the transceiver; 9.8.8.1 overview the security module is based on an aes-128 core acc ording to the fips197 standard [5]. and provides two modes, the electronic code bo ok (ecb) and the cipher block chaining (cbc). the security module works independe nt of other building blocks of the radio transceiver. encryption and decryption can be performed in parallel to a frame transmission or reception. during radio transceiver sleep the registers of the security engine (aes) are cleared (see section "sleep ? sleep state" on page 37 ). the ecb and cbc modules including the aes core are clocked with the 16 mhz radio transceiver crystal oscillator. controlling the security block is possible over 5 r egisters within avr i/o space: table 9-24. security module address space overview register name description aes_status aes status register aes_ctrl aes control register aes_key access to 16 byte key buffer aes_state access to 16 byte data buffer 9.8.8.2 security module preparation the use of the security module requires a configura tion of the security engine before starting a security operation. the following steps are required: 94 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-25. aes engine configuration steps step description description 1 key setup write encryption or decryption key to k ey buffer (16 consecutive byte writes to aes_key) 2 aes configuration select aes mode: ecb or cbc select encryption or decryption enable the aes encryption ready interrupt aes_ready 3 write data write plaintext or cipher text to data buffer (16 consecutive byte writes to aes_state) 4 start operation start aes operation 5 wait for aes finished: 1. aes_ready irq or 2. polling aes_done bit (register aes_status) or 3. wait for 24 s wait until aes encryption/decryption is finished successfully 6 read data read cipher text or plaintext from data buffer (16 consecutive byte reads from aes_state) before starting any security operation a 16 byte ke y must be written to the security engine (refer to section "security key setup" on page 95). this can be done by 16 consecutive write accesses to the i/o register aes_ key. an internal address counter is incremented automatically with every read/ write op eration. an aes encryption/ decryption run resets the internal byte counter. if the key and data buffer has not been read or written completely (all 16 bytes), the foll owing encryption/ decryption operation will finish with an error. the following step selects either electronic code b ook (ecb) or cipher block chaining (cbc) as the aes_mode. these modes are explained in more detail in section "security operation modes" on page 95. encryption or decryption must be further selected with bit aes_dir of register aes_ctrl. if the aes error or aes ready irq is used, the inte rrupt must be enabled with bit aes_im. next the 128-bit plain text or cipher text data has to be provided to the aes hardware engine. the 16 data bytes must be consecutively wri tten to the aes_state register. the aes_state register can be accessed in the same way as the key register (refer to "security key setup" on page 95). the encryption or decryption is initiated with bit aes_request = 1. the operation takes 24 s and the completed encrypt ion/ decryption is indicated by the aes_ready irq and the aes_done bit. the internal by te counter of the key and data buffer is cleared and the resulting data can b e read out. for additional information about the key and data b uffer please refer to section "aes_key ? aes encryption and decryption key buffer register" on page 103 and "aes_state ? aes plain and cipher text buffer regis ter" on page 103. notes: 1. access to the security block is not possi ble while the radio transceiver is in state sleep. 2. all configurations of the security module, the s ram content and keys are reset during sleep or reset states. 95 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.8.8.3 security key setup the key is stored in a 16 byte sequential buffer. t o read or write the contents of the buffer, 16 consecutive read or write operations to the aes_key register are required. a 16-folded read access to registers aes_key return s the last round key of the preceding security operation. this is the key requi red for the corresponding ecb decryption operation after an ecb encryption operat ion. however the initial aes key written to the security module in advance of an aes run (see step 1 in table 9-25 on page 94) is not modified during an aes operation. t his initial key is used for the next aes run although it cannot be read from aes_key. before accessing the key buffer it must be ensured, that the internal address counter is initialized correctly. this is the cases after radi o transceiver reset (see trxpr ? transceiver pin register on page 171 ) or a completed aes encryption/ decryption operation. after an interrupted buffer read or writ e access, address pointer reinitialization is recommended by a simple read ac cess to the aes_ctrl register. note: 1. ecb decryption is not required for ieee 80 2.15.4 or zigbee security processing. the radio transceiver provides this functionality a s an additional feature. 9.8.8.4 security operation modes 9.8.8.4.1 electronic code book (ecb) ecb is the basic operating mode of the security mod ule and is configured by the aes_ctrl register. the bit aes_mode = 0 defines the ecb mode and bit aes_dir selects the direction to either encryption or decry ption. the data to be processed has to be written to registers aes_state. a security operation can be started by writing the start command aes_request = 1 (aes_ctrl register). the ecb encryption operation is illustrated in figure 9-35 below . figure 9-36 on page 96 shows the ecb decryption mode which is supported in a similar way. figure 9-35. ecb mode - encryption block cipher encryption encryption key plaintext ciphertext block cipher encryption plaintext ciphertext encryption key 96 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 9-36. ecb mode - decryption block cipher decryption decryption key plaintext ciphertext block cipher decryption decryption key plaintext ciphertext due to the nature of aes algorithm the initial key to be used when decrypting is not the same as the one used for encryption. instead it is the last round key. this last round key is the content of the key address space stored after running one full encryption cycle and must be saved for decryption. if the decr yption key has not been saved, it has to be recomputed by first running a dummy encryptio n (of an arbitrary plaintext) using the original encryption key. then the resulting rou nd key must be fetched from the key memory and written back into the key memory as the decryption key. ecb decryption is not used by either ieee 802.15.4 or zigbee frame security. both of these standards do not directly encrypt the payload . instead they protect the payload by applying a xor operation between the original paylo ad and the resulting (aes-) cipher text with a nonce (number used once). as the nonce is the same for encryption and decryption only ecb encryption is required. decrypt ion is performed by a xor operation between the received cipher text and its own encryption result concluding in the original plain text payload upon success. 9.8.8.4.2 cipher block chaining (cbc) in cbc mode the result of a previous aes operation is xor-combined with the new incoming vector forming the new plaintext to encryp t as shown in the next figure. this mode is used for the computation of a cryptographic checksum (message integrity code, mic). figure 9-37. cbc mode - encryption block cipher encryption encryption key ciphertext block cipher encryption plaintext ciphertext plaintext initialization vector (iv) encryption key ecb mode cbc mode after preparing the aes key and defining the aes op eration direction register bit aes_dir, the data has to be provided to the aes eng ine and the cbc operation can be started. the first cbc run has to be configured as ecb to pr ocess the initial data (plain text xor with an initialization vector provided by the a pplication software). all succeeding aes runs are to be configured as cbc by setting bit aes_mode = 1 (aes_ctrl register ). bit aes_dir (aes_ctrl register) must be set to aes_dir = 0 to enable aes encryption. the data to be processed has to be transferred to the aes_state 97 8266c-mcu wireless-08/11 ATMEGA128RFA1 register. setting bit aes_request = 1 (aes_ctrl reg ister) as described in section "security operation modes" on page 95 starts the first encryption. this causes t he next 128 bits of plain text data to be xored with the pr evious cipher text data, see figure 9- 37 on page 96. according to ieee 802.15.4 the input for the very f irst cbc operation has to be prepared by a xor operation of the plain text with the initialization vector (iv). the value of the initialization vector is 0. however an y other initialization vector can be applied for non-compliant usage. this operation has to be prepared by the application software. note that the mic algorithm of the ieee 802.15.4-20 06 standard requires cbc mode encryption only because it implements a one-way has h function. the status of the security processing is indicated by register aes_status. after a aes processing time of 24 s the register bit aes_d one changes to 1 (register aes_status) indicating that the security operation has finished (see "digital interface timing characteristics" on page 516 ). the end of the aes processing can also be indicated by the aes_ready interrupt. the bit aes_er of register aes_status is set if the operation has finished with an error. otherwise this bit is zero but aes_done is ? 1?. 9.8.8.5 aes interrupt handling the aes interrupt handling is slightly different fr om all other irq?s. if the aes_im bit (aes_ctrl register) and the global interrupt enable flag is set, the aes core can generate an aes ready interrupt (aes_ready). if the irq is issued, the aes_status register must be read to check the finis h status of the last operation. if aes_done is set, the last aes operation finished su ccessfully. if aes_er is set, an error occurred during the last operation. the aes_e r flag is cleared automatically during the read access to the aes_status register. the aes_done flag is cleared during the next read or write access to the aes_sta te (aes data) register. the two status flags must be cleared before a new i nterrupt can be issued. if aes_im is not set, the processing status can be polled by software (aes_status register), but no interrupt occurs. 9.9 continuous transmission test mode 9.9.1 overview the 2.4ghz transceiver offers a continuous transmis sion test mode to support final application / production tests as well as certifica tion tests. in this test mode the radio transceiver transmits continuously a previously tra nsferred frame (prbs mode) or a continuous wave signal (cw mode). in cw mode two different signal frequencies per cha nnel can be transmitted: ? f 1 = f ch + 0.5 mhz ? f 2 = f ch - 0.5 mhz here f ch is the channel center frequency programmed by regi ster phy_cc_cca. note that in cw mode it is not possible to transmit a rf signal directly on the channel center frequency. psdu data in the frame buffer mus t contain at least a valid phr (see section "introduction ? ieee 802.15.4-2006 frame format" on page 62 ). it is recommended to use a frame of maximum length (127 b ytes) and arbitrary psdu data 98 8266c-mcu wireless-08/11 ATMEGA128RFA1 for the prbs mode. the shr and the phr are not tran smitted. the transmission starts with the psdu data and is repeated continuously. 9.9.2 configuration all register configurations shall be setup as follo ws before enabling continuous transmission test mode: ? tx channel setting (optional); ? tx output power setting (optional); ? mode selection (prbs / cw); an access to the registers tst_ctrl_digi and part_n um enables the continuous transmission test mode. the transmission is started by enabling the pll (tr x_cmd = pll_on) and writing the tx_start command to register trx_state. even for cw signal transmission it is required to w rite valid psdu data to the frame buffer. for prbs mode it is recommended to write a frame of maximum length. the detailed programming sequence is shown in table 9-26 below . the column r/w informs about writing (w) or reading (r) a register or the frame buffer. table 9-26. continuous transmission programming sequence step action register r/ w value description 1 reset reset the transceiver 2 register access irq_mask w 0x01 set irq mask regi ster, enable pll_lock interrupt and set global avr irq enable 3 register access trx_ctrl_1 w 0x00 disable tx_auto _crc_on 4 register access trx_state w 0x03 set radio transceiver state trx_off 5 register access phy_cc_cca w 0x33 set ieee 802.15 .4 channel, e.g. 19 6 register access phy_tx_pwr w 0x00 set tx output p ower, e.g. to p max 7 register access trx_status r 0x08 verify trx_off state 8 register access tst_ctrl_digi w 0x0f enable conti nuous transmission test mode ? step # 1 9 (1) register access trx_ctrl_2 w 0x03 enable high data rate mode, 2 mb/s 10 (1) register access rx_ctrl w 0xa7 configure high data rate mode 11 (2) frame buffer write access w write psdu data (even for cw mode), refer to table 9-27 on page 99 12 register access part_num w 0x54 enable continuou s transmission test mode ? step # 2 13 register access part_num w 0x46 enable continuou s transmission test mode ? step # 3 14 register access trx_state w 0x09 enable pll_on s tate 15 interrupt event r 0x01 wait for pll_lock interr upt 99 8266c-mcu wireless-08/11 ATMEGA128RFA1 step action register r/ w value description 16 register access trx_state w 0x02 initiate transm ission, enter busy_tx state 17 measurement perform measurement 18 register access trx_ctrl_2 w 0x00 disable contin uous transmission test mode 19 reset reset the transceiver notes: 1. only required for cw mode, do not configu re for prbs mode. 2. frame buffer content varies for different modula tion schemes. the content of the frame buffer has to be defined f or continuous transmission prbs mode or cw mode. to measure the power spectral dens ity (psd) mask of the transmitter it is recommended to use a random seque nce of maximum length for the psdu data. to measure cw signals it is necessary to write eith er 0x00 or 0xff to the frame buffer. for details refer to table 9-27 below . table 9-27. frame buffer content for various continuous transm ission modulation schemes step action frame content comment random sequence modulated rf signal 0x00 (each byte) f ch ? 0.5 mhz, cw signal 11 frame buffer write access 0xff (each byte) f ch + 0.5 mhz, cw signal 9.10 abbreviations aack - automatic acknowledgement ack - acknowledgement adc - analog-to-digital converter ad - antenna diversity agc - automated gain control aes - advanced encryption standard aret - automatic retransmission avreg - voltage regulator for analog building bloc ks awgn - additive white gaussian noise batmon - battery monitor bbp - base band processor bpf - band pass filter cbc - cipher block chaining crc - cyclic redundancy check cca - clear channel assessment csma-ca - carrier sense multiple access/collision a voidance 100 8266c-mcu wireless-08/11 ATMEGA128RFA1 cw - continuous wave dvreg - voltage regulator for digital building blo cks ecb - electronic code book ed - energy detection esd - electro static discharge evm - error vector magnitude fcf - frame control field fcs - frame check sequence fifo - first in first out ftn - filter tuning network gpio - general purpose input output ism - industrial, scientific, and medical ldo - low-drop output lna - low-noise amplifier lo - local oscillator lqi - link quality indicator lsb - least significant bit mac - medium access control mfr - mac footer mhr - mac header msb - most significant bit msdu - mac service data unit mpdu - mac protocol data unit msk - minimum shift keying o-qpsk - offset - quadrature phase shift keying pa - power amplifier pan - personal area network pcb - printed circuit board per - packet error rate phr - phy header phy - physical layer pll - phase locked loop por - power-on reset ppf - poly-phase filter prbs - pseudo random bit sequence psdu - phy service data unit 101 8266c-mcu wireless-08/11 ATMEGA128RFA1 psd - power spectral mask qfn - quad flat no-lead package rf - radio frequency rssi - received signal strength indicator rx - receiver sfd - start-of-frame delimiter shr - synchronization header spi - serial peripheral interface sram - static random access memory ssbf - single side band filter tx - transmitter vco - voltage controlled oscillator vreg - voltage regulator xosc - crystal oscillator 9.11 reference documents [1] ieee std 802.15.4? -2006: wireless medium access control (mac) and physical layer (phy) specifications for low-rate wi reless personal area networks (lr-wpans) [2] ieee std 802.15.4? -2003: wireless medium access control (mac) and physical layer (phy) specifications for low-rate wi reless personal area networks (lr-wpans) [3] ansi / esd-stm5.1-2001: esd association standar d test method for electrostatic discharge sensitivity testing ? human body model (hbm). [4] esd-stm5.3.1-1999: esd association standard tes t method for electrostatic discharge sensitivity testing ? charged device mode l (cdm). [5] nist fips pub 197: advanced encryption standard (aes), federal information processing standards publication 197, u s department of commerce/nist, november 26, 2001 [6] at86rf231 software programming model 9.12 register description 9.12.1 aes_ctrl ? aes control register bit 7 6 5 4 3 2 1 0 na ($13c) aes_request res aes_mode res aes_dir aes_im res1 res0 aes_ctrl read/write rw r rw r rw rw r r initial value 0 0 0 0 0 0 0 0 102 8266c-mcu wireless-08/11 ATMEGA128RFA1 this register controls the operation of the securit y module. do not access this register during aes operation to read the aes core status. a read or write access to the register stops the ongoing processing. to read the aes statu s use bit aes_done of register aes_status. note that the aes_ctrl register is clea red when entering the radio transceiver sleep state. ? bit 7 ? aes_request - request aes operation. a write access with aes_request = 1 initiates the a es operation. ? bit 6 ? res - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 5 ? aes_mode - set aes operation mode this register bit sets the aes operation mode (ecb/ cbc mode). table 9-28 aes_mode register bits register bits value description 0 aes mode is ecb (electronic code book). aes_mode 1 aes mode is cbc (cipher block chaining). ? bit 4 ? res - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 3 ? aes_dir - set aes operation direction this register bit sets the aes operation direction to either encryption or decryption. table 9-29 aes_dir register bits register bits value description 0 aes operation is encryption. aes_dir 1 aes operation is decryption. ? bit 2 ? aes_im - aes interrupt enable this register bit is used to enable the aes interru pt. ? bit 1:0 ? res1:0 - reserved bit these bits are reserved for future use. the result of a read access is undefined. the register bits must always be written with the reset value. 9.12.2 aes_status ? aes status register bit 7 6 5 4 3 2 1 0 na ($13d) aes_er res5 res4 res3 res2 res1 res0 aes_done aes_status read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this read-only register signals the status of the s ecurity module and operation. note that the aes_status register is cleared when enteri ng the radio transceiver sleep state. ? bit 7 ? aes_er - aes operation finished with error 103 8266c-mcu wireless-08/11 ATMEGA128RFA1 this register bit indicates an error during aes mod ule run. an error occurs if accessing aes_ctrl while an aes operation is running or if ae s_key or aes_state memory is not loaded completely or less than 16 byte read from aes_state. ? bit 6:1 ? res5:0 - reserved these bits are reserved for future use. ? bit 0 ? aes_done - aes operation finished with succ ess this register bit indicates a successfully finished operation of the aes module. 9.12.3 aes_state ? aes plain and cipher text buffer register bit 7 6 5 4 3 2 1 0 na ($13e) aes_state7:0 aes_state read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the aes_state register accesses a 16 byte internal data buffer. the buffer is accessed by reading or writing 16 times to the same address location (aes_state). if the buffer is not completely read or written an err or occurs when an aes operation is started. note that the aes_state register is cleare d when entering the radio transceiver sleep state. ? bit 7:0 ? aes_state7:0 - aes plain and cipher text buffer these bits represent the data buffer for the aes op eration. 9.12.4 aes_key ? aes encryption and decryption key buffer register bit 7 6 5 4 3 2 1 0 na ($13f) aes_key7:0 aes_key read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the aes key register accesses a 128 bit internal bu ffer that holds the encryption or decryption key. the aes_key buffer is a 16 byte buf fer. the buffer is accessed by reading or writing 16 fold to the same address loca tion (aes_key). a read access to registers aes_key returns the last round key of the preceding security operation. this is the key that is required for the corresponding e cb decryption operation after an ecb encryption operation. however, the initial aes key written to the security module in advance of an aes run is not modified during an aes operation. this initial key is used for the next aes run even if it cannot be read from aes_key register. note that the aes_key register is cleared when entering the radio transceiver sleep state. ? bit 7:0 ? aes_key7:0 - aes encryption/decryption ke y buffer these bits represent the data buffer for the aes en cryption/decryption key. 104 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.5 trx_status ? transceiver status register bit 7 6 5 4 na ($141) cca_done cca_status tst_status trx_status4 trx_stat us read/write r r r r initial value 0 0 0 0 bit 3 2 1 0 na ($141) trx_status3 trx_status2 trx_status1 trx_status0 trx _status read/write r r r r initial value 0 0 0 0 this read-only register signals the present state o f the radio transceiver as well as the status of the cca operation. a state change is init iated by writing a state transition command to the trx_cmd bits of register trx_state. the register is not accessible in sleep state. ? bit 7 ? cca_done - cca algorithm status this bit indicates if a cca request is completed. t his is also indicated by a trx24_cca_ed_done interrupt. note that register bit cca_done is cleared in response to a cca_request. table 9-30 cca_done register bits register bits value description 0 cca calculation not finished cca_done 1 cca calculation finished ? bit 6 ? cca_status - cca status result the result of the cca measurement is available in r egister bit cca_status after a cca request is completed. note that register bit cc a_status is cleared in response to a cca_request. table 9-31 cca_status register bits register bits value description 0 channel indicated as busy. cca_status 1 channel indicated as idle. ? bit 5 ? tst_status - test mode status this bit is reserved for internal use. it indicates the status of the test mode. table 9-32 tst_status register bits register bits value description 0 test mode is disabled. tst_status 1 test mode is active. ? bit 4:0 ? trx_status4:0 - transceiver main status the register bits trx_status signal the current rad io transceiver status. do not try to initiate a further state change while the radio tra nsceiver is in state_transition_in_progress state. values not list ed in the following table are reserved. table 9-33 trx_status register bits register bits value description trx_status4:0 105 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x01 busy_rx 0x02 busy_tx 0x06 rx_on 0x08 trx_off 0x09 pll_on 0x0f sleep 0x11 busy_rx_aack 0x12 busy_tx_aret 0x16 rx_aack_on 0x19 tx_aret_on 0x1f state_transition_in_progress 9.12.6 trx_state ? transceiver state control regist er bit 7 6 5 4 na ($142) trac_status2 trac_status1 trac_status0 trx_cmd4 trx_state read/write r r r rw initial value 0 0 0 0 bit 3 2 1 0 na ($142) trx_cmd3 trx_cmd2 trx_cmd1 trx_cmd0 trx_state read/write rw rw rw rw initial value 0 0 0 0 the states of the radio transceiver are controlled via register trx_state using register bits trx_cmd. the read-only register bits trac_status indicate the status or result of an extended operating mode transaction . a successful state transition shall be confirmed by reading register bits trx_status. t his register is used for both basic and extended operating mode. ? bit 7:5 ? trac_status2:0 - transaction status the status of the rx_aack and tx_aret procedure is indicated by register bits trac_status. trac_status is only valid in extended operating modes (note, trac_status is valid 2us after the respective proce dure is finished by tx_end or rx_end irq). details of the algorithm and a descrip tion of the status information are given in the rx_aack_on and tx_aret_on sections of the data-sheet. even though the reset value for register bits trac_status is 0, the rx_aack and tx_aret procedures set the register bits to trac_status = 7 (invalid) when it is started. not all status values are used in both rx_aack and tx_a ret transactions. in tx_aret the status success_data_pending indicates a success ful reception of an ack frame with frame pending bit set to 1. in rx_aack t he status success_wait_for_ack indicates an ack frame is abou t to sent in rx_aack slotted acknowledgment. slotted acknowledgment oper ation must be enabled with the slotted_operation bit of register xah_ctrl_0. the a pplication software must set the slptr bit of register trxpwr at the next ba ck-off slot boundary in order to 106 8266c-mcu wireless-08/11 ATMEGA128RFA1 initiate a transmission of the ack frame. for detai ls refer to ieee 802.15.4-2006, chapter 5.5.4.1. values not listed in the following table are reserved. table 9-34 trac_status register bits register bits value description 0 success (rx_aack, tx_aret) 1 success_data_pending (tx_aret) 2 success_wait_for_ack (rx_aack) 3 channel_access_failure (tx_aret) 5 no_ack (tx_aret) trac_status2:0 7 invalid (rx_aack, tx_aret) ? bit 4:0 ? trx_cmd4:0 - state control command a write access to register bits trx_cmd initiates a state transition of the radio transceiver towards the new state as defined by the write access. do not try to initiate a further state change while the radio transceiver is in state_transition_in_progress state (see trx_status register). force_pll_on is not valid for the sleep state as we ll as during state_transition_in_progress towards the sleep stat e. values not listed in the following table are reserved and mapped to nop. table 9-35 trx_cmd register bits register bits value description 0x00 nop 0x02 tx_start 0x03 force_trx_off 0x04 force_pll_on 0x06 rx_on 0x08 trx_off 0x09 pll_on (tx_on) 0x16 rx_aack_on trx_cmd4:0 0x19 tx_aret_on 9.12.7 trx_ctrl_0 ? reserved bit 7 6 5 4 3 2 1 0 na ($143) res7 res6 res5 res4 res3 res2 res1 res0 trx_ctrl_0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 1 1 0 0 1 this register is reserved for future use. ? bit 7:0 ? res7:0 - reserved these bits are reserved for future use. 107 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.8 trx_ctrl_1 ? transceiver control register 1 bit 7 6 5 4 na ($144) pa_ext_en irq_2_ext_en tx_auto_crc_on res4 trx_ctrl_1 read/write rw rw rw r initial value 0 0 1 0 bit 3 2 1 0 na ($144) res3 res2 res1 res0 trx_ctrl_1 read/write r r r r initial value 0 0 0 0 the trx_ctrl_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. ? bit 7 ? pa_ext_en - external pa support enable this register bit enables pin dig3 and pin dig4 to indicate the transmit state of the radio transceiver. the control of the external rf f ront-end is disabled when this bit is 0. both pins dig3 and dig4 are then low. the control o f the external front-end is enabled when this bit is 1. dig3 and dig4 then indicate the state of the radio transceiver. pin dig3 is high and pin dig4 is low in the state tx_bu sy. in all other states pin dig3 is low and pin dig4 is high. it is recommended to set pa_ext_en=1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external rf switches or other building blocks especially dur ing sleep state. ? bit 6 ? irq_2_ext_en - connect frame start irq to t c1 when this bit is set to one the capture input of ti mer/counter 1 is connected to the rx frame start signal and pin dig2 becomes an output, driving the rx frame start signal. antenna diversity rf switch control (ant_ext_sw_en= 1) shall not be used at the same time, because it shares the same device pin. t he function irq_2_ext_en is available for alternate frame time stamping using t imer/counter 1. in general the preferred method for frame time stamping is using t he symbol counter. ? bit 5 ? tx_auto_crc_on - enable automatic crc calcu lation this register bit controls the automatic fcs genera tion for tx operations. the automatic fcs algorithm is performed autonomously b y the radio transceiver if register bit tx_auto_crc_on=1. ? bit 4:0 ? res4:0 - reserved 9.12.9 phy_tx_pwr ? transceiver transmit power cont rol register bit 7 6 5 4 na ($145) pa_buf_lt1 pa_buf_lt0 pa_lt1 pa_lt0 phy_tx_pwr read/write rw rw rw rw initial value 1 1 0 0 bit 3 2 1 0 na ($145) tx_pwr3 tx_pwr2 tx_pwr1 tx_pwr0 phy_tx_pwr read/write rw rw rw rw initial value 0 0 0 0 this register controls the output power of the tran smitter. 108 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:6 ? pa_buf_lt1:0 - power amplifier buffer lea d time these register bits control the enable lead time of the internal pa buffer relative to the enable time of the internal pa. this time is furthe r used to derive a control signal for an external rf front-end to switch between receive and transmit. table 9-36 pa_buf_lt register bits register bits value description 0 0 s 1 2 s 2 4 s pa_buf_lt1:0 3 6 s ? bit 5:4 ? pa_lt1:0 - power amplifier lead time these register bits control the enable lead time of the internal power amplifier relative to the beginning of the transmitted frame (shr). table 9-37 pa_lt register bits register bits value description 0 2 s 1 4 s 2 6 s pa_lt1:0 3 8 s ? bit 3:0 ? tx_pwr3:0 - transmit power setting these register bits determine the tx output power o f the radio transceiver. table 9-38 tx_pwr register bits register bits value description 0 3.5 dbm 1 3.3 dbm 2 2.8 dbm 3 2.3 dbm 4 1.8 dbm 5 1.2 dbm 6 0.5 dbm 7 -0.5 dbm 8 -1.5 dbm 9 -2.5 dbm 10 -3.5 dbm 11 -4.5 dbm 12 -6.5 dbm 13 -8.5 dbm 14 -11.5 dbm tx_pwr3:0 15 -16.5 dbm 109 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.10 phy_rssi ? receiver signal strength indicat or register bit 7 6 5 4 na ($146) rx_crc_valid rnd_value1 rnd_value0 rssi4 phy_rssi read/write r r r r initial value 0 0 0 0 bit 3 2 1 0 na ($146) rssi3 rssi2 rssi1 rssi0 phy_rssi read/write r r r r initial value 0 0 0 0 the phy_rssi register is a multi purpose register t hat indicates fcs validity, provides random numbers and shows the current rssi value. ? bit 7 ? rx_crc_valid - received frame crc status reading this register bit indicates whether the las t received frame has a valid fcs or not. the register bit is updated when issuing a trx 24_rx_end interrupt and remains valid until the next trx24_rx_end interrupt is issu ed, caused by a new frame reception. table 9-39 rx_crc_valid register bits register bits value description 0 crc (fcs) not valid rx_crc_valid 1 crc (fcs) valid ? bit 6:5 ? rnd_value1:0 - random value a 2-bit random value can be retrieved by reading register bits rnd_value. the value can be u sed for random numbers for security applications. note that the radio transcei ver shall be in basic operating mode receive state. the values are updated every 1 s. ? bit 4:0 ? rssi4:0 - receiver signal strength indica tor the result of the automated rssi measurement is sto red in these register bits. the value is updated every 2s in receive states. the r ead value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dbm) with a resolution of 3 db. a rssi value of 0 indicates a rf input power lower than rssi_base_val (-90 dbm). a value o f 28 marks a power higher or equal to -10 dbm. table 9-40 rssi register bits register bits value description 0 minimum rssi value: p(rf) < -90 dbm 1 p(rf) = rssi_base_val+3 (rssi-1) [dbm] 2 ... rssi4:0 28 maximum rssi value: p(rf) -10 dbm 110 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.11 phy_ed_level ? transceiver energy detection level register bit 7 6 5 4 na ($147) ed_level7 ed_level6 ed_level5 ed_level4 phy_ed_leve l read/write r r r r initial value 1 1 1 1 bit 3 2 1 0 na ($147) ed_level3 ed_level2 ed_level1 ed_level0 phy_ed_leve l read/write r r r r initial value 1 1 1 1 this register contains the result of an energy dete ction measurement. ? bit 7:0 ? ed_level7:0 - energy detection level the minimum ed value (ed_level = 0) indicates a rec eiver power less than or equal to rssi_base_val. the range is 83 db with a resolut ion of 1 db and an absolute accuracy of 5 db. a manual ed measurement can be i nitiated by a write access to this register. a value of 0xff signals that no measureme nt has yet been started (reset value). the measurement duration is 8 symbol period s (128 s) for a data rate of 250 kb/s. for high data rate modes the automated measur ement duration is reduced to 32 s. for manually initiated ed measurements in these modes the measurement period is still 128 s as long as the receiver is in rx_on st ate. a value other than 0xff indicates the result of the last ed measurement. table 9-41 ed_level register bits register bits value description 0x00 minimum result of last ed measurement 0x01 p(rf) = rssi_base_val+ed [dbm] 0x02 ... 0x53 maximum result of last ed measurement ed_level7:0 0xff reset value 9.12.12 phy_cc_cca ? transceiver clear channel asse ssment (cca) control register bit 7 6 5 4 na ($148) cca_request cca_mode1 cca_mode0 channel4 phy_cc_cca read/write rw rw rw rw initial value 0 0 1 0 bit 3 2 1 0 na ($148) channel3 channel2 channel1 channel0 phy_cc_cca read/write rw rw rw rw initial value 1 0 1 1 this register is provided to initiate and control a cca measurement. ? bit 7 ? cca_request - manual cca measurement reques t a manual cca measurement is initiated with setting cca_request=1. the end of the cca measurement is indicated by the trx24_cca_e d_done interrupt. register bits cca_done and cca_status of register trx_status are updated after a 111 8266c-mcu wireless-08/11 ATMEGA128RFA1 cca_request. the register bit is automatically clea red after requesting a cca measurement with cca_request=1. ? bit 6:5 ? cca_mode1:0 - select cca measurement mode the cca mode can be selected using these register b its. note that ieee 802.15.4- 2006 cca mode 3 defines the logical combination of cca mode 1 and 2 with the logical operators and or or. this can be selected w ith cca_mode=0 for logical operation or and cca_mode=3 for logical operation a nd. table 9-42 cca_mode register bits register bits value description 0 mode 3a, carrier sense or energy above threshold 1 mode 1, energy above threshold 2 mode 2, carrier sense only cca_mode1:0 3 mode 3b, carrier sense and energy above threshold ? bit 4:0 ? channel4:0 - rx/tx channel selection these register bits define the rx/tx channel. the c hannel assignment is according to ieee 802.15.4. table 9-43 channel register bits register bits value description 11 2405 mhz 12 2410 mhz 13 2415 mhz 14 2420 mhz 15 2425 mhz 16 2430 mhz 17 2435 mhz 18 2440 mhz 19 2445 mhz 20 2450 mhz 21 2455 mhz 22 2460 mhz 23 2465 mhz 24 2470 mhz 25 2475 mhz channel4:0 26 2480 mhz 9.12.13 cca_thres ? transceiver cca threshold setti ng register bit 7 6 na ($149) cca_cs_thres3 cca_cs_thres2 cca_thres read/write rw rw initial value 1 1 112 8266c-mcu wireless-08/11 ATMEGA128RFA1 bit 5 4 na ($149) cca_cs_thres1 cca_cs_thres0 cca_thres read/write rw rw initial value 0 0 bit 3 2 na ($149) cca_ed_thres3 cca_ed_thres2 cca_thres read/write rw rw initial value 0 1 bit 1 0 na ($149) cca_ed_thres1 cca_ed_thres0 cca_thres read/write rw rw initial value 1 1 this register sets the threshold level for the ener gy detection (ed) of the clear channel assessment (cca). ? bit 7:4 ? cca_cs_thres3:0 - cs threshold level for cca measurement these bits are reserved for internal use. ? bit 3:0 ? cca_ed_thres3:0 - ed threshold level for cca measurement these bits define the received power threshold of t he energy above threshold algorithm. the threshold is calculated by rssi_base _val + 2cca_ed_thres [dbm]. any received power above this level is inter preted as a busy channel. 9.12.14 rx_ctrl ? transceiver receive control regis ter bit 7 6 5 4 na ($14a) resx7 resx6 resx5 resx4 rx_ctrl read/write rw rw rw rw initial value 1 0 1 1 bit 3 2 1 0 na ($14a) pdt_thres3 pdt_thres2 pdt_thres1 pdt_thres0 rx_ctrl read/write rw rw rw rw initial value 0 1 1 1 the register controls the sensitivity of the antenn a diversity mode. note that in high data rate modes the acr module will always be disab led. ? bit 7:4 ? resx7:4 - reserved ? bit 3:0 ? pdt_thres3:0 - receiver sensitivity contr ol these register bits control the sensitivity of the receiver correlation unit. if the antenna diversity algorithm is enabled the value shall be s et to pdt_thres = 3. otherwise it shall be set back to the reset value. values not li sted in the following table are reserved. table 9-44 pdt_thres register bits register bits value description 0x7 reset value, to be used if antenna diversity algorithm is disabled pdt_thres3:0 0x3 recommended correlator threshold for 113 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description antenna diversity operation 9.12.15 sfd_value ? start of frame delimiter value register bit 7 6 5 4 3 2 1 0 na ($14b) sfd_value7:0 sfd_value read/write rw rw rw rw rw rw rw rw initial value 1 0 1 0 0 1 1 1 this register contains the one octet start-of-frame delimiter (sfd) to synchronize to a received frame. the lower 4 bits must not be all ze ro to avoid decoding conflicts. ? bit 7:0 ? sfd_value7:0 - start of frame delimiter v alue for compliant ieee 802.15.4 networks set sfd_value = 0xa7. this is the default value of the register. to establish non ieee 802.15 .4 compliant networks the sfd value can be changed to any other value. if enabled a rx_ start interrupt is issued only if the received sfd matches the register content of sf d_value and a valid phr is received. table 9-45 sfd_value register bits register bits value description sfd_value7:0 0xa7 ieee 802.15.4 compliant value of the sfd 9.12.16 trx_ctrl_2 ? transceiver control register 2 bit 7 6 5 4 na ($14c) rx_safe_mode res4 res3 res2 trx_ctrl_2 read/write rw r r r initial value 0 0 0 0 bit 3 2 1 0 na ($14c) res1 res0 oqpsk_data_rate1 oqpsk_data_rate0 trx_ctrl_2 read/write r r rw rw initial value 0 0 0 0 this register controls the data rate setting of the radio transceiver. ? bit 7 ? rx_safe_mode - rx safe mode if this bit is set, the next received frame will be protected and not overwritten by following frames. set this bit to 0 to release the buffer (and set it again for further protection). ? bit 6:2 ? res4:0 - reserved ? bit 1:0 ? oqpsk_data_rate1:0 - data rate selection a write access to these register bits sets the oqps k psdu data rate used by the radio transceiver. the reset value oqpsk_data_rate = 0 is the psdu data rate according to ieee 802.15.4. all other values are used in high data rate modes. 114 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-46 oqpsk_data_rate register bits register bits value description 0 250 kb/s (ieee 802.15.4 compliant) 1 500 kb/s 2 1000 kb/s oqpsk_data_rate1:0 3 2000 kb/s 9.12.17 ant_div ? antenna diversity control registe r bit 7 6 5 4 na ($14d) ant_sel res2 res1 res0 ant_div read/write r r r r initial value 0 0 0 0 bit 3 2 1 0 na ($14d) ant_div_en ant_ext_sw_en ant_ctrl1 ant_ctrl0 ant_div read/write rw rw rw rw initial value 0 0 1 1 this register controls the antenna diversity. ? bit 7 ? ant_sel - antenna diversity antenna status this register bit signals the currently selected an tenna path. the selection may be based either on the last antenna diversity cycle (a nt_div_en = 1) or on the content of register bits ant_ctrl. table 9-47 ant_sel register bits register bits value description 0 antenna 0 ant_sel 1 antenna 1 ? bit 6:4 ? res2:0 - reserved ? bit 3 ? ant_div_en - enable antenna diversity if this register bit is set the antenna diversity a lgorithm is enabled. on reception of a frame the algorithm selects an antenna autonomously during shr search. this selection is kept until 1. a new shr search starts or 2. receive states are left or 3. a manually programming of bits ant_ctrl occurred . if ant_div_en = 1 the bit ant_ext_sw_en shall also be set to 1. table 9-48 ant_div_en register bits register bits value description 0 antenna diversity algorithm disabled ant_div_en 1 antenna diversity algorithm enabled ? bit 2 ? ant_ext_sw_en - enable external antenna swi tch control if enabled, pin dig1 and pin dig2 become output pin s and provide a differential control signal for an external antenna diversity switch. th e selection of a specific antenna is done either by the automatic antenna diversity algo rithm (ant_div_en = 1) or 115 8266c-mcu wireless-08/11 ATMEGA128RFA1 according to bits ant_ctrl if the antenna diversity algorithm is disabled. do not enable antenna diversity rf switch control (ant_ext _sw_en = 1) and rx frame time stamping (irq_2_ext_en = 1, see register trx_c trl_1) at the same time. if this bit is set the control pins dig1/dig2 are acti vated in all radio transceiver states as long as bit ant_ext_sw_en is also set. if the radio transceiver is not in a receive or transmit state, it is recommended to disable bit an t_ext_sw_en to reduce the power consumption or avoid leakage current of an external rf switch especially during sleep state. the output pins dig1 and dig2 are pull ed-down to digital ground if bit ant_ext_sw_en = 0. table 9-49 ant_ext_sw_en register bits register bits value description 0 antenna diversity rf switch control disabled ant_ext_sw_en 1 antenna diversity rf switch control enabled ? bit 1:0 ? ant_ctrl1:0 - static antenna diversity sw itch control these bits provide a static control of an antenna d iversity switch. this register setting defines the selected antenna if ant_div_en is set t o 0 (antenna diversity disabled). register values 1 and 2 are valid for ant_ext_sw_en = 1. table 9-50 ant_ctrl register bits register bits value description 0 reserved 1 antenna 1: dig1=l, dig2=h 2 antenna 0: dig1=h, dig2=l ant_ctrl1:0 3 default value for ant_ext_sw_en=0; mandatory setting for applications not using antenna diversity 9.12.18 irq_mask ? transceiver interrupt enable reg ister bit 7 6 5 4 na ($14e) awake_en tx_end_en ami_en cca_ed_done_en irq_mask read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($14e) rx_end_en rx_start_en pll_unlock_en pll_lock_en irq_mask read/write rw rw rw rw initial value 0 0 0 0 this register is used to enable or disable individu al interrupts of the radio transceiver. an interrupt is enabled if the corresponding bit is set to 1. all interrupts are disabled after the power up sequence or reset. if an interru pt is enabled it is recommended to read the interrupt status register irq_status first to clear the history. ? bit 7 ? awake_en - awake interrupt enable ? bit 6 ? tx_end_en - tx_end interrupt enable ? bit 5 ? ami_en - address match interrupt enable ? bit 4 ? cca_ed_done_en - end of ed measurement inte rrupt enable ? bit 3 ? rx_end_en - rx_end interrupt enable 116 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 2 ? rx_start_en - rx_start interrupt enable ? bit 1 ? pll_unlock_en - pll unlock interrupt enable ? bit 0 ? pll_lock_en - pll lock interrupt enable 9.12.19 irq_status ? transceiver interrupt status r egister bit 7 6 5 4 na ($14f) awake tx_end ami cca_ed_done irq_status read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($14f) rx_end rx_start pll_unlock pll_lock irq_status read/write rw rw rw rw initial value 0 0 0 0 this register contains the status of the pending in terrupt requests. an interrupt is pending if the associated bit has a value of one. s uch a pending interrupts can be manually cleared by writing a 1 to that register bi t. interrupts are automatically cleared when the corresponding interrupt service routine is being executed. ? bit 7 ? awake - awake interrupt status ? bit 6 ? tx_end - tx_end interrupt status ? bit 5 ? ami - address match interrupt status ? bit 4 ? cca_ed_done - end of ed measurement interru pt status ? bit 3 ? rx_end - rx_end interrupt status ? bit 2 ? rx_start - rx_start interrupt status ? bit 1 ? pll_unlock - pll unlock interrupt status ? bit 0 ? pll_lock - pll lock interrupt status 9.12.20 vreg_ctrl ? voltage regulator control and s tatus register bit 7 6 5 4 na ($150) avreg_ext avdd_ok resx5 resx4 vreg_ctrl read/write rw r rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($150) dvreg_ext dvdd_ok resx1 resx0 vreg_ctrl read/write rw r rw rw initial value 0 0 0 0 this register controls the use of the voltage regul ators and indicates their status. ? bit 7 ? avreg_ext - use external avdd regulator if set, this register bit disables the internal ana log voltage regulator to apply an external regulated 1.8v supply for the analog building block s. 117 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-51 avreg_ext register bits register bits value description 0 internal avdd voltage regulator for the analog section is enabled. avreg_ext 1 internal avdd voltage regulator is disabled; use external regulated 1.8v supply voltage for the analog section. ? bit 6 ? avdd_ok - avdd supply voltage valid this register bit indicates if the internal 1.8v re gulated voltage supply avdd has settled. the bit is set to logic high if avreg_ext = 1. table 9-52 avdd_ok register bits register bits value description 0 analog voltage regulator disabled or supply voltage not stable avdd_ok 1 analog supply voltage has settled ? bit 5:4 ? resx5:4 - reserved ? bit 3 ? dvreg_ext - use external dvdd regulator this bit may be set in the register, but is deactiv ated in the design. the dvreg_ext functionality to deactivate the digital voltage reg ulator is no implemented anymore table 9-53 dvreg_ext register bits register bits value description 0 internal dvdd voltage regulator for the digital section is enabled. dvreg_ext 1 internal dvdd voltage regulator is disabled; use external regulated 1.8v supply voltage for the digital section. ? bit 2 ? dvdd_ok - dvdd supply voltage valid this register bit indicates if the internal 1.8v re gulated voltage supply dvdd has settled. the bit is set to logic high if dvreg_ext = 1. table 9-54 dvdd_ok register bits register bits value description 0 digital voltage regulator disabled or supply voltage not stable dvdd_ok 1 digital supply voltage has settled ? bit 1:0 ? dvreg_trim1:0 - reserved table 9-55 dvreg_trim register bits register bits value description 0 1.80v 1 1.75v 2 1.84v dvreg_trim1:0 3 1.88v 118 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.21 batmon ? battery monitor control and status register bit 7 6 5 4 na ($151) bat_low bat_low_en batmon_ok batmon_hr batmon read/write rw rw r rw initial value 0 0 0 0 bit 3 2 1 0 na ($151) batmon_vth3 batmon_vth2 batmon_vth1 batmon_vth0 batmon read/write rw rw rw rw initial value 0 0 1 0 this register configures the battery monitor to obs erve the supply voltage at evdd. the status of the evdd supply voltage is accessible by reading bit batmon_ok with respect to the actual batmon settings. furthermore the battery monitor interrupt can be controlled with the bits bat_low and bat_low_en similar to the function of the irq_status and irq_mask register for other radio tr ansceiver interrupts. ? bit 7 ? bat_low - battery monitor interrupt status a batmon interrupt is pending if this bit is set. w riting one to this bit if it has been at one will clear the interrupt. ? bit 6 ? bat_low_en - battery monitor interrupt enab le the battery monitor interrupt is enabled if this bi t is set to one. the battery monitor will not generate an interrupt if this bit is zero. ? bit 5 ? batmon_ok - battery monitor status the register bit batmon_ok indicates the level of t he external supply voltage with respect to the programmed threshold batmon_vth. table 9-56 batmon_ok register bits register bits value description 0 the battery voltage is below the threshold. batmon_ok 1 the battery voltage is above the threshold. ? bit 4 ? batmon_hr - battery monitor voltage range this bit sets the range and resolution of the batte ry monitor. table 9-57 batmon_hr register bits register bits value description 0 enables the low range, see batmon_vth batmon_hr 1 enables the high range, see batmon_vth ? bit 3:0 ? batmon_vth3:0 - battery monitor threshold voltage the threshold values for the battery monitor are se t by these register bits according to the following table. table 9-58 batmon_vth register bits register bits value description 0x0 2.550v / 1.70v (batmon_hr=1/0) 0x1 2.625v / 1.75v (batmon_hr=1/0) 0x2 2.700v / 1.80v (batmon_hr=1/0) batmon_vth3:0 0x3 2.775v / 1.85v (batmon_hr=1/0) 119 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x4 2.850v / 1.90v (batmon_hr=1/0) 0x5 2.925v / 1.95v (batmon_hr=1/0) 0x6 3.000v / 2.00v (batmon_hr=1/0) 0x7 3.075v / 2.05v (batmon_hr=1/0) 0x8 3.150v / 2.10v (batmon_hr=1/0) 0x9 3.225v / 2.15v (batmon_hr=1/0) 0xa 3.300v / 2.20v (batmon_hr=1/0) 0xb 3.375v / 2.25v (batmon_hr=1/0) 0xc 3.450v / 2.30v (batmon_hr=1/0) 0xd 3.525v / 2.35v (batmon_hr=1/0) 0xe 3.600v / 2.40v (batmon_hr=1/0) 0xf 3.675v / 2.45v (batmon_hr=1/0) 9.12.22 xosc_ctrl ? crystal oscillator control regi ster bit 7 6 5 4 na ($152) xtal_mode3 xtal_mode2 xtal_mode1 xtal_mode0 xosc_ct rl read/write rw rw rw rw initial value 1 1 1 1 bit 3 2 1 0 na ($152) xtal_trim3 xtal_trim2 xtal_trim1 xtal_trim0 xosc_ct rl read/write rw rw rw rw initial value 0 0 0 0 this register controls the operation of the 16mhz c rystal oscillator. ? bit 7:4 ? xtal_mode3:0 - crystal oscillator operati ng mode these register bits set the operating mode of the 1 6 mhz crystal oscillator. for normal operation the default value is set to xtal_mode = 0 xf after reset. for use with an external clock source it is recommended to set xtal _mode = 0x4. table 9-59 xtal_mode register bits register bits value description 0x4 internal crystal oscillator disabled; use external reference frequency. xtal_mode3:0 0xf internal crystal oscillator enabled; amplitude regulation of oscillation enabled. ? bit 3:0 ? xtal_trim3:0 - crystal oscillator load ca pacitance trimming these register bits control two internal capacitanc e arrays connected to pins xtal1 and xtal2. a capacitance value in the range from 0 pf to 4.5 pf is selectable with a resolution of 0.3 pf. table 9-60 xtal_trim register bits register bits value description 0x0 0.0 pf, trimming capacitors disconnected xtal_trim3:0 0x1 0.3 pf, trimming capacitor switched on 120 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x2 ... 0xf 4.5 pf, trimming capacitor switched on 9.12.23 rx_syn ? transceiver receiver sensitivity c ontrol register bit 7 6 na ($155) rx_pdt_dis res2 rx_syn read/write rw r initial value 0 0 bit 5 4 na ($155) res1 res0 rx_syn read/write r r initial value 0 0 bit 3 2 na ($155) rx_pdt_level3 rx_pdt_level2 rx_syn read/write rw rw initial value 0 0 bit 1 0 na ($155) rx_pdt_level1 rx_pdt_level0 rx_syn read/write rw rw initial value 0 0 this register controls the sensitivity threshold of the receiver. ? bit 7 ? rx_pdt_dis - prevent frame reception rx_pdt_dis = 1 prevents the reception of a frame ev en if the radio transceiver is in receive modes. an ongoing frame reception is not af fected. this operation mode is independent of the setting of register bits rx_pdt_ level. ? bit 6:4 ? res2:0 - reserved ? bit 3:0 ? rx_pdt_level3:0 - reduce receiver sensiti vity these register bits reduce the receiver sensitivity such that frames with a rssi level below the rx_pdt_level threshold level are not rece ived (rx_pdt_level>0). the threshold level can be calculated according to the following formula: rx_thres > rssi_base_val+3(rx_pdt_level-1), for rx_pdt_level> 0. if register bits rx_pdt_level>0 the current consumption of the recei ver in states rx_on and rx_aack_on is reduced by 500 a. if register bits r x_pdt_level=0 (reset value) all frames with a valid shr and phr are received, i ndependently of their signal strength. examples for certain register settings ar e given in the following table. table 9-61 rx_pdt_level register bits register bits value description 0x0 rx_thres rssi_base_val (reset value); rssi value not considered 0x1 rx_thres > rssi_base_val + 0 3; rssi > -90 dbm 0x2 ... rx_pdt_level3:0 0xe rx_thres > rssi_base_val + 13 3; 121 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description rssi > -51 dbm 0xf rx_thres > rssi_base_val + 14 3; rssi > -48 dbm 9.12.24 xah_ctrl_1 ? transceiver acknowledgment fra me control register 1 bit 7 6 5 4 na ($157) res1 res0 aack_fltr_res_ft aack_upld_res_ft xah_ctrl_1 read/write r r rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($157) res aack_ack_time aack_prom_mode res xah_ctrl_1 read/write r rw rw r initial value 0 0 0 0 this register is a multi-purpose control register f or various rx_aack settings. ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 5 ? aack_fltr_res_ft - filter reserved frames this register bit shall only be set if aack_upld_re s_ft = 1. if aack_fltr_res_ft = 1 reserved frame types are filte red similar to data frames as specified in ieee 802.15.4-2006. reserved frame typ es are explained in ieee 802.15.4 section 7.2.1.1.1. if aack_fltr_res_ft = 0 a receiv ed, reserved frame is only checked for a valid fcs. ? bit 4 ? aack_upld_res_ft - process reserved frames if aack_upld_res_ft = 1 received frames indicated a s reserved are further processed. a rx_end interrupt is generated if the f cs of those frames is valid. in conjunction with the configuration bit aack_fltr_re s_ft set, these frames are handled like ieee 802.15.4 compliant data frames du ring rx_aack transaction. an ami interrupt is issued if the address in the recei ved frame matches the node address. that means if a reserved frame passes the third lev el filter rules, an acknowledgment frame is generated and transmitted if it was reques ted by the received frame. if this is not wanted bit aack_dis_ack in register csma_seed_1 has to be set. ? bit 3 ? res - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 2 ? aack_ack_time - reduce acknowledgment time according to ieee 802.15.4, section 7.5.6.4.2 the t ransmission of an acknowledgment frame shall commence 12 symbols (aturnaroundtime) a fter the reception of the last symbol of a data or mac command frame. this is achi eved with the reset value of the register bit aack_ack_time. if aack_ack_time = 1 an acknowledgment frame is alternatively sent already 2 symbol periods (32 s) after the reception of the last symbol of a data or mac command frame. this may be applied to proprietary networks or networks using the high data rate modes to increase battery lifetime and to improve the overall data throughput. this setting affects a lso to acknowledgment frame response time for slotted acknowledgment operation. 122 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-62 aack_ack_time register bits register bits value description 0 12 symbols acknowledgment time aack_ack_time 1 2 symbols acknowledgment time ? bit 1 ? aack_prom_mode - enable promiscuous mode this register bit enables the promiscuous mode with in the rx_aack mode; refer to ieee 802.15.4-2006 chapter 7.5.6.5. if this bit is set, every incoming frame with a valid phr finishes with a rx_end interrupt even if the th ird level filter rules do not match or the fcs is not valid. the bit rx_crc_valid of regis ter phy_rssi is set accordingly. if this bit is set and a frame passes the third lev el filter rules, an acknowledgment frame is generated and transmitted unless disabled by bit aack_dis_ack of register csma_seed_1. ? bit 0 ? res - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. 9.12.25 ftn_ctrl ? transceiver filter tuning contro l register bit 7 6 5 4 na ($158) ftn_start resx6 resx5 resx4 ftn_ctrl read/write rw rw rw rw initial value 0 1 0 1 bit 3 2 1 0 na ($158) resx3 resx2 resx1 resx0 ftn_ctrl read/write rw rw rw rw initial value 1 0 0 0 this register controls the operation of the calibra tion loop of the filter tuning network. ? bit 7 ? ftn_start - start calibration loop of filte r tuning network ftn_start = 1 initiates the calibration of the filt er tuning network. when the calibration cycle has finished after at most 25 s the register bit is automatically reset to 0. ? bit 6:0 ? resx6:0 - reserved 9.12.26 pll_cf ? transceiver center frequency calib ration control register bit 7 6 na ($15a) pll_cf_start resx6 pll_cf read/write rw rw initial value 0 1 bit 5 4 na ($15a) resx5 resx4 pll_cf read/write rw rw initial value 0 1 123 8266c-mcu wireless-08/11 ATMEGA128RFA1 bit 3 2 na ($15a) resx3 resx2 pll_cf read/write rw rw initial value 0 1 bit 1 0 na ($15a) resx1 resx0 pll_cf read/write rw rw initial value 1 1 this register controls the operation of the center frequency calibration loop. ? bit 7 ? pll_cf_start - start center frequency calib ration pll_cf_start = 1 initiates the center frequency cal ibration. the calibration cycle has finished after 35 s (typical). the register bit is cleared immediately after finishing the calibration. ? bit 6:0 ? resx6:0 - reserved 9.12.27 pll_dcu ? transceiver delay cell calibratio n control register bit 7 6 5 4 na ($15b) pll_dcu_start resx6 resx5 resx4 pll_dcu read/write rw r rw rw initial value 0 0 1 0 bit 3 2 1 0 na ($15b) resx3 resx2 resx1 resx0 pll_dcu read/write rw rw rw rw initial value 0 0 0 0 this register controls the operation of the calibra tion loop of the delay cell. ? bit 7 ? pll_dcu_start - start delay cell calibratio n pll_dcu_start = 1 initiates the delay cell calibrat ion. the calibration cycle has finished after at most 6 s. the register bit is cl eared immediately after finishing the calibration. ? bit 6:0 ? resx6:0 - reserved 9.12.28 part_num ? device identification register ( part number) bit 7 6 5 4 3 2 1 0 na ($15c) part_num7:0 part_num read/write r r r r r r r r initial value 1 0 0 0 0 0 1 1 this register contains the part number of the devic e. ? bit 7:0 ? part_num7:0 - part number these bits decode the part number of the device acc ording to the following table. 124 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-63 part_num register bits register bits value description part_num7:0 0x83 ATMEGA128RFA1 part number 9.12.29 version_num ? device identification registe r (version number) bit 7 6 5 4 3 2 1 0 na ($15d) version_num7:0 version_num read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register contains the version number of the de vice. the device identification overwrites the reset value. ? bit 7:0 ? version_num7:0 - version number these bits decode the version number of the device according to the following table. table 9-64 version_num register bits register bits value description 2 revision ab 3 revision c version_num7:0 4 revision d 9.12.30 man_id_0 ? device identification register ( manufacture id low byte) bit 7 6 5 4 3 2 1 0 na ($15e) man_id_07:00 man_id_0 read/write r r r r r r r r initial value 0 0 0 1 1 1 1 1 bits [7:0] of the 32-bit jedec manufacturer id are stored in this register. bits [15:8] are stored in register man_id_1. the highest 16 bits of the jedec id are not stored in registers. ? bit 7:0 ? man_id_07:00 - manufacturer id (low byte) these bits contain bits [7:0] of the 32-bit jedec m anufacturer id. table 9-65 man_id_0 register bits register bits value description man_id_07:00 0x1f atmel jedec manufacturer id, bits [7:0] of 32 bit manufacturer id: 00 00 00 1f 9.12.31 man_id_1 ? device identification register ( manufacture id high byte) bit 7 6 5 4 3 2 1 0 na ($15f) man_id_17:10 man_id_1 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 125 8266c-mcu wireless-08/11 ATMEGA128RFA1 bits [15:8] of the 32-bit jedec manufacturer id are stored in this register. bits [7:0] are stored in register man_id_0. the highest 16 bits of the jedec id are not stored in registers. ? bit 7:0 ? man_id_17:10 - manufacturer id (high byte ) these bits contain bits [15:8] of the 32-bit jedec manufacturer id. table 9-66 man_id_1 register bits register bits value description man_id_17:10 0x00 atmel jedec manufacturer id, bits [15:8] of 32 bit manufacturer id: 00 00 00 1f 9.12.32 short_addr_0 ? transceiver mac short addres s register (low byte) bit 7 6 5 4 3 2 1 0 na ($160) short_addr_07:00 short_addr_0 read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 this register contains the lower 8 bits of the mac short address for frame filter address recognition. ? bit 7:0 ? short_addr_07:00 - mac short address these bits contain the bits [7:0] of the mac short address. 9.12.33 short_addr_1 ? transceiver mac short addres s register (high byte) bit 7 6 5 4 3 2 1 0 na ($161) short_addr_17:10 short_addr_1 read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 this register contains the upper 8 bits of the mac short address for frame filter address recognition. ? bit 7:0 ? short_addr_17:10 - mac short address these bits contain the bits [15:8] of the mac short address. 9.12.34 pan_id_0 ? transceiver personal area networ k id register (low byte) bit 7 6 5 4 3 2 1 0 na ($162) pan_id_07:00 pan_id_0 read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 this register contains the lower 8 bits of the mac pan id for frame filter address recognition. ? bit 7:0 ? pan_id_07:00 - mac personal area network id 126 8266c-mcu wireless-08/11 ATMEGA128RFA1 these bits contain the bits [7:0] of the mac pan id . 9.12.35 pan_id_1 ? transceiver personal area networ k id register (high byte) bit 7 6 5 4 3 2 1 0 na ($163) pan_id_17:10 pan_id_1 read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 this register contains the upper 8 bits of the mac pan id for frame filter address recognition. ? bit 7:0 ? pan_id_17:10 - mac personal area network id these bits contain the bits [15:8] of the mac pan i d. 9.12.36 ieee_addr_0 ? transceiver mac ieee address register 0 bit 7 6 5 4 3 2 1 0 na ($164) ieee_addr_07:00 ieee_addr_0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [7:0] of the mac ie ee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_07:00 - mac ieee address these bits map to the bits [7:0] of the 64 bit mac ieee address. 9.12.37 ieee_addr_1 ? transceiver mac ieee address register 1 bit 7 6 5 4 3 2 1 0 na ($165) ieee_addr_17:10 ieee_addr_1 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [15:8] of the mac i eee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_17:10 - mac ieee address these bits map to the bits [15:8] of the 64 bit mac ieee address. 9.12.38 ieee_addr_2 ? transceiver mac ieee address register 2 bit 7 6 5 4 3 2 1 0 na ($166) ieee_addr_27:20 ieee_addr_2 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 127 8266c-mcu wireless-08/11 ATMEGA128RFA1 this register contains the bits [23:16] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_27:20 - mac ieee address these bits map to the bits [23:16] of the 64 bit ma c ieee address. 9.12.39 ieee_addr_3 ? transceiver mac ieee address register 3 bit 7 6 5 4 3 2 1 0 na ($167) ieee_addr_37:30 ieee_addr_3 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [31:24] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_37:30 - mac ieee address these bits map to the bits [31:24] of the 64 bit ma c ieee address. 9.12.40 ieee_addr_4 ? transceiver mac ieee address register 4 bit 7 6 5 4 3 2 1 0 na ($168) ieee_addr_47:40 ieee_addr_4 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [39:32] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_47:40 - mac ieee address these bits map to the bits [39:32] of the 64 bit ma c ieee address. 9.12.41 ieee_addr_5 ? transceiver mac ieee address register 5 bit 7 6 5 4 3 2 1 0 na ($169) ieee_addr_57:50 ieee_addr_5 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [47:40] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_57:50 - mac ieee address these bits map to the bits [47:40] of the 64 bit ma c ieee address. 128 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.42 ieee_addr_6 ? transceiver mac ieee address register 6 bit 7 6 5 4 3 2 1 0 na ($16a) ieee_addr_67:60 ieee_addr_6 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [55:48] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_67:60 - mac ieee address these bits map to the bits [55:48] of the 64 bit ma c ieee address. 9.12.43 ieee_addr_7 ? transceiver mac ieee address register 7 bit 7 6 5 4 3 2 1 0 na ($16b) ieee_addr_77:70 ieee_addr_7 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the bits [63:56] of the mac ieee address for frame filter address recognition. ? bit 7:0 ? ieee_addr_77:70 - mac ieee address these bits map to the bits [63:56] of the 64 bit ma c ieee address. 9.12.44 xah_ctrl_0 ? transceiver extended operating mode control register bit 7 6 na ($16c) max_frame_retries3 max_frame_retries2 xah_ctrl_0 read/write rw rw initial value 0 0 bit 5 4 na ($16c) max_frame_retries1 max_frame_retries0 xah_ctrl_0 read/write rw rw initial value 1 1 bit 3 2 na ($16c) max_csma_retries2 max_csma_retries1 xah_ctrl_0 read/write rw rw initial value 1 0 bit 1 0 na ($16c) max_csma_retries0 slotted_operation xah_ctrl_0 read/write rw rw initial value 0 0 this register is used to control various settings o f the extended operating mode. 129 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:4 ? max_frame_retries3:0 - maximum number of frame re- transmission attempts the setting of max_frame_retries in tx_aret mode sp ecifies the number of attempts to retransmit a frame when it was not ackn owledged by the recipient. the transaction gets canceled if the number of attempts exceeds max_frame_retries. table 9-67 max_frame_retries register bits register bits value description 0x0 retransmission of frame is not attempted. 0x1 retransmission of frame is attempted once. 0x2 ... max_frame_retries3:0 0xf retransmission of frame is attempted 15 times. ? bit 3:1 ? max_csma_retries2:0 - maximum number of c sma-ca procedure repetition attempts max_csma_retries specifies the number of retries in tx_aret mode to repeat the csma-ca procedure before the transaction gets cance led. according to ieee 802.15.4 the valid range of max_csma_retries is 0 to 5. a va lue of max_csma_retries = 7 initiates an immediate frame transmission without performing csma-ca. this may especially be required for slotted acknowledgment o peration. max_csma_retries = 6 is reserved. table 9-68 max_csma_retries register bits register bits value description 0x0 no repetition of csma-ca procedure 0x1 one repetition of csma-ca procedure 0x2 ... 0x5 five repetitions (highest ieee 802.15.4 compliant value) 0x6 reserved max_csma_retries2:0 0x7 immediate frame re-transmission without performing csma-ca ? bit 0 ? slotted_operation - set slotted acknowledgm ent when using rx_aack mode in networks operating in be acon or slotted mode according to ieee 802.15.4-2006, chapter 5.5.1 the register bit slotted_operation indicates that acknowledgment fra mes are to be sent on back- off slot boundaries (slotted acknowledgment). if th is register bit is set the acknowledgment frame transmission has to be initiat ed by the application software using bit slptr of register trxpr. this waiting sta te is signaled in sub register trac_status of register trx_state with value succes s_wait_for_ack. table 9-69 slotted_operation register bits register bits value description 0 the radio transceiver operates in unslotted mode. an acknowledgment frame is automatically sent if requested. slotted_operation 1 the transmission of an acknowledgment frame has to be controlled by the microcontroller. 130 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.12.45 csma_seed_0 ? transceiver csma-ca random nu mber generator seed register bit 7 6 5 4 3 2 1 0 na ($16d) csma_seed_07:00 csma_seed_0 read/write rw rw rw rw rw rw rw rw initial value 1 1 1 0 1 0 1 0 this register contains the lower 8 bits of the csma _seed. the upper 3 bits are part of register csma_seed_1. csma_seed is the seed for the random number generation that determines the length of the back-off period i n the csma-ca algorithm. it is recommended to initialize registers csma_seed by ra ndom values. this can be done using the bits rnd_value of register phy_rssi. ? bit 7:0 ? csma_seed_07:00 - seed value for csma ran dom number generator these bits contain the bits [7:0] of the csma_seed. 9.12.46 csma_seed_1 ? transceiver acknowledgment fr ame control register 2 bit 7 6 na ($16e) aack_fvn_mode1 aack_fvn_mode0 csma_seed_1 read/write rw rw initial value 0 1 bit 5 4 na ($16e) aack_set_pd aack_dis_ack csma_seed_1 read/write rw rw initial value 0 0 bit 3 2 na ($16e) aack_i_am_coord csma_seed_12 csma_seed_1 read/write rw rw initial value 0 0 bit 1 0 na ($16e) csma_seed_11 csma_seed_10 csma_seed_1 read/write rw rw initial value 1 0 this register is a control register for rx_aack and contains a part of the csma_seed for the csma-ca algorithm. ? bit 7:6 ? aack_fvn_mode1:0 - acknowledgment frame f ilter mode the frame control field of the mac header (mhr) con tains a frame version subfield. the setting of aack_fvn_mode specifies the frame fi ltering behavior of the radio transceiver. according to the content of these regi ster bits the radio transceiver passes frames with a specific frame version number, number group or independent of the frame version number. thus the register bits aack_f vn_mode define the maximum acceptable frame version. received frames with a hi gher frame version number than configured do not pass the address filter and are n ot acknowledged. 131 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-70 aack_fvn_mode register bits register bits value description 0 acknowledge frames with version number 0 1 acknowledge frames with version number 0 or 1 2 acknowledge frames with version number 0 or 1 or 2 aack_fvn_mode1:0 3 acknowledge frames independent of frame version number ? bit 5 ? aack_set_pd - set frame pending sub-field the content of aack_set_pd bit is copied into the f rame pending subfield of the acknowledgment frame if the acknowledgment is the a nswer to a data request mac command frame. if in addition the bits aack_fvn_mod e of this register are configured to accept frames with a frame version ot her than 0 or 1, the content of register bit aack_set_pd is also copied into the fr ame pending subfield of the acknowledgment frame for any mac command frame with a frame version of 2 or 3 that have the security enabled subfield set to 1. this i s done in the assumption that a future version of the ieee 802.15.4 standard might change the length or structure of the auxiliary security header, so that it is not possib le to safely detect whether the mac command frame is actually a data request command or not. ? bit 4 ? aack_dis_ack - disable acknowledgment frame transmission if this bit is set no acknowledgment frames are tra nsmitted in rx_aack extended operating mode even if requested. ? bit 3 ? aack_i_am_coord - set personal area network coordinator this register bit has to be set if the node is a pa n coordinator. it is used for address filtering in rx_aack. ? bit 2:0 ? csma_seed_12:10 - seed value for csma ran dom number generator these bits contain the bits [10:8] of the csma_seed . the lower part is defined in register csma_seed_0. see register csma_seed_0 for details. 9.12.47 csma_be ? transceiver csma-ca back-off expo nent control register bit 7 6 5 4 na ($16f) max_be3 max_be2 max_be1 max_be0 csma_be read/write rw rw rw rw initial value 0 1 0 1 bit 3 2 1 0 na ($16f) min_be3 min_be2 min_be1 min_be0 csma_be read/write rw rw rw rw initial value 0 0 1 1 this register controls the back-off exponent for th e csma-ca procedure. ? bit 7:4 ? max_be3:0 - maximum back-off exponent these register bits define the maximum back-off exp onent used in the csma-ca algorithm to generate a pseudo random number for ba ck off the cca. for details refer to ieee 802.15.4-2006, section 7.5.1.4. valid value s are 3 to 8. 132 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 9-71 max_be register bits register bits value description 1 this value is not valid for the maximum back-off exponent. 2 this value is not valid for the maximum back-off exponent. 3 minimum, ieee compliant value for the maximum back-off exponent. 4 ... max_be3:0 8 maximum, ieee compliant value for the maximum back-off exponent. ? bit 3:0 ? min_be3:0 - minimum back-off exponent these register bits define the minimum back-off exp onent used in the csma-ca algorithm to generate a pseudo random number for ba ck off the cca. for details refer to ieee 802.15.4-2006, section 7.5.1.4. valid valu es are max_be, max_be-1), ..., 0. if min_be = 0 and max_be = 0 the cca back off perio d is always set to 0. table 9-72 min_be register bits register bits value description 0 minimum value of minimum back-off exponent. 1 ... min_be3:0 8 maximum value of minimum back-off exponent. min_be must be smaller or equal to max_be. 9.12.48 tst_ctrl_digi ? transceiver digital test co ntrol register bit 7 6 na ($176) resx7 resx6 tst_ctrl_digi read/write rw rw initial value 0 0 bit 5 4 na ($176) resx5 resx4 tst_ctrl_digi read/write rw rw initial value 0 0 bit 3 2 na ($176) tst_ctrl_dig3 tst_ctrl_dig2 tst_ctrl_digi read/write rw rw initial value 0 0 bit 1 0 na ($176) tst_ctrl_dig1 tst_ctrl_dig0 tst_ctrl_digi read/write rw rw initial value 0 0 this register takes part in the activation sequence of the continuous transmission test mode. other functionality of this register is reser ved for internal use. ? bit 7:4 ? resx7:4 - reserved 133 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 3:0 ? tst_ctrl_dig3:0 - digital test controller register this sub-register selects a test controller functio n. all values not listed int the following table are reserved for internal use. table 9-73 tst_ctrl_dig register bits register bits value description 0 normal (no test is active) tst_ctrl_dig3:0 15 tst_cont_tx (continuous transmit) 9.12.49 tst_rx_length ? transceiver received frame length register bit 7 6 5 4 na ($17b) rx_length7 rx_length6 rx_length5 rx_length4 tst_rx_ length read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($17b) rx_length3 rx_length2 rx_length1 rx_length0 tst_rx_ length read/write rw rw rw rw initial value 0 0 0 0 this register contains the frame length information of a received frame. this information is not stored in the frame buffer. the frame length information is written to this register after the last received octet. ? bit 7:0 ? rx_length7:0 - received frame length these bits contain the length of the last received frame. 9.12.50 trxfbst ? start of frame buffer bit 7 6 5 4 3 2 1 0 na ($180) trxfbst7:0 trxfbst read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 first byte of the 128 byte long frame buffer of the trx24. ? bit 7:0 ? trxfbst7:0 - frame buffer start byte 9.12.51 trxfbend ? end of frame buffer bit 7 6 5 4 3 2 1 0 na ($1ff) trxfbend7:0 trxfbend read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register is the last byte of the 128 byte long frame buffer of the radio transceiver. ? bit 7:0 ? trxfbend7:0 - frame buffer end byte 134 8266c-mcu wireless-08/11 ATMEGA128RFA1 32bit symbol counter compare unit 1 interrupt generation 320s backoff slot counter configuration register compare unit 2 compare unit 3 clock prescaler clock select sfd timestamp beacon timestamp 32khz rtc 16mhz xtal avr i/o bus 10 mac symbol counter figure 10-1. symbol counter overview 10.1 main features the mac symbol counter provides symbol timing infor mation for ieee 802.15.4 wireless networks. the counter time base can be der ived from the 16 mhz crystal or the rtc (32.768 khz crystal on tosc) during operati on. in deep-sleep mode the counter operates from the rtc clock. the module pro vides the following features: ? backoff slot counter with interrupt generation ? counter clock source selection between xtal1 (16 mh z) and tosc1 (rtc) ? automatic rtc clock selection for sleep mode operat ion and automatic fallback ? 3 independent compare units with relative and absol ute compare mode and interrupt generation (support for slotted operation and superframe handling) ? low-power, deep-sleep mode operation and system wak e up with all symbol counter interrupt events ? automatic sfd and incoming beacon timestamping ? manual beacon timestamping ? manual timer synchronization within a 16 s symbol period by resetting clock prescaler and backoff slot counter ? atomic read/write access for 32 bit registers 10.2 clock source selection and sleep/active mode o peration the symbol counter can be sourced by the transceive r clock or by the asynchronous real time clock (rtc) oscillator. if the transceive r goes from active mode into sleep mode, the symbol counter clock source is switched t o the rtc clock automatically. a 135 8266c-mcu wireless-08/11 ATMEGA128RFA1 clock source change is indicated in the bit sccksel of register "sccr0 ? symbol counter control register 0" on page 144 . the bit sccksel can not be written if the radio transceiver is in sleep mode. after wake up, the counter switches back to the clo ck source which was selected before going to sleep mode. switching the clock source fro m rtc to 16 mhz resets the 16 mhz clock prescaler. this makes sure, that after sw itching back the clock source, the symbol counter starts counting with a full 16 s sy mbol period. the clock source can be selected with bit sccksel i n the sccr0 register note: the avr system clock has to be at least 4 times th e symbol counter clock frequency. the symbol counter clock frequency is us ually 62.5khz, which would require a minimum of 250khz avr system clock frequency. 10.3 32 bit register access (atomic read/write) all 32 bit registers support atomic read or write o peration. that means reading or writing the least significant xxx ll byte (the register name ends in ll) updates or c aptures the complete 32 bit value. read access: 1. reading the ll-byte captures the 32 bit value in a temporary register 2. read the upper 3 bytes write access: 1. write the upper 3 byte 2. writing the ll-byte stores the 32 bit value in the counter registers the same temporary register is used for all 32 bit register of the mac symbol counter. 10.4 symbol counter (32 bit, sccnt) the symbol counter is a 32 bit counter which can be sourced by a 62.5 khz clock, derived from the 16 mhz system clock or from the rt c (32.768 khz). if sourced by the rtc, a special control circuitry ensures that the c ounter error does not exceed one symbol period. the symbol counter can be set or read from the cont roller. reading must start with the least significant byte. if the least significant by te is accessed, all 32 bit of the counter are captured. a read access to sccntll requires a m aximum of three avr clocks. reading the upper three bytes of the counter requir es two cpu clock cycles for each byte. writing to the counter should start with the most s ignificant byte. writing the least significant byte initiates the counter update and t he new 32 bit counter value is loaded into the counter with the next available counter cl ock edge. this can take up to 16 s beginning from the low byte write operation, if the counter is sourced by the rtc. if the counter clock is derived from the 16 mhz clo ck system, the new counter value is stored immediately. during the counter update cycle, the counter busy f lag scbsy in the scsr register is set to ?1?. as long as this bit is ?1?, no further read/write access to the counter should be initiated. the same applies if the avr is forced to any sleep mode with disabled avr clock, right after writing to the sccnt register. i f the counter busy flag is not checked before going to sleep, it is possible that the coun ter register is not updated correctly. the symbol counter overflow is indicated by a overf low interrupt. the interrupt is generated when the counter turns from 0xffffffff to 0x00000000. 10.5 symbol counter sfd timestamp register (32 bit, sctsr, read only) the sfd timestamp register stores the symbol counte r value at the time, the sfd has been detected. the register value becomes valid if a valid frame length byte (frame 136 8266c-mcu wireless-08/11 ATMEGA128RFA1 length > 0) has been detected, but it is not checke d if the received frame is valid (crc check). timestamping must be enabled in the control register (bit sctse of register sccr0). a read access to sctsrll requires a maximum of three avr clocks. reading the upper three bytes of the timestamp requ ires two cpu clock cycles for each byte. note that there is no separate interrupt provided f or timestamping. instead the trx24_rx_start interrupt can be used (see "interrupt vectors in ATMEGA128RFA1" on page 212 ). 10.6 symbol counter beacon timestamp register (32 b it, scbtsr) if timestamping is enabled in the sccr register, th e beacon timestamp register is updated with the sfd timestamp at the end of the re ceived frame, if the received frame was a beacon frame with valid fcs and: ? source pan identifier == {pan_id_1, pan_id_0} or ? {pan_id_1, pan_id_0} == 0xffff pan_id_0 and pan_id_1 are register of the radio tra nsceiver, see "pan_id_0 ? transceiver personal area network id register (low byte)" on page 125 . beacon timestamps can also be generated manually. w riting ?1? to scmbts of register sccr0 captures the current symbol counter value and stores it in the beacon timestamp register. the bit is cleared automaticall y afterwards. it is also possible to manually set the register in order to provide a distinct starting value for the relative compare modes (see next section). 10.7 compare unit (3x 32 bit, scocr1, scocr2, scocr 3) the compare unit contains 3 independent 32 bit comp are modules and is used to compare the current counter value with the value st ored in the compare register, and optionally the beacon timestamp register. there are two possible modes available which can be selected separately for all three comp are modules: 1. absolute compare: in this mode the value stored in the compare regis ter is compared directly with the symbol counter value (sc cnt == scocrx). if the values are equal an interrupt is generated. 2. relative compare: this mode allows the compare between the current s ymbol counter value and the compare value plus the beacon timestamp value (sccnt == scbtsr + scocrx). this mode can be used to generate an interrupt at a time offset relative to the value stored in the beacon timestam p register. note that a beacon timestamp is valid after a valid fcs. the relative compare must exceed the beacon length, otherwise no relative com pare interrupt will occur. 10.8 interrupt control registers the interrupt status and mask registers control the interrupt generation. each interrupt can be enabled in scirqm (symbol counter irq mask r egister). if an interrupt occurs, the appropriate interrupt flag within the i nterrupt status register is set regardless of the interrupt mask register setting. if the appr opriate interrupt is enabled, an interrupt is generated. the interrupt flags can be cleared either by: 1. entering the respective interrupt handler, or 2. writing ?one? to the according interrupt flag in the interrupt status register. 137 8266c-mcu wireless-08/11 ATMEGA128RFA1 all interrupts can be used to wakeup the controller from any sleep state. 10.9 backoff slot counter the backoff slot counter can be used to provide acc urate mac protocol timing. the counter is sourced by the transceiver clock and wor ks only if the transceiver clock is running. if the transceiver is disabled or in sleep mode the counter is also disabled. the counter generates periodic interrupts every 20 symbols, i.e. every 320 s. 10.10 symbol counter usage 10.10.1 sfd and beacon timestamp generation the sfd timestamp register is updated with the symb ol counter value at the time the sfd value has been received completely. for an inco ming frame, the register is valid after the rx_start irq was issued until the next rx _start irq. sfd timestamps are generated for all incoming frames with valid sf d and length field even if the psdu is corrupted (invalid fcs). figure 10-2. sfd and beacon timestamp generation note that figure 10-2 contains no exact timing info rmation; it is for visualization only. the beacon timestamp register is updated with the s fd timestamp value at the end of the frame (rx_end irq), if the received frame was a beacon frame with valid fcs and expected source pan identifier or { pan_id_1, pan_i d_0} = 0xffff. the register value is valid until a new beacon fram e has been received or the beacon timestamp is updated manually. a manual beacon time stamp can be generated by writing ?1? to scmbts of the sccr0 register. 10.10.2 relative compare mode for superframe access timing the ieee 802.15.4 describes a superframe structure which contains different time slots where a device can access the channel. 138 8266c-mcu wireless-08/11 ATMEGA128RFA1 the symbol counter together with the three compare units provide support for waking up the device at the right time to receive the beac on for superframe synchronization and at certain times within the superframe. a typical superframe timing scenario using the symb ol counter relative compare mode is shown in figure 10-3 below . the symbol counter values in the figure do not re flect realistic time intervals but demonstrate the princi ple of operation. figure 10-3. relative compare mode 326 beacon beacon 327 328 329 324 325 404 405 406 407 402 403 482 483 484 485 480 481 637 638 640 641 635 636 323 activation activation the compare match registers are programmed with sym bol intervals relative to the beacon frame sfd timestamp. for instance the sccmp1 is programmed to 80, because the first granted time slot (gts1) is expec ted 80 symbols after the beacon frame. register sccmp2 is programmed to 156 to meet gts3 156 symbols after the beacon frame. sccmp3 is programmed to 312. this is the time interval where the beacon of the next superframe is expected. because it requires some time to activate the transceiver and there is also some timing drift possible, the compare interrupt must be programmed to wake up some symbols in advance to make sure the next beacon is not missed. if the controller receives a compare match wake up event it is activating the transceiver. after the frame operations are finished, the system can go back to sleep until the next compare match event occurs. 10.11 register description 10.11.1 sccnthh ? symbol counter register hh-byte bit 7 6 5 4 3 2 1 0 na ($e4) sccnthh7:0 sccnthh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 139 8266c-mcu wireless-08/11 ATMEGA128RFA1 this register contains the most significant byte of the 32 bit symbol counter. ? bit 7:0 ? sccnthh7:0 - symbol counter register hh-b yte 10.11.2 sccnthl ? symbol counter register hl-byte bit 7 6 5 4 3 2 1 0 na ($e3) sccnthl7:0 sccnthl read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit symbol counter. ? bit 7:0 ? sccnthl7:0 - symbol counter register hl-b yte 10.11.3 sccntlh ? symbol counter register lh-byte bit 7 6 5 4 3 2 1 0 na ($e2) sccntlh7:0 sccntlh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit symbol counter. ? bit 7:0 ? sccntlh7:0 - symbol counter register lh-b yte 10.11.4 sccntll ? symbol counter register ll-byte bit 7 6 5 4 3 2 1 0 na ($e1) sccntll7:0 sccntll read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit symbol counter. ? bit 7:0 ? sccntll7:0 - symbol counter register ll-b yte 10.11.5 sctsrhh ? symbol counter frame timestamp re gister hh-byte bit 7 6 5 4 3 2 1 0 na ($ec) sctsrhh7:0 sctsrhh read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register contains the most significant byte of the 32 bit frame (sfd) timestamp register ? bit 7:0 ? sctsrhh7:0 - symbol counter frame timesta mp register hh-byte 140 8266c-mcu wireless-08/11 ATMEGA128RFA1 10.11.6 sctsrhl ? symbol counter frame timestamp re gister hl-byte bit 7 6 5 4 3 2 1 0 na ($eb) sctsrhl7:0 sctsrhl read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit frame (sfd) timestamp register ? bit 7:0 ? sctsrhl7:0 - symbol counter frame timesta mp register hl-byte 10.11.7 sctsrlh ? symbol counter frame timestamp re gister lh-byte bit 7 6 5 4 3 2 1 0 na ($ea) sctsrlh7:0 sctsrlh read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit frame (sfd) timestamp register ? bit 7:0 ? sctsrlh7:0 - symbol counter frame timesta mp register lh-byte 10.11.8 sctsrll ? symbol counter frame timestamp re gister ll-byte bit 7 6 5 4 3 2 1 0 na ($e9) sctsrll7:0 sctsrll read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit frame (sfd) timestamp register ? bit 7:0 ? sctsrll7:0 - symbol counter frame timesta mp register ll-byte 10.11.9 scbtsrhh ? symbol counter beacon timestamp register hh-byte bit 7 6 5 4 3 2 1 0 na ($e8) scbtsrhh7:0 scbtsrhh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the most significant byte of the 32 bit beacon timestamp register. the beacon timestamp register is updated with the contents of the frame timestamp register if the received frame was a vali d beacon frame with matching source pan identifier or register {pan_id_1, pan_id _0} = 0xffff. ? bit 7:0 ? scbtsrhh7:0 - symbol counter beacon times tamp register hh- byte 141 8266c-mcu wireless-08/11 ATMEGA128RFA1 10.11.10 scbtsrhl ? symbol counter beacon timestamp register hl-byte bit 7 6 5 4 3 2 1 0 na ($e7) scbtsrhl7:0 scbtsrhl read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit beacon timestamp register. ? bit 7:0 ? scbtsrhl7:0 - symbol counter beacon times tamp register hl- byte 10.11.11 scbtsrlh ? symbol counter beacon timestamp register lh-byte bit 7 6 5 4 3 2 1 0 na ($e6) scbtsrlh7:0 scbtsrlh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit beacon timestamp register. ? bit 7:0 ? scbtsrlh7:0 - symbol counter beacon times tamp register lh- byte 10.11.12 scbtsrll ? symbol counter beacon timestamp register ll-byte bit 7 6 5 4 3 2 1 0 na ($e5) scbtsrll7:0 scbtsrll read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit beacon timestamp register. ? bit 7:0 ? scbtsrll7:0 - symbol counter beacon times tamp register ll-byte 10.11.13 scocr1hh ? symbol counter output compare r egister 1 hh-byte bit 7 6 5 4 3 2 1 0 na ($f8) scocr1hh7:0 scocr1hh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the most significant byte of the 32 bit compare value for the first compare unit 142 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:0 ? scocr1hh7:0 - symbol counter output compa re register 1 hh-byte 10.11.14 scocr1hl ? symbol counter output compare r egister 1 hl-byte bit 7 6 5 4 3 2 1 0 na ($f7) scocr1hl7:0 scocr1hl read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit compare value for the first compare unit ? bit 7:0 ? scocr1hl7:0 - symbol counter output compa re register 1 hl-byte 10.11.15 scocr1lh ? symbol counter output compare r egister 1 lh-byte bit 7 6 5 4 3 2 1 0 na ($f6) scocr1lh7:0 scocr1lh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit compare value for the first compare unit ? bit 7:0 ? scocr1lh7:0 - symbol counter output compa re register 1 lh-byte 10.11.16 scocr1ll ? symbol counter output compare r egister 1 ll-byte bit 7 6 5 4 3 2 1 0 na ($f5) scocr1ll7:0 scocr1ll read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit compare value for the first compare unit ? bit 7:0 ? scocr1ll7:0 - symbol counter output compa re register 1 ll-byte 10.11.17 scocr2hh ? symbol counter output compare r egister 2 hh-byte bit 7 6 5 4 3 2 1 0 na ($f4) scocr2hh7:0 scocr2hh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the most significant byte of the 32 bit compare value for the second compare unit ? bit 7:0 ? scocr2hh7:0 - symbol counter output compa re register 2 hh-byte 143 8266c-mcu wireless-08/11 ATMEGA128RFA1 10.11.18 scocr2hl ? symbol counter output compare r egister 2 hl-byte bit 7 6 5 4 3 2 1 0 na ($f3) scocr2hl7:0 scocr2hl read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit compare value for the second compare unit ? bit 7:0 ? scocr2hl7:0 - symbol counter output compa re register 2 hl-byte 10.11.19 scocr2lh ? symbol counter output compare r egister 2 lh-byte bit 7 6 5 4 3 2 1 0 na ($f2) scocr2lh7:0 scocr2lh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit compare value for the second compare unit ? bit 7:0 ? scocr2lh7:0 - symbol counter output compa re register 2 lh-byte 10.11.20 scocr2ll ? symbol counter output compare r egister 2 ll-byte bit 7 6 5 4 3 2 1 0 na ($f1) scocr2ll7:0 scocr2ll read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit compare value for the second compare unit ? bit 7:0 ? scocr2ll7:0 - symbol counter output compa re register 2 ll-byte 10.11.21 scocr3hh ? symbol counter output compare r egister 3 hh-byte bit 7 6 5 4 3 2 1 0 na ($f0) scocr3hh7:0 scocr3hh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the most significant byte of the 32 bit compare value for the third compare unit ? bit 7:0 ? scocr3hh7:0 - symbol counter output compa re register 3 hh-byte 144 8266c-mcu wireless-08/11 ATMEGA128RFA1 10.11.22 scocr3hl ? symbol counter output compare r egister 3 hl-byte bit 7 6 5 4 3 2 1 0 na ($ef) scocr3hl7:0 scocr3hl read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second most significant byte of the 32 bit compare value for the third compare unit ? bit 7:0 ? scocr3hl7:0 - symbol counter output compa re register 3 hl-byte 10.11.23 scocr3lh ? symbol counter output compare r egister 3 lh-byte bit 7 6 5 4 3 2 1 0 na ($ee) scocr3lh7:0 scocr3lh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the second least significant byte of the 32 bit compare value for the third compare unit ? bit 7:0 ? scocr3lh7:0 - symbol counter output compa re register 3 lh-byte 10.11.24 scocr3ll ? symbol counter output compare r egister 3 ll-byte bit 7 6 5 4 3 2 1 0 na ($ed) scocr3ll7:0 scocr3ll read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register contains the least significant byte o f the 32 bit compare value for the third compare unit ? bit 7:0 ? scocr3ll7:0 - symbol counter output compa re register 3 ll-byte 10.11.25 sccr0 ? symbol counter control register 0 bit 7 6 5 4 3 2 1 0 na ($dc) scres scmbts scen sccksel sctse sccmp3 sccmp2 sccmp1 sccr0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the control register 0 is used to setup the operati ng mode of the symbol counter and the compare units ? bit 7 ? scres - symbol counter synchronization if this bit is set to 1, the 16 mhz clock prescaler as well as the backoff slot counter is cleared. this function can be used to align the sym bol timing within one 16 s symbol period and to restart the backoff slot counter with a complete 320 s period. this 145 8266c-mcu wireless-08/11 ATMEGA128RFA1 feature works only if the symbol counter module ope rates with the 16 mhz clock from xtal1. after switching to rtc clock source, the sym bol period synchronization is lost. this bit is cleared automatically. ? bit 6 ? scmbts - manual beacon timestamp with this bit a manual beacon timestamp can be gene rated. if set to 1, the current symbol counter value is stored into the beacon time stamp register. the bit is cleared afterwards. the manual beacon timestamping can be u sed in conjunction with the relative compare mode of the three compare units to generate compare match interrupts without having a beacon frame received. ? bit 5 ? scen - symbol counter enable this bit activates the symbol counter module. if th e bit is not set, the counter, backoff slot counter and the compare unit are disabled and disconnected from the clock. in this way the power consumption can be reduced. all regis ters can be accessed, but write access to the counter register sccnt is not possibl e. ? bit 4 ? sccksel - symbol counter clock source selec t with this bit the clock source for the symbol count er can be selected. if the bit is one, the rtc clock from tosc1 is selected, otherwise the symbol counter operates with the clock from xtal1. during transceiver sleep modes th e clock falls back to the rtc clock source, regardless of the selected clock. after wak eup, it switches back to the previosly selected clock source. ? bit 3 ? sctse - symbol counter automatic timestampi ng enable this bit enables automatic sfd and beacon timestamp ing. if the bit is zero, no automatic timestamp capturing is possible. only man ual beacon timestamping can be used. ? bit 2 ? sccmp3 - symbol counter compare unit 3 mode select this bit enables the relative compare mode for comp are unit 3. if enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 3 (sccnt == scbts+s cocr3). otherwise, the counter is compared against the copare register 3 ( sccnt == scocr3). ? bit 1 ? sccmp2 - symbol counter compare unit 2 mode select this bit enables the relative compare mode for comp are unit 2. if enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 2 (sccnt == scbts+s cocr2). otherwise, the counter is compared against the copare register 2 ( sccnt == scocr2). ? bit 0 ? sccmp1 - symbol counter compare unit 1 mode select this bit enables the relative compare mode for comp are unit 1. if enabled, the counter value is compared against the content of the beacon timestamp register plus the content of the compare register 1 (sccnt == scbts+s cocr1). otherwise, the counter is compared against the copare register 1 ( sccnt == scocr1). 10.11.26 sccr1 ? symbol counter control register 1 bit 7 6 5 4 3 2 1 0 na ($dd) res6 res5 res4 resx4 resx3 resx2 resx1 scenbo sccr1 read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 146 8266c-mcu wireless-08/11 ATMEGA128RFA1 this register is used to enable the backoff slot co unter. ? bit 7:5 ? res6:4 - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 4:1 ? resx4:1 - reserved ? bit 0 ? scenbo - backoff slot counter enable if this bit is set, the backoff slot counter start s working. to enable the corresponding irq the scirqm register must be updated. 10.11.27 scsr ? symbol counter status register bit 7 6 5 4 3 2 1 0 na ($de) res6 res5 res4 res3 res2 res1 res0 scbsy scsr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 ? bit 7:1 ? res6:0 - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 0 ? scbsy - symbol counter busy this bit is set if a write operation to the symbol counter register is pending. this bit is set after writing the counter low byte (sccntll) un til the symbol counter is updated with the new value. this update process can take up to 16 s and during this time no read or write access to the 32 bit counter register should occure. 10.11.28 scirqs ? symbol counter interrupt status r egister bit 7 6 5 4 3 2 1 0 na ($e0) res2 res1 res0 irqsbo irqsof irqscp3 irqscp2 irqscp1 scirqs read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the interrupt status register indicates pending int errupt requests. if the corresponding interrupt mask bit is set, an interrupt service rou tine is called and the status bit is cleared automatically. it is also possible to clear the status bit by writing "1" to the selected bit. ? bit 7:5 ? res2:0 - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 4 ? irqsbo - backoff slot counter irq this interrupt is generated every 320 s, that mean s every 20 symbols. ? bit 3 ? irqsof - symbol counter overflow irq this interrupt is generated when the 32 bit counter turns from 0xfffffff to 0x00000000. ? bit 2 ? irqscp3 - compare unit 3 compare match irq 147 8266c-mcu wireless-08/11 ATMEGA128RFA1 this interrupt indicates a compare match on compare unit 3. ? bit 1 ? irqscp2 - compare unit 2 compare match irq this interrupt indicates a compare match on compare unit 2. ? bit 0 ? irqscp1 - compare unit 1 compare match irq this interrupt indicates a compare match on compare unit 1. 10.11.29 scirqm ? symbol counter interrupt mask reg ister bit 7 6 5 4 3 2 1 0 na ($df) res2 res1 res0 irqmbo irqmof irqmcp3 irqmcp2 irqmcp1 scirqm read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the interrupt mask register is used to enable corre sponding interrupts. after reset all interrupts are disabled. disabled interrupts are st ill captured in the interrupt status register scirqs, but no interrupt is requested. bef ore enabling an interrupt, the corresponding interrupt status bit should be cleare d by writing a 1. if the status bit is set and the irq gets enabled, the irq handler is called immediatly. ? bit 7:5 ? res2:0 - reserved bit this bit is reserved for future use. the result of a read access is undefined. the register bit must always be written with the reset value. ? bit 4 ? irqmbo - backoff slot counter irq enable this bit enables the scnt_backoff interrupt. ? bit 3 ? irqmof - symbol counter overflow irq enable this bit enables the scnt_ovfl interrupt. ? bit 2 ? irqmcp3 - symbol counter compare match 3 ir q enable this bit enables the scnt_cmp3 interrupt. ? bit 1 ? irqmcp2 - symbol counter compare match 2 ir q enable this bit enables the scnt_cmp2 interrupt. ? bit 0 ? irqmcp1 - symbol counter compare match 1 ir q enable this bit enables the scnt_cmp1 interrupt. 148 8266c-mcu wireless-08/11 ATMEGA128RFA1 11 system clock and clock options this section describes the clock options for the av r microcontroller. 11.1 overview figure 11-1 below presents the principal clock systems in the avr an d their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in chapter "power management and sleep modes" on page 157 . the clock systems are detailed below. figure 11-1. clock distribution asynchronous timer general i/o modules adc cpu core ram flash and eeprom radio transceiver avr clock control unit system clock prescaler reset logic watchdog timer timer/counter oscillator (32.768khz) transceiver crystal oscillator (16mhz) calibrated rc oscillator (16mhz) w atchdog oscillator (128khz) tosc1 tosc2 xtal1 xtal2 clock multiplexer 1/8 clock prescaler clock multiplexer clock multiplexer clk cpu clk adc clk i/o clk asy clk ramregf clk calib clk flash source clock clk w dt external clock clki 1:2 prescaler symbol counter amr clk rcosc clk trx 11.2 clock systems and their distribution 11.2.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system conc erned with operation of the avr core. examples of such modules are the general purp ose register file, the status register and the data memory holding the stack poin ter. halting the cpu clock inhibits the core from performing general operations and cal culations. 149 8266c-mcu wireless-08/11 ATMEGA128RFA1 11.2.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o mo dules, like timer/counters, spi, and usart. the i/o clock is also used by the external i nterrupt module, but note that some external interrupts are detected by asynchronous lo gic, allowing such interrupts to be detected even if the i/o clock is halted. also note that start condition detection in the 2- wire serial interface (twi) module is carried out a synchronously when clk i/o is halted. similar the twi address recognition in all sleep mo des also occurs asynchronously. 11.2.3 flash clock ? clk flash the flash clock controls operation of the flash int erface. the flash clock is usually active simultaneously with the cpu clock. 11.2.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronou s timer/counter to be clocked directly from an external clock or an external 32 k hz clock crystal. the dedicated clock domain allows using this timer/counter as a real-ti me counter even if the device is in sleep mode. 11.2.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by di gital circuitry. this gives more accurate adc conversion results. 11.3 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. table 11-1. device clocking options select (1) device clocking option cksel3:0 transceiver clock 1111 ? 0110 reserved 0101 - 0100 internal 128 khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 notes: 1. for all fuses ?1? means unprogrammed whil e ?0? means programmed. 11.3.1 default clock source the device is shipped with internal rc oscillator a t 16.0 mhz, the 1:2 prescaler enabled and with the fuse ckdiv8 programmed, resulting in 1 .0 mhz system clock. the startup time is set to maximum time. (cksel = "0010", sut = "10", ckdiv8 = "0"). the default setting ensures that all users can make their desir ed clock source setting using any available programming interface. 11.3.2 clock start-up sequence any clock source needs a minimum number of oscillat ing cycles before it can be considered stable. 150 8266c-mcu wireless-08/11 ATMEGA128RFA1 to ensure sufficient startup time, the device issue s an internal reset with a time-out delay (t tout ) after the device reset is released by all other r eset sources. section "power-on reset" on page 179 describes the start conditions for the internal re set. the delay (t tout ) is timed from the watchdog oscillator and the num ber of cycles in the delay is set by the sutx and ckselx fuse bits. the selectable delays are shown in table 11-2 below . the frequency of the watchdog oscillator is volta ge dependent as shown in section "typical characteristics" on page 519 . table 11-2. number of watchdog oscillator cycles typ time-out number of cycles 0 ms 0 4.0 ms 512 64 ms 8k (8,192) main purpose of the delay is to keep the avr in res et until it is supplied with a stable v devdd . the delay will not monitor the actual voltage and it will be required to select a delay longer than the devdd rise time. if this is n ot possible, an internal or external brown-out detection (bod) circuit should be used. a bod circuit will ensure sufficient v devdd before it releases the reset, and the time-out del ay can be disabled. disabling the time-out delay without utilizing a brown-out de tection circuit is not recommended. the oscillator is required to oscillate for a minim um number of cycles before the clock is considered stable. an internal ripple counter monit ors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. the reset is then released and the device will start to execute. the recommended oscillator start-up time is dependent on the clock type, and varies from 6 c ycles for an externally applied clock to 32k cycles for a low frequency crystal. the start-up sequence for the clock includes both t he time-out delay and the start-up time when the device starts up from reset. when sta rting up from power-save or power- down mode, devdd is assumed to be at a sufficient l evel and only the start-up time is included. 11.4 calibrated internal rc oscillator by default, the internal rc oscillator provides an approximate 16 mhz clock. the rc oscillator is voltage and temperature dependent, bu t can be very accurately calibrated by the user. see chapter "clock characteristics" on page 509 and "internal oscillator speed" on page 541 for more details. the device is shipped with the c kdiv8 fuse and the 1:2 system clock prescaler programmed. see sect ion "system clock prescaler" on page 153 for more details. this clock may be selected as the system clock by p rogramming the cksel fuses as shown in table 11-3 on page 151. if selected, it will operate with no ext ernal components. during reset, hardware loads the pre-pr ogrammed calibration value into the osccal register and thereby automatically calib rates the rc oscillator. the accuracy of this calibration is shown as factory ca libration in section "clock characteristics" on page 509 . by changing the osccal register (see "osccal ? oscillator calibration value" on page 154 ) from software, it is possible to get a higher cal ibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in section "clock characteristics" on page 509 . 151 8266c-mcu wireless-08/11 ATMEGA128RFA1 when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre- programmed calibration value, see the section "calibration byte" on page 468 . table 11-3. internal calibrated rc oscillator operating modes (1)(2) frequency range (mhz) cksel3:0 9.6 ... 22.4 0010 notes: 1. the device is shipped with this option se lected. when this oscillator is selected, start-up times ar e determined by the sut fuses as shown in the following table. table 11-4. start-up times for the internal calibrated rc oscil lator clock selection power conditions start-up time from power- down and power-save additional delay from reset sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.0 ms 01 slowly rising power 6 ck 14ck + 64 ms (1) 10 reserved 11 notes: 1. the device is shipped with this option se lected 11.5 128 khz internal oscillator the 128 khz internal oscillator is an ultra-low pow er rc oscillator providing a clock of approximate 128 khz nominal frequency. this clock m ay be selected as the system clock by programming the cksel fuses to ?0011? as s hown in the following table. table 11-5. 128 khz internal oscillator operating modes (1) nominal frequency cksel3:0 128 khz 0011 notes: 1. note that the 128 khz oscillator is a ver y low power clock source, and is not designed for high accuracy when this clock source is selected, start-up times are determined by the sut fuses as shown in the following table. table 11-6. start-up times for the 128 khz internal oscillator power conditions start-up time from power-down and power-save additional delay from reset sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 64 ms 10 reserved 11 11.6 external clock to drive the device from an external clock source, clki should be used as shown in figure 11-2 on page 152. to run the device on an external clock, the cksel fuses must be programmed to ?0000?. 152 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 11-2. external clock drive configuration clki vss external clock when this clock source is selected, start-up times are determined by the sut fuses as shown in table 11-8 below . table 11-7. external clock frequency nominal frequency cksel3:0 0 ? 16 mhz 0000 table 11-8. start-up times for the external clock selection power conditions start-up time from power-down and power-save additional delay from reset sut1:0 bod enabled 6 ck 14 ck 00 fast rising power 6 ck 14 ck + 4.0 ms 01 slowly rising power 6 ck 14 ck + 64 ms 10 reserved 11 when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the m icrocontroller unit (mcu). a variation in frequency of more than 2% from one clock cycle t o the next can lead to unpredictable behavior. if changes of more than 2% are required, ensure that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring s table operation. refer to section "system clock prescaler" on page 153 for details. 11.7 transceiver crystal oscillator the integrated crystal oscillator for the radio tra nsceiver generates a low-jitter 16mhz clock frequency. see section "crystal oscillator (xosc)" on page 81 for details about the operation of this oscillator. the avr core and the radio transceiver operate synchronously on the same clock if this oscillator is selected. if the transceiver crystal oscillator is selected as avr core clock, it remain s enabled even if the radio transceiver is in sleep mode or its power reduction bit prtrx24 is set. table 11-9. transceiver crystal clock operating mode frequency range (mhz) cksel3:0 (1) 16 1111 - 0110 notes: 1. all cksel fuse values have the same signi ficance. 153 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 11-10. start-up times for the transceiver oscillator clock selection power conditions start-up time from power-down and power-save additional delay from reset cksel0 sut1:0 fast rising power 258 ck 14ck + 4.1 ms 0 00 slowly rising power 258 ck 14ck + 65 ms 0 01 bod enabled 1k ck 14ck + 0 ms 0 10 fast rising power 1k ck 14ck + 4.1 ms 0 11 slowly rising power 1k ck 14ck + 65 ms 1 00 bod enabled 16k ck 14ck + 0 ms 1 01 fast rising power 16k ck 14ck + 4.1 ms 1 10 slowly rising power 16k ck 14ck + 65 ms 1 11 11.8 clock output buffer the device can output the system clock on the clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suita ble when the chip clock is used to drive other circuits on the system. the clock al so will be output during reset, and the normal operation of i/o pin will be overridden when the fuse is programmed. any clock source, including the internal rc oscillator, can b e selected when the clock is output on clko. if the system clock prescaler is used, it is the divided system clock that is output. special attention is required to prevent unwanted r adiation from the connected pcb clock trace. proper filtering can help to suppress higher harmonics. 11.9 timer/counter oscillator the device can operate the timer/counter2 from the 32.768 khz crystal oscillator or an external clock source. see section "application circuits" on page 495 for the watch crystal connection. 11.10 system clock prescaler the ATMEGA128RFA1 has a system clock prescaler, and the system clock can be divided by setting the ?clkpr ? clock prescale regi ster?. this feature can be used to decrease the system clock frequency and the power c onsumption when the requirement for processing power is low. this can b e used with all clock source options, and it will affect the clock frequency of the cpu a nd all synchronous peripherals. the clocks clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in clkpr ? clock prescale register on page 155 . the prescaler clock division factor of the internal rc-oscillator is different from all other clock sources, see register description clkpr ? clock prescale register on page 155 flash, eeprom, fuse- and lock-bit programming is no t allowed while using rc- oscillator with clkps=0xf (clk cpu = 16mhz). when switching between prescaler settings, the syst em clock prescaler ensures that no glitches occur in the clock system. it also ensu res that no intermediate frequency is higher than neither the clock frequency correspondi ng to the previous setting nor the clock frequency corresponding to the new setting. the prescaler is implemented as a ripple counter ru nning at the frequency of the undivided clock, which may be faster than the cpu's clock frequency. hence, it is not 154 8266c-mcu wireless-08/11 ATMEGA128RFA1 possible to determine the state of the prescaler - even if it were readable. the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values are written, it take s between t 1 + t 2 and t 1 + 2t 2 before the new clock frequency is active. in this interval 2 active clock edges are produced. here t 1 is the previous clock period and t 2 is the clock period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired value to c lkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler settings to make sure the write procedure is not interrupted. it is not required to change the prescaler setting of an existing software package written for an 8mhz internal rc oscillator. the change of t he prescaler (additional 1:2 divider) is compensated by doubling the rc oscillator freque ncy of the ATMEGA128RFA1. 11.11 register description 11.11.1 osccal ? oscillator calibration value bit 7 6 5 4 3 2 1 0 na ($66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator fr equency. a preprogrammed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency. the application softw are can write this register to change the oscillator frequency. the oscillator can be cal ibrated to frequencies as specified in the section "electrical characteristics". calibrati on outside that range is not guaranteed. note that this oscillator is used to time eeprom an d flash write accesses and these write times will be affected accordingly. the calib ration to very high frequencies can cause eeprom or flash erase/write failures. the cal 7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. th e two frequency ranges are overlapping, in other words a setting of osccal = 0 x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune th e frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. ? bit 7:0 ? cal7:0 - oscillator calibration tuning va lue table 11-11 cal register bits register bits value description 0x00 calibration value for lowest oscillator frequency 0x7f end value of low frequency range calibration cal7:0 0x80 start value of high frequency range calibration 155 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0xff calibration value for highest oscillator frequency 11.11.2 clkpr ? clock prescale register bit 7 6 5 4 3 2 1 0 na ($61) clkpce res2 res1 res0 clkps3 clkps2 clkps1 clkps0 clkpr read/write rw r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? clkpce - clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in c lkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles aft er it is written or when clkps bits are written. rewriting the clkpce bit within this t ime-out period does neither extend the time-out period, nor clear the clkpce bit. ? bit 6:4 ? res2:0 - reserved ? bit 3:0 ? clkps3:0 - clock prescaler select bits these bits define the division factor between the s elected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides th e master clock input to the mcu, the speed of all synchronous peripherals is reduced whe n a division factor is used. the division factors are given in the following table. note that the factor is different when using the internal 16mhz rc oscillator as the clock source. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is not programmed, the clkps bits will be reset to 0000. if ckdiv8 is prog rammed, clkps bits are reset to 0011 giving a division factor of 8 at start up. thi s feature should be used if the selected clock source has a higher frequency than the maximu m frequency of the device at the present operating conditions. note that any value c an be written to the clkps bits regardless of the ckdiv8 fuse setting. the applicat ion software must ensure that a sufficient division factor is chosen if the selecte d clock source has a higher frequency than the maximum frequency of the device at the pre sent operating conditions. the device is shipped with the ckdiv8 fuse programmed. table 11-12 clkps register bits register bits value description 0x0 division factor 1 / rc-oscillator 2 0x1 division factor 2 / rc-oscillator 4 0x2 division factor 4 / rc-oscillator 8 0x3 division factor 8 / rc-oscillator 16 0x4 division factor 16 / rc-oscillator 32 0x5 division factor 32 / rc-oscillator 64 0x6 division factor 64 / rc-oscillator 128 0x7 division factor 128 / rc-oscillator 256 0x8 division factor 256 / rc-oscillator 512 0x9 reserved clkps3:0 0xa reserved 156 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0xb reserved 0xc reserved 0xd reserved 0xe reserved 0xf division factor 1 only permitted for rc- oscillator. flash and eeprom programming is not allowed. 157 8266c-mcu wireless-08/11 ATMEGA128RFA1 12 power management and sleep modes sleep modes enable the application to shut down unu sed modules in the mcu, thereby saving power. the avr microcontroller and the rf tr ansceiver provide various sleep modes allowing the user to tailor the power consump tion to the application?s requirements. 12.1 deep-sleep mode when the microcontroller goes into power-down or po wer-save modes while the transceiver is in sleep state the device enters the deep-sleep mode. sending the microcontroller to power-down or power- save is not allowed during the wake-up phase of the transceiver. the trx24_awake i nterrupt shall be used to wait for the transceiver is operational. the dvdd voltage regulator and the associated power chain will be switched off. remaining running logic will then be supplied from the low leakage voltage regulator. even the avdd regulator will switched off. see chap ter "radio transceiver" on page 162 how to disable the radio transceiver. the sram blocks use the data retention mode to pres erve its content while saving leakage power. the low leakage voltage regulator ha s only limited driving capabilities, see section "supply voltage and leakage control" on page 162 for details. therefore the remaining running logic must be clock ed with low frequencies only. the deep-sleep mode can be finished by a wake-up so urce shown by the table 12-1 on page 158. then dvdd voltage regulator and the asso ciated power chain will be switched on. if the power-chain is completely enabl ed the standard avr wake-up procedure continues (for details see chapter "power-chain" on page 162). note that the wake-up time from deep-sleep mode is significantly longer than the wake- up time from the power-down or power-save mode beca use the entire power-chain will be restarted. additionally note that if the adc is enabled and/or running a conversion, while entering deep-sleep mode, the adc supply voltage is switched off. therefore the adc must be disabled before entering deep-sleep mode to avoid a n undefined adc operation. if timer/counter 2 is not operated asynchronously ( i.e., as2 in assr is 0), the timer is kept running in all sleep modes (see chapter power-save mode on page 159). this implies the main oscillator (as selected by the fus e configuration) is kept running. the power chain remains enabled and the device does not enter the deep_sleep mode. 12.2 avr microcontroller sleep modes in chapter "system clock and clock options" on page 148 the different clock systems in the ATMEGA128RFA1, and their distribution were p resented. figure 11-1 on page 148 is helpful in selecting an appropriate sleep mode. the following table shows the different sleep modes and their wake-up sources. 158 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 12-1. active clock domains and wake-up sources in the dif ferent sleep modes active clock domains oscillators wake-up sources sleep mode clkcpu clkflash clkio clkadc clkasy main clock- source enabled timer oscillator enabled int7:0 and pin change twi address match timer/counter2 spm/eeprom ready adc wdt interrupt other i/o symbol counter transceiver idle x x x x x (2) x x x x x x x x (4) x (4) adcnrm x x x x (2) x (3) x x (2) x x x x (4) x (4) power-down x (3) x x x (4) x (4) power-save x x (2) x (3) x x x x (4) x (4) standby (1) x x (3) x x x (4) x (4) extended standby x (2) x x (2) x (3) x x x x (4) x (4) notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mod e. 3. for int7:4, only level interrupt. 4. the symbol counter and/or the transceiver can wa keup the avr if the transceiver oscillator is enabled (transceiver not in sleep). to enter any of the sleep modes, the se bit in in t he smcr register (see "smcr ? sleep mode control register" on page 168 ) must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode will be activated by the sl eep instruction. see chapter "register description" on page 168 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the i nstruction following sleep. the contents of the register file and sram are unaltere d when the device wakes up from sleep. note that sram data retention must be enable d in some sleep modes to preserve the memory contents (see section "sram with data retention" on page 164). if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 12.2.1 idle mode when the sm2:0 bits are written to 000 in the smcr register, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, 2-wire serial interface, ti mer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart tra nsmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the a nalog comparator control and status register ? acsr. this will reduce power cons umption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. 159 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.2.2 adc noise reduction mode when the sm2:0 bits are written to 001, the sleep i nstruction makes the mcu enter adc noise reduction mode (adcnrm), stopping the cpu but allowing the adc, the external interrupts, 2-wire serial interface addres s match, timer/counter2 and the watchdog to continue operating (if enabled). this s leep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, en abling higher resolution measurements. if the adc is enabled, a conversion s tarts automatically when this mode is entered. apart form the adc conversion comp lete interrupt, only an external reset, a watchdog system reset, a watchdog interrup t, a brown-out reset, a 2-wire serial interface interrupt, a timer/counter2 interr upt, an spm/eeprom ready interrupt, an external level interrupt on int7:4 or a pin chan ge interrupt can wakeup the mcu from adc noise reduction mode. 12.2.3 power-down mode when the sm2:0 bits are written to 010, the sleep i nstruction makes the mcu enter power-down mode. in this mode, the 16 mhz crystal o scillator is stopped (if selected by cksel fuses), while the external interrupts, the 2- wire serial interface, and the watchdog continue operating (if enabled). only an e xternal reset, a watchdog reset, a brown-out reset, 2-wire serial interface address match, an external level interrupt on int7:4, an external interrupt on int3:0, a pin chan ge interrupt, or a symbol counter interrupt can wake up the mcu. this sleep mode basi cally halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used fo r wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to section "external interrupts" on page 219 for details. when waking up from power-down mode, there is a del ay from the wake-up condition occurs until the wake-up becomes effective. this al lows the clock to restart and become stable after have been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as des cribed in chapter "system clock and clock options" on page 148 . 12.2.4 power-save mode when the sm2:0 bits are written to 011, the sleep i nstruction makes the mcu enter power-save mode. this mode is identical to power-do wn, with one exception: if timer/counter2 is enabled, it will keep running during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/count er2 is not running, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronousl y and asynchronously in power- save mode. if the timer/counter2 is not using the a synchronous clock, the timer/counter oscillator is stopped during sleep. i f the timer/counter2 is not using the synchronous clock, the clock source is stopped duri ng sleep. note that even if the synchronous clock is running in power-save, this cl ock is only available for the timer/counter2. timer/counter2 operation is describ ed in detail in section "8-bit timer/counter2 with pwm and asynchronous operation" on page 310 . 160 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.2.5 standby mode when the sm2:0 bits are 110 and the crystal oscilla tor of the radio transceiver is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in six clock cycl es. 12.2.6 extended standby mode when the sm2:0 bits are 111 and the crystal oscilla tor of the radio transceiver is selected, the sleep instruction makes the mcu enter extended standby mode. this mode is identical to power-save mode with the excep tion that the oscillator is kept running. from extended standby mode, the device wak es up in six clock cycles. 12.3 power reduction register the power reduction register (prr), see "prr0 ? power reduction register0" on page 169 , "prr1 ? power reduction register 1" on page 169 and "prr2 ? power reduction register 2" on page 170 , provide a method to stop the clock to individual peripherals to reduce power consumption. the curren t state of the peripheral is frozen and the i/o registers can not be read or written. r esources used by the peripheral when stopping the clock will remain occupied. hence the peripheral unit should in most cases be disabled before stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state a s before the shutdown. exceptions are the sram blocks and the radio transceiver. the sram is shut down by a drt switch and the radio transceiver is in reset state if its respective power reduction bit is set. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consumption. see chapter "typical characteristics" on page 519 for examples. in all other sleep modes, the clock is al ready stopped. 12.4 minimizing power consumption there are several issues to consider when trying mi nimizing the power consumption in an avr controlled system. in general, sleep modes s hould be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 12.4.1 analog to digital converter if enabled, the adc will be enabled in all sleep mo des. to save power, the adc should be disabled before entering any sleep mode. refer t o chapter "adc ? analog to digital converter" on page 411 for details on adc operation. 12.4.2 analog comparator when entering idle mode, the analog comparator shou ld be disabled if not used. when entering adc noise reduction mode the analog compar ator should also be disabled. in other sleep modes, the analog comparator is auto matically disabled. however, if the analog comparator is set up to use the internal vol tage reference as input, the analog comparator should be disabled in all sleep modes. o therwise, the internal voltage reference will be enabled, independent of sleep mod e. refer to "ac ? analog comparator" on page 408 for details on how to configure the analog compara tor. 161 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.4.3 brown-out detector if the brown-out detector is enabled by the bodleve l fuses, it will be disabled in deep-sleep mode. refer to "brown-out detection" on page 180 for details on how to configure the brown-out detector. it is recommended to enable the brown-out detector. 12.4.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the adc. if the se modules are disabled as described in the sections above, the internal volta ge reference will be disabled and not consume power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to "internal voltage reference" on page 181 for details on the start-up time. 12.4.5 watchdog timer if the watchdog timer is not needed in the applicat ion, the module should be turned off. if the watchdog timer is enabled, it will be enable d in all sleep modes, and hence, always consume power. in the deeper sleep modes, th is will contribute significantly to the total current consumption. refer to "watchdog timer" on page 182 for details on how to configure the watchdog timer. 12.4.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins d rive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensure s that no power is consumed by the input logic when not needed. in some cases, the inp ut logic is needed for detecting wake-up conditions, and it will then be enabled. re fer to the section "i/o-ports" on page 188 for details on which pins are enabled. if the inpu t buffer is enabled and the input signal is left floating or have an analog signal le vel close to devdd/2, the input buffer will use excessive power. for analog input pins, the digital input buffer sho uld be disabled at all times. an analog signal level close to devdd/2 on an input pin can c ause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers didr1 and didr0. refer to "didr1 ? digital input disable register 1" on page 410 and "didr0 ? digital input disable register 0" on page 434 for details. 12.4.7 on-chip debug system if the on-chip debug system is enabled by the ocden fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. in the deeper sleep modes, this will contribute significan tly to the total current consumption. there are three alternative ways to disable the ocd system: ? disable the ocden fuse. ? disable the jtagen fuse. ? write one to the jtd bit in mcucr. 12.4.8 symbol counter the symbol counter acts as a separate counter, whic h uses either the 16mhz clock from xtal1/xtal2 crystal pins or the clock from pg3 /pg4 low frequency crystal pins. if the symbol counter module is not used, it should be disabled, see section "mac symbol counter" on page 134 . 162 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.4.9 radio transceiver the radio transceiver module is automatically start ing its state machine after power on. while the cpu is in any sleep mode, the radio trans ceiver remains active. this enables the radio transceiver to wakeup the mcu if a pendin g action is over (frame received or transmission completed). the radio transceiver will be inactive during sleep, if either the its power reduction bit prtrx24 in register prr1 is set or it is send into sleep mode, see "prr1 ? power reduction register 1" on page 169 for details. the radio transceiver is derived from a stand alone solution that was partly controlled by external pins. now the radio transceiver is full y controlled by individual register bits. the radio transceiver has a separate reset signal. a radio transceiver reset is initiated by setting bit trxrst in register trxpr. this bit i s self-resetting. the radio transceiver signal slptr can be controlle d by the bit slptr in register trxpr and is used to set the radio transceiver into sleep mode (assuming trx_state is trx_off). this bit has a multiple func tion, see section "low-power 2.4 ghz transceiver" on page 30 for a detailed description of the radio transceive r. 12.5 supply voltage and leakage control for battery applications using deep_sleep periods, the leakage current defines the system life time. due to the typical strong tempera ture dependency of the leakage current, major contributors to the leakage budget a re turned off: ? analog and digital voltage regulator, ? non-volatile memory (nvm), ? sram, ? digital signal processor of the radio transceiver including aes engine. if the cpu uses one of the sleep modes ?power-down? or ?power-save?, the above mentioned blocks will be switched off by power swit ches. when the cpu wakes up, the blocks are switched on again. there are some additi onal exceptions (internal voltage regulator, sram, radio transceiver), see section "power-chain" below . the supply voltage control is mainly hidden to the application, it is not necessary to configure the supply voltage control. nevertheless some configurations can be done in order to get the maximum effect and the lowest slee p current, for details see section "sram with data retention" on page 164. 12.5.1 power-chain the following figure shows the major dependencies o f the power-chain and how the power switches are situated inside the chain. 163 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 12-1. power-chain connections startup and wakeup from deep_sleep after power-on reset (por) or wakeup from deep_slee p the power switches of the blocks will be enabled one after another (power-cha ined) to decrease current peaks. the blocks will be enabled in the following order: 1. bandgap reference and voltage regulator, 2. digital voltage regulator (dvreg) and low leakag e voltage regulator (llvreg), 3. first sram block (lower 4k bytes), 4. last sram block (upper 4k bytes), 5. radio transceiver including aes engine, 6. non-volatile memory. if the power-chain is completely enabled the standa rd avr wake-up procedure continues. figure 12-2 shows the chained startup procedure aft er power up. the figure 12-3 shows the startup from deep_sleep. a module is only switched on if it is not deselected by power reduction register (prr1 or prr 2). this is possible for sram blocks and radio transceiver power switch. at the e nd of the startup, the pin rston is enabled. depending of the currently enabled memory blocks (n sram ), the startup procedure takes different time. t startup_total = t bg + t dvreg + n sram t drt_on + 3 t pwrsw_on + t osc_startup the sram is organized in 4kbyte blocks, the nvm in 128kbyte blocks. deselected sram blocks (by prr2 register) reduce the wakeup ti me from deep_sleep. for further timing information see "power management electrical characteristics" on pa ge 510 . figure 12-2. timing visualization of power up s t a r t u p b a n d g a p s t a r t u p d v r e g d r t s w i t c h s r a m # 0 p o r d r t s w it c h s r a m # 1 d r t s w i t c h s r a m # 2 d r t s w it c h s r a m # 3 p o w e r s w i t c h r a d i o t r a n s . p o w e r s w i t c h n v m o s c il l a t o r s t a r t u p t p o r t b g t d v r e g t d r t _ o n t d r t _ o n t d r t _ o n t d r t _ o n t p w r s w _ o n t p w r s w _ o n t o s c _ s t a r t u p r s t o n t s t a r t u p 164 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 12-3. timing visualization of wakeup from deep_sleep s t a r t u p b a n d g a p s t a r t u p d v r e g d r t s w it c h s r a m # 0 s l e e p d r t s w i t c h s r a m # 1 d r t s w i t c h s r a m # 2 d r t s w i t c h s r a m # 3 p o w e r s w it c h r a d i o t r a n s . p o w e r s w i t c h n v m o s c il l a t o r s t a r t u p t b g t d v r e g t d r t _ o n t d r t _ o n t d r t _ o n t d r t _ o n t p w r s w _ o n t p w r s w _ o n t o s c _ s t a r t u p t s t a r t u p sleep six sleep modes are defined for the cpu. disabling the power-chain and thus switching off of the above mentioned blocks makes only sense for the modes ?power-down? and ?power-save?. also an enabled radio transceiver pre vents the power-chain from being disabled. in order to disable the power-chain, one of the fol lowing conditions must fit: ? the radio transceiver has to be disabled (power re duction register prr1 bit prtrx24). ? the radio transceiver is sent into sleep mode (reg ister trxpr bit slptr). the sram blocks may be configured separately to dec rease their leakage current (see section "sram with data retention" below ). the following table shows the different implemented sleep modes and the behavior of the power-chain depending on the current state of t he radio transceiver. table 12-2. power states of microcontroller and rad io transceiver avr state radio transceiver state powerchain on on on on off (sleep or power reduction) on off (1?6) on on off (1,4?6) off (sleep or power reduction) on off (2,3) deep sleep off (sleep or power reduction) off (7) notes: 1. idle 2. power down 3. power save 4. adc noise reduction mode 5. standby 6. extended standby 7. 12.5.2 sram with data retention it is necessary to prevent any data loss of the sra m when setting the cpu in one of the deep_sleep modes. for that purpose the sram blo cks will not be completely switched off if the power-chain is disabled. the su pply voltage for any individual sram block is decreased to reduce its leakage current bu t guaranteeing its data retention. the sram memory is divided into 4kbyte blocks. each block can be fully switched off by setting the correspondent bit (prram0 ... prram3 ) in register prr2 (see "prr2 ? power reduction register 2" on page 170 ). this enables the application software to switch off unused sram memory to save power and to reduce leakage currents. 165 8266c-mcu wireless-08/11 ATMEGA128RFA1 every sram block can be enabled again by resetting the respective bit (prram0 ... prram3) of register prr2. for each sram block n the bit drtswok of the corresponding register drtram n shows the state of the drt switch (logic high mean s sram block can be accessed). if the power-chain is switched off during deep-slee p modes, the content of the sram blocks must be sustained. to provide data retention and lowest leakage current, a data retention block controls the sram behavior during d eep-sleep. since the leakage current is dramatically depending from the voltage of the sram, the supply voltage can be decreased by enabling the data retention mode dr t. every sram block n is controlled by its assigned register drtram n . the bit endrt enables the data retention mode during deep-sleep. if this bit is zero, the respective sram block is completely switched off. table 12-3. sram behavior while in deep-sleep mode endrt power-chain sram supply voltage 1 on 1.8v (dvdd) 0 on 1.8v (dvdd) 1 off reduced 0 off disconnected the lower 4-bit of the register drtram n are reserved and should not be changed. the reset value of the drt voltage settings are preprog rammed during the manufacturing process and need not to be changed. 12.5.3 voltage regulators (avreg, dvreg) the main features of the voltage regulator blocks a re: ? bandgap stabilized 1.8v supply for analog and digi tal domain; ? low dropout (ldo) voltage regulator; ? configurable to use an external voltage regulator; the internal voltage regulators supply a stabilized voltage to the ATMEGA128RFA1. the avreg provides the regulated 1.8v supply voltage fo r the analog section and the dvreg supplies the 1.8v supply voltage for the digi tal section. the dvreg is enabled during startup and is switched off if the power-cha in is disabled. the avreg is enabled only on request by either the a/d converter or the radio transceiver. a simplified schematic of the internal voltage regu lator is shown in figure 12-4 below . figure 12-4. simplified schematic of avreg/dvreg b andgap voltage reference 1 .25 v a v d d , d v d d (d )e v d d 166 8266c-mcu wireless-08/11 ATMEGA128RFA1 the voltage regulators require bypass capacitors fo r stable operation. the value of the bypass capacitors determines their settling time. t he bypass capacitors shall be placed as close as possible to the pins and shall be conne cted to ground with the shortest possible traces. the voltage regulators can be configured with the r egister vreg_ctrl. it is recommended to use the internal regulators but it i s also possible to supply the low voltage domains by an external voltage supply. for this configuration the internal analog voltage regulator needs to be switched off b y setting the register bit avreg_ext = 1 (see "vreg_ctrl ? voltage regulator control and status r egister" on page 116 ). the internal digital voltage regulator may not b e switched off, an external voltage has to overdrive the internal voltage. a re gulated external supply voltage of 1.8v must then be connected to the pins 13, 14 (dvd d) and pin 29 (avdd). when turning on the external supply ensure a sufficientl y long stabilization time before interacting with the ATMEGA128RFA1. the status bits avdd_ok = 1 and dvdd_ok = 1 of regi ster vreg_ctrl indicate an enabled and stable internal supply voltage. reading value 0 indicates that the internal supply voltage is disabled or not yet settled to th e final value. in case the the ATMEGA128RFA1 is not supplied with a sufficient (d)evdd and the digital voltage regulator output voltage is too low , a power on reset (por) is initiated. this is implemented with revision f, the register v ersion_num must be equal or greater than rev_f (see rx_syn ? transceiver receiver sensitivity control r egister on page 120 ) 12.5.4 low leakage voltage regulator (llvreg) the main digital voltage regulator (dvreg) will be switched off during the deep_sleep modes ?power-down? and ?power-save?. the low leakage voltage regulator will then keep the digital supply voltage to provide data retention. no application software control is required. during the active power states, when the main volta ge regulator supplies the chip, the low leakage voltage regulator is digitally calibrat ed. its output voltage is adjusted to match the output voltage of the main regulator. thi s fixed calibration result is stored and used when the chip enters a power-down state where the main regulator is switched off. because the calibration setting is fixed, temperatu re and load current variations during the following deep_sleep period are not regulated o ut. thus the output voltage may drift away from the target value. however the desig n guarantees that for allowed operating conditions the output voltage will stay w ithin valid limits. after every wake-up a new calibration cycle is initiated. the output driving capability of the low leakage vo ltage regulator is limited. its main purpose is to provide the leakage current of the co nnected analog and digital blocks. at least one full calibration cycle of the low leak age voltage regulator has to be completed before the power-chain can be disabled. t herefore if the cpu uses one of the deep_sleep modes ?power down? or ?power save?, the power-chain is not disabled before the low leakage voltage regulator c ompleted this first calibration cycle. by default the llvreg automatically starts the cali bration after finishing the power-on reset and the wake-up/start-up procedures (see sect ion "low leakage voltage regulator control" on page 167 for a detailed description of the low lea kage voltage regulator). 167 8266c-mcu wireless-08/11 ATMEGA128RFA1 notes: 1. the llvreg calibration will be inaccurate at a devdd supply voltage of 1.8v or lower. therefore when operating the device at 1.8v the llvreg calibration should be disabled and the register val ues of lldrl and lldrh should be set to 0x06 and 0x0f, respectively. 12.5.5 low leakage voltage regulator control the three register llcr, lldrl and lldrh allow the software to monitor the calibration process and to modify or correct the ca libration results. the automatic calibration is the normal operation mode. it is an internal process that does not require any software interaction. nevertheless the calibrat ion is transparent for the user through llcr, lldrl and lldrh (control and data register re spectively). the register access requires a minimum system clock of at least the output frequency of the 128 khz rc oscillator. the register access w ill not work if the system clock is slower. see chapter system clock and clock options on page 148 for details on how to set the system clock frequency. before the device can enter the sleep mode ?power d own? or ?power save? the first calibration cycle of the low leakage voltage regula tor must be completed to get valid data in lldrl and lldrh. the cycle time t llvreg_calib is not fixed. it depends on the temperature, manufacturing process and the frequenc y of the 128 khz rc oscillator (independent of the watchdog setting). systems that require very short power-up times may temporarily disable the calibration process by setting bit llencal to 0. after disablin g the calibration the register values read from llcr, lldrl and lldrh will be stable afte r at most five 64 khz clock cycles (clock output of the 128 khz rc oscillator d ivided by 2). the output voltage of the low leakage voltage regul ator in sleep mode will be the most accurate if constantly calibrated to compensat e for any environmental changes (e.g. temperature). however these changes may be sl ow enough to skip the calibration during some power-up cycles (e.g. calibrate only ev ery 10 th power-up time and use the old calibration results during all other times). after the completion of the power-up process the ca libration will start automatically if bit llencal in the control register llcr is 1 (default) . the completion of a calibration cycle is indicated by the bit lldone in that same r egister. after the first cycle the calibration will continue to run until either the d evice goes into a sleep mode (?power down? or ?power save?) or by setting the llencal bi t to 0. the output voltage of the low leakage voltage regulator is then defined by th e values in the data register lldrl and lldrh and by the bits lltco and llshort o f the control register. write access to the three register is granted when the bit llencal is set to 0. the application software can then modify the calibratio n results. higher values in the data register generate lower output voltages in the slee p modes. in general it is not recommended nor required to alter the automatically generated calibration result. the write access to the three register must follow a certain scheme to be successful. the registers are implemented in the i/o clock doma in while the logic of the low leakage voltage regulator runs with 64 khz (clock o utput of the 128 khz rc oscillator divided by 2). it takes at least two 64 khz clock c ycles before the data written to the register take effect in the regulator circuit. the write access from the software must be aware of this process. furthermore the value of lld rh must be written first followed by lldrl. otherwise the lldrh write access will be ign ored. the following assembler code fragment shows a working example. note the pol ling of bit 3 llcal of the llcr register to verify the completion of the synchroniz ation process. 168 8266c-mcu wireless-08/11 ATMEGA128RFA1 assembly code example ? clr r20 iost lldrh,r18 ; write lldrh first iost lldrl,r19 ; write lldrl second iost llcr,r20 ; bit 0 cleared = disable automatic calibration ; poll llcal bit of llcr to check if automatic calibration is ; turned of wait_calib: iold r20,llcr sbrc r20,3 rjmp wait_calib ; not executed if bit 3 of llcr is cleared ? 12.6 register description 12.6.1 smcr ? sleep mode control register bit 7 6 5 4 3 2 1 0 $33 ($53) res3 res2 res1 res0 sm2 sm1 sm0 se smcr read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 the sleep mode control register contains control bi ts for power management. ? bit 7:4 ? res3:0 - reserved ? bit 3:1 ? sm2:0 - sleep mode select bit 2 these bits select between the five available sleep modes. standby modes are only recommended for use with external crystals or reson ators. table 12-4 sm register bits register bits value description 0x00 idle 0x01 adc noise reduction (if available) 0x02 power down 0x03 power save 0x04 reserved 0x05 reserved 0x06 standby sm2:0 0x07 extended standby ? bit 0 ? se - sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmers purpose, it is recommended to wr ite the sleep enable (se) bit to one just before the execution of the sleep instruct ion and to clear it immediately after waking up. 169 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.6.2 prr0 ? power reduction register0 bit 7 6 5 4 3 2 1 0 na ($64) prtwi prtim2 prtim0 prpga prtim1 prspi prusart0 pradc prr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ? bit 7 ? prtwi - power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 ? prtim2 - power reduction timer/counter2 writing a logic one to this bit shuts down the time r/counter2 module. when the timer/counter2 is enabled, operation will continue like before the shutdown. ? bit 5 ? prtim0 - power reduction timer/counter0 writing a logic one to this bit shuts down the time r/counter0 module. when the timer/counter0 is enabled, operation will continue like before the shutdown. ? bit 4 ? prpga - power reduction pga writing a logic one to this bit reduced the power c onsumption of the programmable gain amplifier. the block is not turned off. only the cu rrent levels in the amplifiers are reduced. reducing the pga current levels is only re commended for slow adc clock frequencies. a new adc conversion using the pga sho uld be delayed by a default start-up time after changing (setting or resetting) this bit. ? bit 3 ? prtim1 - power reduction timer/counter1 writing a logic one to this bit shuts down the time r/counter1 module. when the timer/counter1 is enabled, operation will continue like before the shutdown. ? bit 2 ? prspi - power reduction serial peripheral i nterface writing a logic one to this bit shuts down the seri al peripheral interface by stopping the clock to the module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 ? prusart0 - power reduction usart writing a logic one to this bit shuts down the usar t0 by stopping the clock to the module. when waking up the usart0 again, the usart0 should be reinitialized to ensure proper operation. ? bit 0 ? pradc - power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled (reset aden bit in register adcsra) before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. 12.6.3 prr1 ? power reduction register 1 bit 7 6 5 4 3 2 1 0 na ($65) res prtrx24 prtim5 prtim4 prtim3 prusart1 prr1 read/write r rw rw rw rw rw initial value 0 0 0 0 0 0 170 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 6 ? prtrx24 - power reduction transceiver writing a logic one to this bit shuts down the tran sceiver (disconnect from the power supply). in power-down and power-save modes the pow er-chain will be disabled when this bit is one. writing a logic zero to this bit w ill re-enable the transceiver. ? bit 5 ? prtim5 - power reduction timer/counter5 writing a logic one to this bit shuts down the time r/counter5 module. when the timer/counter5 is enabled, operation will continue like before the shutdown. ? bit 4 ? prtim4 - power reduction timer/counter4 writing a logic one to this bit shuts down the time r/counter4 module. when the timer/counter4 is enabled, operation will continue like before the shutdown. ? bit 3 ? prtim3 - power reduction timer/counter3 writing a logic one to this bit shuts down the time r/counter3 module. when the timer/counter3 is enabled, operation will continue like before the shutdown. ? bit 0 ? prusart1 - power reduction usart1 writing a logic one to this bit shuts down the usar t1 by stopping the clock to the module. when waking up the usart1 again, the usart1 should be reinitialized to ensure proper operation. 12.6.4 prr2 ? power reduction register 2 bit 7 6 5 4 3 2 1 0 na ($63) res3 res2 res1 res0 prram3 prram2 prram1 prram0 prr2 read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 the power reduction register prr2 allows to individ ually disable all four sram blocks. setting any prram3:0 bit to one will comple tely switch off (disconnect from the power supply) the corresponding sram block. this en ables the application to disable unused sram memory to save power. every sram block can be re-enabled by reseting the appropriate prram3:0 bit. ? bit 7:4 ? res3:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? prram3 - power reduction sram 3 setting this bit to one will disable the sram block 3. setting this bit to zero will enable the sram block 3. ? bit 2 ? prram2 - power reduction sram 2 setting this bit to one will disable the sram block 2. setting this bit to zero will enable the sram block 2. ? bit 1 ? prram1 - power reduction sram 1 setting this bit to one will disable the sram block 1. setting this bit to zero will enable the sram block 1. 171 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 0 ? prram0 - power reduction sram 0 setting this bit to one will disable the sram block 0. setting this bit to zero will enable the sram block 0. 12.6.5 trxpr ? transceiver pin register bit 7 6 5 4 3 2 1 0 na ($139) res3 res2 res1 res0 resx3 resx2 slptr trxrst trxpr read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 the register trxpr allows to control basic actions of the radio transceiver like reset or state transitions. the register bit functionality i s inherited from the external pins of the stand-alone radio transceiver. ? bit 7:4 ? res3:0 - reserved ? bit 3:2 ? resx3:2 - reserved ? bit 1 ? slptr - multi-purpose transceiver control b it the bit slptr is a multi-functional bit to control transceiver state transitions. dependent on the radio transceiver state, a rising edge of bit slptr causes the following state transitions: trx_off => sleep (leve l sensitive), pll_on => busy_tx. whereas the falling edge of bit slptr caus es the following state transition: sleep => trx_off (level sensitive). when the radio transceiver is in trx_off state the microcontroller forces the transceiver to sleep by setting slptr = h. the transceiver awakes when the microcontroller release s the bit slptr. in states pll_on and tx_aret_on, bit slptr is used as trigger input to initiate a tx transaction. here slptr is sensitive on rising edge only. after initiating a state change by a rising edge at bit slptr in radio transceiver states trx_off, rx_on or rx_aack_on, the radio transceiver remains in the ne w state as long as the pin is logical high and returns to the preceding state wit h the falling edge. ? bit 0 ? trxrst - force transceiver reset the reset state is used to set back the state machi ne and to reset all registers of the transceiver to their default values. a reset forces the radio transceiver into the trx_off state and resets all transceiver register t o their default values. a reset is initiated with bit trxrst = h. the bit is cleared a utomatically during transceiver reset the microcontroller has to set the radio transceive r control bit slptr to the default value. 12.6.6 drtram0 ? data retention configuration regis ter of sram 0 bit 7 6 5 4 3 2 1 0 na ($135) res1 res0 drtswok endrt resx3 resx2 resx1 resx0 drtram0 read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the drtram0 register controls the behavior of sram block 0 in the power-states "power-save" and "power-down". to prevent any data loss the sram will not completely disconnected from the power supply. rese rved bits will be overwritten during chip reset by the factory calibration and sh ould not be modified. 172 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:6 ? res1:0 - reserved ? bit 5 ? drtswok - drt switch ok this bit indicates the status of the sram power-swi tch. a logical one indicates that the sram supply voltage is fully available and the memo ry may be accessed normally. ? bit 4 ? endrt - enable sram data retention during "deep-sleep" each sram block will either be switched off or provides data retention of its memory content. this bit must set to one if data retention mode should be used. otherwise the sram is switched off (discon nected from the power supply) and all its data are lost. ? bit 3:0 ? resx3:0 - reserved 12.6.7 drtram1 ? data retention configuration regis ter of sram 1 bit 7 6 5 4 3 2 1 0 na ($134) res1 res0 drtswok endrt resx3 resx2 resx1 resx0 drtram1 read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the drtram1 register controls the behavior of sram block 1 in the power-states "power-save" and "power-down". to prevent any data loss the sram will not completely disconnected from the power supply. rese rved bits will be overwritten during chip reset by the factory calibration and sh ould not be modified. ? bit 7:6 ? res1:0 - reserved ? bit 5 ? drtswok - drt switch ok this bit indicates the status of the sram power-swi tch. a logical one indicates that the sram supply voltage is fully available and the memo ry may be accessed normally. ? bit 4 ? endrt - enable sram data retention during "deep-sleep" each sram block will either be switched off or provides data retention of its memory content. this bit must set to one if data retention mode should be used. otherwise the sram is switched off (discon nected from the power supply) and all its data are lost. ? bit 3:0 ? resx3:0 - reserved 12.6.8 drtram2 ? data retention configuration regis ter of sram 2 bit 7 6 5 4 3 2 1 0 na ($133) resx7 res drtswok endrt resx3 resx2 resx1 resx0 drtram2 read/write rw r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the drtram2 register controls the behavior of sram block 2 in the power-states "power-save" and "power-down". to prevent any data loss the sram will not completely disconnected from the power supply. rese rved bits will be overwritten during chip reset by the factory calibration and sh ould not be modified. ? bit 7 ? resx7 - reserved ? bit 6 ? res - reserved bit 173 8266c-mcu wireless-08/11 ATMEGA128RFA1 this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? drtswok - drt switch ok this bit indicates the status of the sram power-swi tch. a logical one indicates that the sram supply voltage is fully available and the memo ry may be accessed normally. ? bit 4 ? endrt - enable sram data retention during "deep-sleep" each sram block will either be switched off or provides data retention of its memory content. this bit must set to one if data retention mode should be used. otherwise the sram is switched off (discon nected from the power supply) and all its data are lost. ? bit 3:0 ? resx3:0 - reserved 12.6.9 drtram3 ? data retention configuration regis ter of sram 3 bit 7 6 5 4 3 2 1 0 na ($132) res1 res0 drtswok endrt resx3 resx2 resx1 resx0 drtram3 read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the drtram3 register controls the behavior of sram block 3 in the power-states "power-save" and "power-down". to prevent any data loss the sram will not completely disconnected from the power supply. rese rved bits will be overwritten during chip reset by the factory calibration and sh ould not be modified. ? bit 7:6 ? res1:0 - reserved ? bit 5 ? drtswok - drt switch ok this bit indicates the status of the sram power-swi tch. a logical one indicates that the sram supply voltage is fully available and the memo ry may be accessed normally. ? bit 4 ? endrt - enable sram data retention during "deep-sleep" each sram block will either be switched off or provides data retention of its memory content. this bit must set to one if data retention mode should be used. otherwise the sram is switched off (discon nected from the power supply) and all its data are lost. ? bit 3:0 ? resx3:0 - reserved 12.6.10 llcr ? low leakage voltage regulator contro l register bit 7 6 5 4 3 2 1 0 na ($12f) res1 res0 lldone llcomp llcal lltco llshort llencal llcr read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 1 this register allows to monitor and to control the calibration process of the low-leakage voltage regulator. the automatic calibration is the normal operation mode. however, certain circumstances may require to disable this a utomatic process for instance to save power-up time. the results of the automatic ca libration can also be modified when required by the application for instance to get a h igher or lower output voltage. 174 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? lldone - calibration done this bit indicates the last state of the calibratio n algorithm. the data register contents is updated with new calibration data after the bit cha nged to 1. the bit will only be high for one 64khz clock period, because a new calibration l oop is started automatically. ? bit 4 ? llcomp - comparator output this bit indicates the output state of the comparat or of the low-leakage voltage regulator. in this way the calibration progress can be directly monitored for debug purposes. the state of the bit changes at most ever y 64khz clock period. ? bit 3 ? llcal - calibration active this bit indicates that the automatic calibration i s in progress. the analog part of the calibration circuit is powered up if the bit is 1. ? bit 2 ? lltco - temperature coefficient of current source this bit shows the status of the selection of the t emperature coefficient. the state of the bit is updated in the course of the automatic calib ration. a valid value is present after the lldone bit is 1 for the first time. write acces s is only enabled when the automatic calibration is turned off (llencal is 0). this bit should not be changed without further information. ? bit 1 ? llshort - short lower calibration circuit this bit shows the status of the short switch for t he lower calibration circuit. the state of the bit is updated in the course of the automatic c alibration. a valid value is present after the lldone bit is 1 for the first time. if th is bit is set to 1 register lldrl has no function. write access is only possible when the au tomatic calibration is turned off (llencal is 0). this bit should not be changed with out further information. ? bit 0 ? llencal - enable automatic calibration this bit enables the automatic calibration. the aut omatic calibration runs if the state of the bit is 1. write access to the two data register and the bits llshort and lltco is then denied. if the state of llencal is 0 then the calibration algorithm is stopped and the output voltage of the low-leakage voltage regul ator is defined by the values in the two data register lldrl and lldrh and by the bits l lshort and lltco. 12.6.11 lldrh ? low leakage voltage regulator data register (high-byte) bit 7 6 5 4 3 2 1 0 na ($131) res2 res1 res0 lldrh4 lldrh3 lldrh2 lldrh1 lldrh0 lldrh read/write r r r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the high-byte of the calibration data can be access ed through this register. write access is only enabled when the bit llencal of the llcr register is 0. then the data bits lldrh4:0 directly control the output voltage o f the low-leakage voltage regulator. higher numbers generate lower voltages. if the bit llencal is 1 then the results of the automatic calibration are stored. ? bit 7:5 ? res2:0 - reserved these bits are reserved for future use. 175 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 4:0 ? lldrh4:0 - high-byte data register bits value of the high-byte calibration result table 12-5 lldrh register bits register bits value description 0x00 calibration limit for fast process corner/high output voltage lldrh4:0 0x10 calibration limit for slow process corner/low output voltage 12.6.12 lldrl ? low leakage voltage regulator data register (low-byte) bit 7 6 5 4 3 2 1 0 na ($130) res3 res2 res1 res0 lldrl3 lldrl2 lldrl1 lldrl0 lldrl read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 the low-byte of the calibration data can be accesse d through this register. write access is only enabled when the bit llencal of the llcr re gister is 0. then the data bits lldrl3:0 directly control the output voltage of the low-leakage voltage regulator. higher numbers generate lower voltages. the content s of this register is meaningless when the bit llshort of the llcr register is 1. if the bit llencal is 1 then the results of the automatic calibration are stored. ? bit 7:4 ? res3:0 - reserved these bits are reserved for future use. ? bit 3:0 ? lldrl3:0 - low-byte data register bits value of the low-byte calibration result table 12-6 lldrl register bits register bits value description 0x00 calibration limit for fast process corner/high output voltage lldrl3:0 0x08 calibration limit for slow process corner/low output voltage 12.6.13 dpds0 ? port driver strength register 0 bit 7 6 5 4 3 2 1 0 na ($136) pfdrv1 pfdrv0 pedrv1 pedrv0 pddrv1 pddrv0 pbdrv1 pbdrv0 dpds0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output driver strength can be set individually for each digital i/o port. the following tables show output current levels for a typical sup ply voltage of devdd = 3.3v. refer to section "electrical characteristics" for details. ? bit 7:6 ? pfdrv1:0 - driver strength port f 176 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 12-7 pfdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pfdrv1:0 3 8 ma ? bit 5:4 ? pedrv1:0 - driver strength port e table 12-8 pedrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pedrv1:0 3 8 ma ? bit 3:2 ? pddrv1:0 - driver strength port d table 12-9 pddrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pddrv1:0 3 8 ma ? bit 1:0 ? pbdrv1:0 - driver strength port b table 12-10 pbdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pbdrv1:0 3 8 ma 12.6.14 dpds1 ? port driver strength register 1 bit 7 6 5 4 3 2 1 0 na ($137) res5 res4 res3 res2 res1 res0 pgdrv1 pgdrv0 dpds1 read/write r r r r r r rw rw initial value 0 0 0 0 0 0 0 0 the output driver strength can be set individually for each digital i/o port. the following table shows output current levels for a typical sup ply voltage of devdd = 3.3v. refer to section "electrical characteristics" for details. ? bit 7:2 ? res5:0 - reserved ? bit 1:0 ? pgdrv1:0 - driver strength port g driver strength can be set for port g except the po rt pins pg3 and pg4. the leakage current of the ports pg3 and pg4 is reduced. 177 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 12-11 pgdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pgdrv1:0 3 8 ma 178 8266c-mcu wireless-08/11 ATMEGA128RFA1 13 system control and reset 13.1 resetting the avr during reset, all i/o registers are set to their in itial values, and the program starts execution from the reset vector. the instruction pl aced at the reset vector must be a jmp ? absolute jump ? instruction to the reset hand ling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 13-1 on page 179 shows the reset logic. "system and reset characteristics" on page 510 defines the electrical parameters of the reset cir cuitry. the i/o ports of the avr are immediately reset to t heir initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a st able level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the different selections for the d elay period are presented in "clock sources" on page 149 . 13.2 reset sources the ATMEGA128RFA1 has five sources of reset: ? power-on reset. the mcu is reset when the supply v oltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the rstn pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage evdd is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system . refer to the section "ieee 1149.1 (jtag) boundary-scan" on page 442 for details. 179 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 13-1. reset logic evdd rstn delay counters s q r mcu status register (mcusr) bodlevel [2..0] cksel[3:0] ck timeout wdrf borf extrf data bus spike filter pull-up resistor jtrf sut[1:0] jtag reset register brown-out reset circuit power-on reset circuit reset circuit watchdog timer watchdog oscillator clock generator internal reset counter reset porf devdd 13.2.1 power-on reset a power-on reset (por) pulse is generated by a dyna mic, on-chip detection circuit. the por is active when devdd is rising. the electri cal characteristics are defined in "system and reset characteristics" on page 510 . the por circuit can be used to trigger the start-up reset. to detect a failure in the supply voltage (e.g. a voltage drop) the brown-own detector should be used. a power-on reset (por) circuit ensures that the dev ice is reset from power-on. reaching the power-on reset threshold voltage invok es the delay counter, which determines how long the device is kept in reset aft er the devdd rise. the reset signal is activated again without any delay, when d evdd decreases below the detection level. figure 13-2. mcu start-up, rstn tied to devdd devdd rstn time-out internal reset v pot v rst t tout 180 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 13-3. mcu start-up, rstn extended externally v cc rstn time-out internal reset v pot v rst t tout 13.2.2 external reset an external reset is generated by a low level on th e rstn pin. reset pulses longer than the minimum pulse width (see "system and reset characteristics" on page 510 ) will generate a reset, even if the clock is not run ning. shorter pulses are not guaranteed to generate a reset. when the applied signal reache s the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts t he mcu after the time-out period ? t tout ? has expired. figure 13-4. reset during operation devdd rstn time-out internal reset t tout v rst 13.2.3 brown-out detection ATMEGA128RFA1 has an on-chip brown-out detection (b od) circuit for monitoring the evdd level during operation by comparing it to a fi xed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hyste resis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. when the bod is enabled, and evdd decreases to a va lue below the trigger level (v bot- in figure 13-5 on page 181), the brown-out reset is immediately acti vated. when evdd increases above the trigger level (v bot+ in figure 13-5 on page 181), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in evdd if the voltage stays below the trigger level for longer than t bod given in "system and reset characteristics" on page 510 . 181 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 13-5. brown-out reset during operation evdd rstn time-out internal reset t tout v bot- v bot+ 13.2.4 watchdog reset when the watchdog times out, it will generate a sho rt reset pulse of one ck cycle duration. on the falling edge of this pulse, the de lay timer starts counting the time-out period t tout . see "watchdog timer" on page 182. for details on operation of the watchdog timer. figure 13-6. watchdog reset during operation devdd rstn reset time-out internal reset t tout 1 ck cycle wdt time-out 13.3 internal voltage reference ATMEGA128RFA1 features an internal bandgap referenc e. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in "system and reset characteristics" on page 510 . to save power, the reference is not always turned on. the r eference is on during the following situations: 1. when the bod is enabled (by programming the bodl evel [2:0] fuse). 2. when the bandgap reference is connected to the a nalog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting th e acbg bit or enabling the adc, the user must always allow the reference to start u p before the output from the analog comparator or adc is used. to reduce power consumpt ion in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 182 8266c-mcu wireless-08/11 ATMEGA128RFA1 13.4 watchdog timer 13.4.1 features ? clocked from separate on-chip oscillator ? 3 operating modes - interrupt - system reset - interrupt and system reset ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) f or fail-safe mode figure 13-7. watchdog timer 128khz oscillator osc/2kosc/4k osc/8k osc/16kosc/32k osc/64k osc/128kosc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 wat chdog reset wde wdif wdie mcu reset interrupt 13.4.2 overview ATMEGA128RFA1 has an enhanced watchdog timer (wdt). the wdt is a timer counting cycles of a separate on-chip 128 khz oscil lator. the wdt gives an interrupt or a system reset when the counter reaches a given tim e-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be i ssued. in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and al so as a general system timer. one example is to limit the maximum time allowed fo r certain operations, giving an interrupt when the operation has run longer than ex pected. in system reset mode, the wdt gives a reset when the timer expires. this is t ypically used to prevent system hang-up in case of runaway code. the third mode, in terrupt and system reset mode, combines the other two modes by first giving an int errupt and then switch to system reset mode. this mode will for instance allow a saf e shutdown by saving critical parameters before a system reset. the watchdog always on (wdton) fuse, if programmed, will force the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure 183 8266c-mcu wireless-08/11 ATMEGA128RFA1 program security, alterations to the watchdog set-u p must follow timed sequences. the sequence for clearing wde and changing time-out con figuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardl ess of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this mus t be done in one operation. the following code example shows one assembly and o ne c function for turning off the watchdog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occ ur during the execution of these functions. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 186 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 6 ? wdie - watchdog timeout interrupt enable when this bit is written to one and the i-bit in th e status register is set, the watchdog interrupt is enabled. if wde is cleared in combinat ion with this setting, the watchdog timer is in interrupt mode, and the corresponding i nterrupt is executed if time-out in the watchdog timer occurs. if wde is set, the watchdog timer is in interrupt and system reset mode. the first time-out in the watchdog time r will set wdif. executing the corresponding interrupt vector will clear wdie and wdif automatically by hardware (the watchdog goes to system reset mode). this is u seful for keeping the watchdog timer security while using the interrupt. to stay i n interrupt and system reset mode, wdie must be set after each interrupt. this should however not be done within the interrupt service routine itself, as this might com promise the safety-function of the watchdog system reset mode. if the interrupt is not executed before the next time-out, a system reset will be applied. table 13-1. watchdog timer configuration wdton (1) wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 1 1 1 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset note: 1. wdton fuse set to ?0? means programmed and ?1? means un-programmed. ? bit 4 ? wdce - watchdog change enable this bit is used in timed sequences for changing wd e and prescaler bits. to clear the wde bit, and/or change the prescaler bits, wdce mus t be set. once written to one, hardware will clear wdce after four clock cycles. ? bit 3 ? wde - watch dog enable when the wde is set (one) the watchdog timer is ena bled, and if the wde is cleared (zero) the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set (one). to disable an enabled watch dog timer, the following procedure must be followed: 1. in the same operation, write a logical one to wdtoe and wde. a logical one must be written to wde even though it i s set to one before the disable operation starts. 2. within the next four clock cyc les, write a logical 0 to wde. this disables the watchdog. wde is overridden by wdrf in mcusr. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensures multiple resets during conditions c ausing failure, and a safe start-up after the failure. ? bit 5, 2:0 ? wdp3:0 ? watchdog timer prescaler 3, 2 , 1 and 0 the wdp3:0 bits determine the watchdog timer presca ling when the watchdog timer is running. table 13-2. wdp register bits register bits value description 0x00 oscillator cycles 2k, (16ms) 0x01 oscillator cycles 4k, (32ms) 0x02 oscillator cycles 8k, (64ms) wdp3:0 0x03 oscillator cycles 16k, (0.125s) 187 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x04 oscillator cycles 32k, (0.25s) 0x05 oscillator cycles 64k, (0.5s) 0x06 oscillator cycles 128k, (1.0s) 0x07 oscillator cycles 256k, (2.0s) 0x08 oscillator cycles 512k, (4.0s) 0x09 oscillator cycles 1024k, (8.0s) 188 8266c-mcu wireless-08/11 ATMEGA128RFA1 14 i/o-ports 14.1 introduction all ATMEGA128RFA1 ports have true read-modify-write functionality when used as general digital i/o ports. this means that the dire ction of one port pin can be changed without unintentionally changing the direction of a ny other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configu red as input). each output buffer has symmetrical drive characteristics with both configu rable sink and source capability. every port is individually configurable in four dif ferent drive strengths. the pin driver is strong enough to drive led displays directly. all p ort pins have individually selectable pull-up resistors with a supply-voltage invariant r esistance. all i/o pins have protection diodes to both devdd and dvss as indicated in figure 14-1 below . refer to "electrical characteristics" on page 507 for a complete list of parameters. figure 14-1. i/o pin equivalent schematic all registers and bit references in this section ar e written in general form. a lower case ?x? represents the numbering letter for the port, a nd a lower case ?n? represents the bit number. however, when using the register or bit def ines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. three i/o memory address locations are allocated fo r each port, one each for the data register ? portx, data direction register ? ddrx, a nd the port input pins ? pinx. the port input pins i/o location is read only, whil e the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the correspond ing bit in the data register. in addition, the pull-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is descri bed in "ports as general digital i/o" on page 189. most port pins are multiplexed with alte rnate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in "alternate port functions" on page 193. refer to the individual module sections for a full description of the alternate fu nctions. note that enabling the alternate function of some o f the port pins does not affect the use of the other pins in the port as general digital i/ o. 189 8266c-mcu wireless-08/11 ATMEGA128RFA1 14.2 ports as general digital i/o the ports are bi-directional i/o ports with optiona l internal pull-ups. figure 14-2 below shows a functional description of one i/o-port pin, here generically called pxn. figure 14-2. general digital i/o (1) dpds0/dpds1 dpds0/dpds1: drive strength register note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to a ll pins within the same port. clk i/o , sleep, and pud are common to all ports. 14.2.1 configuring the port drive strength of output buffers is configurable po rt-wise. source/sink capably of 2ma, 4ma, 6ma or 8ma is selectable through registers dpd s1 and dpds0. note that pins pg3 and pg4 of portg have fixed drive strength of 2 ma to enable the operation of the low power crystal oscillator. 14.2.2 configuring the pin each port pin consists of three register bits: ddxn , portxn, and pinxn. the ddxn bits are accessed at the ddrx i/o address, the portxn bi ts at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direc tion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if d dxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is conf igured as an input pin, the pull-up resistor is activated. to switch the pull-up resist or off, portxn has to be written logic zero or the pin has to be configured as an output p in. the port pins are tri-stated when reset condition becomes active, even if no clocks a re running. if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic ze ro when the pin is configured as an output pin, the port pin is driven low (zero). 190 8266c-mcu wireless-08/11 ATMEGA128RFA1 14.2.3 toggling the pin writing a logic one to pinxn toggles the value of p ortxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 14.2.4 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must oc cur. normally, the pull-up enabled state is fully acceptable, as a high-impeda nt environment will not notice the difference between a strong high driver and a pull- up. if this is not the case, the pud bit in the mcucr register can be set to disable all pul l-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. the following table summarizes the control signals for the pin value. table 14-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pul led low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 14.2.5 reading the pin value independent of the setting of data direction bit dd xn, the port pin can be read through the pinxn register bit. as shown in figure 14-2 on page 189, the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid meta-stability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 14-3 on page 191 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. 191 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 14-3. synchronization when reading an external applied pi n value consider the clock period starting shortly after th e first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sync latc h? signal. the signal value is latched when the system clock goes low. it is clock ed into the pinxn register at the succeeding positive clock edge. as indicated by the two arrows t pd,max and t pd,min , a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 14-4 below . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the d elay t pd through the synchronizer is 1 system clock period. figure 14-4. synchronization when reading software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but a s previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. 192 8266c-mcu wireless-08/11 ATMEGA128RFA1 assembly code example (1) ? ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 194 8266c-mcu wireless-08/11 ATMEGA128RFA1 note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to a ll pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. the following table summarizes the function of the overriding signals. the pin and port indexes from figure 14-5 on page 193 are not shown in the succeeding tables. t he overriding signals are generated internally in the modules having the alternate function. table 14-2. generic description of overriding signals for alter nate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is contro lled by the puov signal. if this signal is cleared, the pul l-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled whe n puov is set/cleared, regardless of the setting of t he ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cl eared, the output driver is enabled by the ddxn register b it. ddov data direction override value if ddoe is set, the output driver is enabled/disabl ed when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enab led, the port value is controlled by the pvov signal. if pvo e is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bi t. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted . dieoe digital input enable override enable if this bit is set, the digital input enable is con trolled by the dieov signal. if this signal is cleared, the di gital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disab led when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of th e schmitt-trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronize r. aio analog input/output this is the analog inp ut/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. the following subsections shortly describe the alte rnate functions for each port, and relate the overriding signals to the alternate func tion. refer to the alternate function description for further details. 14.3.1 alternate functions of port b the port b pins with alternate functions are shown in the following table. 195 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-3. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c/pcint7 (output compare and pwm out put a for timer/counter0, output compare and pwm output c for timer/counter1 or pin change interrupt 7) pb6 oc1b/pcint6 (output compare and pwm output b for timer/counter1 or pin change interrupt 6) pb5 oc1a/pcint5 (output compare and pwm output a for timer/counter1 or pin change interrupt 5) pb4 oc2a/pcint4 (output compare and pwm output a for timer/counter2 or pin change interrupt 4) pb3 miso/pdo/pcint3 (spi bus master input/slave output, programming data output or pin change interrupt 3) pb2 mosi/pdi/pcint2 (spi bus master output/slave input , programming data input or pin change interrupt 2) pb1 sck/pcint1 (spi bus serial clock or pin chan ge interrupt 1) pb0 ss /pcint0 (spi slave select input or pin c hange interrupt 0) the alternate pin configuration is as follows: ? oc0a/oc1c/pcint7, bit 7 oc0a, output compare match a output: the pb7 pin ca n serve as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a p in is also the output pin for the pwm mode timer function. oc1c, output compare match c output: the pb7 pin ca n serve as an external output for the timer/counter1 output compare c. the pin ha s to be configured as an output (ddb7 set (one)) to serve this function. the oc1c p in is also the output pin for the pwm mode timer function. pcint7, pin change interrupt source 7: the pb7 pin can serve as an external interrupt source. ? oc1b/pcint6, bit 6 oc1b, output compare match b output: the pb6 pin ca n serve as an external output for the timer/counter1 output compare b. the pin ha s to be configured as an output (ddb6 set (one)) to serve this function. the oc1b p in is also the output pin for the pwm mode timer function. pcint6, pin change interrupt source 6: the pb6 pin can serve as an external interrupt sourceoc1a, output compare match a output: the pb5 pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set (one)) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint5, pin change interrupt source 5: the pb5 pin can serve as an external interrupt source. ? oc2a/pcint4, bit 4 oc2a, output compare match output: the pb4 pin can serve as an external output for the timer/counter2 output compare. the pin has to b e configured as an output (ddb4 set (one)) to serve this function. the oc2a pin is also the output pin for the pwm mode timer function. 196 8266c-mcu wireless-08/11 ATMEGA128RFA1 pcint4, pin change interrupt source 4: the pb4 pin can serve as an external interrupt source. ? miso/pdo/pcint3 ? port b, bit 3 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an i nput regardless of the setting of ddb3. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb3. when the pin is forced to be an input, the pu ll-up can still be controlled by the portb3 bit. pdo, spi serial programming data output. during ser ial program downloading, this pin is used as data output line (see section "serial downloading" on page 479 for details). pcint3, pin change interrupt source 3: the pb3 pin can serve as an external interrupt source. ? mosi/pdi/pcint2 ? port b, bit 2 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an in put regardless of the setting of ddb2. when the spi is enabled as a master, the data direc tion of this pin is controlled by ddb2. when the pin is forced to be an input, the pu ll-up can still be controlled by the portb2 bit. pdi, spi serial programming data input. during seri al program downloading, this pin is used as data input line (see section "serial downloading" on page 479 for details). pcint2, pin change interrupt source 2: the pb2 pin can serve as an external interrupt source. ? sck/pcint1 ? port b, bit 1 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an in put regardless of the setting of ddb1. when the spi0 is enabled as a master, the data dire ction of this pin is controlled by ddb1. when the pin is forced to be an input, the pu ll-up can still be controlled by the portb1 bit. pcint1, pin change interrupt source 1: the pb1 pin can serve as an external interrupt source. ? ss /pcint0 ? port b, bit 0 ss : slave port select input. when the spi is enab led as a slave, this pin is configured as an input regardless of the setting of ddb0. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a mas ter, the data direction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 bit. table 14-4 below and table 14-5 on page 197 relate the alternate functions of port b to the overriding signals shown in figure 14-5 on page 193. spi mstr input and spi slave output constitute the miso signal, while mosi is divided into spi mstr output and spi slave input. pcint0, pin change interrupt source 0: the pb0 pin can serve as an external interrupt source. table 14-4. overriding signals for alternate functions in pb7:p b4 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puoe 0 0 0 0 197 8266c-mcu wireless-08/11 ATMEGA128RFA1 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0/oc1c enable oc1b enable oc1a enable oc2a enable pvov oc0/oc1c oc1b oc1a oc2a dieoe pcint7?pcie0 pcint6?pcie0 pcint5?pcie0 pcint4?pcie0 dieov 1 1 1 1 di pcint7 input pcint6 input pcint5 input pcint4 input aio ? ? ? ? table 14-5. overriding signals for alternate functions in pb3:pb0 signal name pb3/miso/pdo pb2/mosi/pdi pb1/sck pb0/ss puoe spe?mstr spe?(~mstr) spe?(~mstr) spe?(~ mstr) puov portb3?(~pud) portb2?(~pud) portb1?(~pud) p ortb0?(~pud) ddoe spe?mstr spe?(~mstr) spe?(~mstr) spe?(~ms tr) ddov 0 0 0 0 pvoe spe?(~mstr) spe?mstr spe?mstr 0 pvov spi slave output spi mstr output sck output 0 dieoe pcint3?pcie0 pcint2?pcie0 pcint1?pcie0 pcint0 ?pcie0 dieov 1 1 1 1 di spi mstr input pcint3 input spi slave input pcint2 input sck input pcint1 input spi ss pcint0 input aio ? ? ? ? 14.3.2 alternate functions of port d the port d pins with alternate functions are shown in the following table. table 14-6. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 t1 (timer/counter1 clock input) pd5 xck1 (usart1 external clock input/output) pd4 icp1 (timer/counter1input capture trigger) pd3 int3/txd1 (external interrupt3 input or usart1 transmit pin) pd2 int2/rxd 1(external interrupt2 input or usart1 receive pin) pd1 int1/sda (external interrupt1 input or twi seri al data) pd0 int0/scl (external interrupt0 input or twi seri al clock) the alternate pin configuration is as follows: ? t0 ? port d, bit 7 t0, this is timer/counter0 counter source. 198 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? t1 ? port d, bit 6 t1, this is timer/counter1 counter source. ? xck1 ? port d, bit 5 xck1, usart1 external clock: the data direction reg ister (ddd5) controls whether the clock is output (ddd5 set) or input (ddd5 clear ed). the xck1 pin is active only when the usart1 operates in synchronous mode. ? icp1 ? port d, bit 4 icp1 ? input capture pin 1: the pd4 pin can act as an input capture pin for timer/counter1. ? int3/txd1 ? port d, bit 3 int3, external interrupt source 3: the pd3 pin can serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1 ). when the usart1 transmitter is enabled, this pin is configured as an output reg ardless of the value of ddd3. ? int2/rxd1 ? port d, bit 2 int2, external interrupt source 2: the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the usart1). when the usart1 receiver is enabled this pin is configured as an input regardle ss of the value of ddd2. when the usart forces this pin to be an input, the pull-up c an still be controlled by the portd2 bit. ? int1/sda ? port d, bit 1 int1, external interrupt source 1: the pd1 pin can serve as an external interrupt source to the mcu. sda, 2-wire serial interface data: when the twen bi t in twcr is set (one) to enable the 2-wire serial interface, pin pd1 is disconnecte d from the port and becomes the serial data i/o pin for the 2-wire serial interface . in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on th e input signal, and the pin is driven by an open drain driver with slew rate limitation. ? int0/scl ? port d, bit 0 int0, external interrupt source 0: the pd0 pin can serve as an external interrupt source to the mcu. scl, 2-wire serial interface clock: when the twen b it in twcr is set (one) to enable the 2-wire serial interface, pin pd0 is disconnecte d from the port and becomes the serial clock i/o pin for the 2-wire serial interfac e. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on th e input signal, and the pin is driven by an open drain driver with slew-rate limitation. table 14-7 below and table 14-8 on page 199 relates the alternate functions of port d to the overriding signals shown in figure 14-5 on page 193. table 14-7. overriding signals for alternate functions pd7:pd4 signal name pd7/t0 pd6/t1 pd5/xck1 pd4/icp1 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 xck1 output enable 0 199 8266c-mcu wireless-08/11 ATMEGA128RFA1 signal name pd7/t0 pd6/t1 pd5/xck1 pd4/icp1 ddov 0 0 1 0 pvoe 0 0 xck1 output enable 0 pvov 0 0 xck1 output 0 dieoe 0 0 0 0 dieov 0 0 0 0 di t0 input t1 input xck1 input icp1 input aio ? ? ? ? table 14-8. overriding signals for alternate functions pd3:pd0 signal name pd3/int3/txd1 pd2/int2/rxd1 pd1/int1/sda pd0/int0/s cl puoe txen1 rxen1 twen twen puov 0 portd2&(~pud) portd1&(~pud) portd0&(~pud) ddoe txen1 rxen1 twen twen ddov 1 0 sda_out scl_out pvoe txen1 0 twen twen pvov txd1 0 0 0 dieoe int3 enable int2 enable int1 enable int0 enab le dieov 1 1 1 1 di int3 input int2 input/rxd1 int1 input int0 input aio - - sda input scl input note: 1. when enabled, the 2-wire serial interface enable s slew-rate controls on the output pins pd0 and pd1. this is not shown in this table. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. 14.3.3 alternate functions of port e the port e pins with alternate functions are shown in the following table. table 14-9. port e pins alternate functions port pin alternate function pe7 int7/icp3/clk0 (external interrupt7 input, time r/counter3 input capture trigger or divided system clock) pe6 int6/t3 (external interrupt6 input or timer/cou nter3 clock input) pe5 int5/oc3c (external interrupt5 input or output compare and pwm output c for timer/counter3) pe4 int4/oc3b (external interrupt4 input or output compare and pwm output b for timer/counter3) pe3 ain1/oc3a (analog comparator negative input or output compare and pwm output a for timer/counter3) pe2 ain0/xck0 (analog comparator or positive input or usart0 external clock input/output) pe1 txd0 (usart0 transmit pin) 200 8266c-mcu wireless-08/11 ATMEGA128RFA1 port pin alternate function pe0 rxd0/pcint8 (usart0 receive pin or pin change i nterrupt8) ? int7/icp3/clko ? port e, bit 7 int7, external interrupt source 7: the pe7 pin can serve as an external interrupt source. icp3, input capture pin 3: the pe7 pin can act as a n input capture pin for timer/counter3. clko - divided system clock: the divided system clo ck can be output on the pe7 pin. the divided system clock will be output if the ckou t fuse is programmed, regardless of the porte7 and dde7 settings. it will also be ou tput during reset. ? int6/t3 ? port e, bit 6 int6, external interrupt source 6: the pe6 pin can serve as an external interrupt source. t3, this is the timer/counter3 counter source. ? int5/oc3c ? port e, bit 5 int5, external interrupt source 5: the pe5 pin can serve as an external interrupt source. oc3c, output compare match c output: the pe5 pin ca n serve as an external output for the timer/counter3 output compare c. the pin ha s to be configured as an output (dde5 set ?one?) to serve this function. the oc3c p in is also the output pin for the pwm mode timer function. ? int4/oc3b ? port e, bit 4 int4, external interrupt source 4: the pe4 pin can serve as an external interrupt source. oc3b, output compare match b output: the pe4 pin ca n serve as an external output for the timer/counter3 output compare b. the pin ha s to be configured as an output (dde4 set (one)) to serve this function. the oc3b p in is also the output pin for the pwm mode timer function. ? ain1/oc3a ? port e, bit 3 ain1 ? analog comparator negative input. this pin i s directly connected to the negative input of the analog comparator. oc3a, output compare match a output: the pe3 pin ca n serve as an external output for the timer/counter3 output compare a. the pin ha s to be configured as an output (dde3 set ?one?) to serve this function. the oc3a p in is also the output pin for the pwm mode timer function. ? ain0/xck0 ? port e, bit 2 ain0 ? analog comparator positive input. this pin i s directly connected to the positive input of the analog comparator. xck0, this is the usart0 external clock. the data d irection register (dde2) controls whether the clock is output (dde2 set) or input (dd e2 cleared). the xck0 pin is active only when the usart0 operates in synchronous mode. ? txd0 ? port e, bit 1 txd0, this is the usart0 transmit pin. ? rxd0/pcint8 ? port e, bit 0 201 8266c-mcu wireless-08/11 ATMEGA128RFA1 rxd0, usart0 receive pin. receive data (data input pin for the usart0). when the usart0 receiver is enabled this pin is configured a s an input regardless of the value of ddre0. when the usart0 forces this pin to be an inp ut, a logical one in porte0 will turn on the internal pull-up. pcint8, pin change interrupt source 8: the pe0 pin can serve as an external interrupt source. table 14-10 below and table 14-11 below relates the alternate functions of port e to the overriding signals shown in figure 14-5 on page 193. table 14-10. overriding signals for alternate functions pe7:pe4 signal name pe7/int7/icp3 pe6/int6/t3 pe5/int5/oc3c pe4/int4/oc 3b puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 oc3c enable oc3b enable pvov 0 0 oc3c oc3b dieoe int7 enable int6 enable int5 enable int4 enab le dieov 1 1 1 1 di int7 input / icp3 input int7 input / t3 input int5 input int4 input aio ? ? ? ? table 14-11. overriding signals for alternate functions pe3:pe0 signal name pe3/ain1/oc3a pe2/ain0/xck0 pe1/txd0 pe0 / rxd0/pcint8 puoe 0 0 txen0 rxen0 puov 0 0 0 porte0 & (~pud) ddoe 0 xck0 output enable txen0 rxen0 ddov 0 1 1 0 pvoe oc3benable xck0 output enable txen0 0 pvov oc3b xck0 output txd0 0 dieoe 0 0 0 pcint8 & pcie1 dieov 0 0 0 1 di 0 xck0 input ? rxd0 pe0 0 0 0 pcint8 input aio ain1 input ain0 input - - 14.3.4 alternate functions of port f the port f has an alternate function as analog inpu t for the adc as shown in table 14-12 on page 202. if some port f pins are configured as ou tputs, it is essential that these do not switch when a conversion is in progres s. this might corrupt the result of the conversion. if the jtag interface is enabled, t he pull-up resistors on pins pf7(tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. 202 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-12. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag test data input) pf6 adc6/tdo (adc input channel 6 or jtag test data output) pf5 adc5/tms (adc input channel 5 or jtag test mode select) pf4 adc4/tck (adc input channel 4 or jtag test cloc k) pf3 adc3/dig4 (adc input channel 3 or radio transce iver rx/tx indicator output) pf2 adc2/dig2 (adc input channel 2 or radio transce iver antenna diversity control output) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, channel 7. tdi, jtag test data in: serial input data to be shi fted in to the instruction register or data register (scan chains). when the jtag interfac e is enabled, this pin can not be used as an i/o pin. ? tdo, adc6 ? port f, bit 6 adc6, analog to digital converter, channel 6. tdo, jtag test data out: serial output data from in struction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. the tdo pin is tri-stated unless tap states that sh ift out data are entered. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, channel 5. tms, jtag test mode select: this pin is used for na vigating through the tap- controller state machine. when the jtag interface i s enabled, this pin can not be used as an i/o pin. ? tck, adc4 ? port f, bit 4 adc4, analog to digital converter, channel 4. tck, jtag test clock: jtag operation is synchronous to tck. when the jtag interface is enabled, this pin can not be used as a n i/o pin. ? dig4, adc3 ? port f, bit 3 adc3, analog to digital converter, channel 3. dig4, radio transceiver rx/tx indicator output: if the bit pa_ext_en in trx_ctrl_1 is set to one then the pf3 pin serves as the radio transceiver receive/transmit indicator output to control an ext ernal rf front-end. ? dig2, adc2 ? port f, bit 2 adc2, analog to digital converter, channel 2. dig2, radio transceiver antenna diversity control o utput: if the bit ant_ext_sw_en in ant_div is set to one then the pf2 pin serves as a radio transceiver output to control external antenna dive rsity. ? adc1 ? adc0 ? port f, bit 1:0 analog to digital converter, channel 1:0. 203 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-13. overriding signals for alternate functions pf7:pf4 signal name pf7/adc7/tdi pf6/adc6/tdo pf5/adc5/tms pf4/adc4/tck puoe jtagen jtagen jtagen jtagen puov 1 0 1 1 ddoe jtagen jtagen jtagen jtagen ddov 0 shift_ir+shift_dr 0 0 pvoe 0 jtagen 0 0 pvov 0 tdo 0 0 dieoe jtagen jtagen jtagen jtagen dieov 0 0 0 0 di ? ? ? ? aio tdi/adc7 input adc6 input tms/adc5 input tck/adc4 input table 14-14. overriding signals for alternate functions pf3:pf0 signal name pf3/adc3/dig4 pf2/adc2/dig2 pf1/adc1 pf0/adc0 puoe 0 0 0 0 puov 0 0 0 0 ddoe pa_ext_en ant_ext_sw_en 0 0 ddov pa_ext_en ant_ext_sw_en 0 0 pvoe pa_ext_en ant_ext_sw_en 0 0 pvov dig4 dig2 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio adc3 input adc2 input adc1 input adc0 input 14.3.5 alternate functions of port g the port g alternate pin configuration is as follow s: table 14-15. port g pins alternate functions port pin alternate function pg5 oc0b (output compare and pwm output b for timer /counter0) pg4 tosc1 (rtc oscillator timer/counter2) pg3 tosc2 (rtc oscillator timer/counter2) pg2 amr (automated meter reading - counter input for timer/counter2) pg1 dig1 (radio transceiver antenna diversity contr ol output) pg0 dig3 (radio transceiver rx/tx indicator output) ? oc0b ? port g, bit 5 oc0b, output compare match b output: the pg5 pin ca n serve as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddg5 set) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. ? tosc1 ? port g, bit 4 204 8266c-mcu wireless-08/11 ATMEGA128RFA1 tosc2, timer oscillator pin 1: setting the as2 bit to one and the exclkamr bit to zero in assr, enables asynchronous clocking of time r/counter2 by a crystal oscillator. the pin pg4 is disconnected from the po rt, and becomes the input of the inverting oscillator amplifier. in this mode, a cry stal oscillator is connected to this pin, and the pin can not be used as an i/o pin. tosc2 ? port g, bit 3 tosc2, timer oscillator pin 2: setting the as2 bit to one and the exclkamr bit to zero in assr, enables asynchronous clocking of time r/counter2 by a crystal oscillator. the pin pg3 is disconnected from the po rt, and becomes the inverting output of the oscillator amplifier. in this mode, a crysta l oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? amr ? port g, bit 2 amr, automated meter reading input: setting the as2 and the exclkamr bits in assr to one, enables asynchronous clocking of timer /counter2 by the amr pin ? dig1 ? port g, bit 1 dig1, radio transceiver antenna diversity control o utput: if the bit ant_ext_sw_en in ant_div is set to one then the pg1 pin serves as a radio transceiver output to control external antenna dive rsity. ? dig3 ? port g, bit 0 dig3, radio transceiver rx/tx indicator output: if the bit pa_ext_en in trx_ctrl_1 is set to one then the pg0 pin serves as the radio transceiver receive/transmit indicator output to control an ext ernal rf front-end. table 14-16 below relates the alternate functions of port g to the o verriding signals shown in figure 14-5 on page 193. table 14-16. overriding signals for alternate functions pg5:pg2 signal name pg5/oc0b pg4/tosc1 pg3/tosc2 pg2/amr puoe ? as2 & (~exclkamr) as2 & (~exclkamr) & (~exclk) as2 & exclkamr puov ? 0 0 0 ddoe ? as2 & (~exclkamr) as2 & (~exclkamr) & (~exclk) as2 & exclkamr ddov ? 0 0 0 pvoe oc0b enable 0 0 0 pvov oc0b 0 0 0 dieoe ? as2 & (~exclkamr) as2 & (~exclkamr) & (~exclk) as2 & exclkamr dieov ? exclk 0 1 di ? ? ? amr aio ? t/c2 osc input t/c2 osc output ? 205 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-17. overriding signals for alternate functions pg1:pg0 signal name pg1/dig1 pg0/dig3 puoe 0 0 puov 0 0 ddoe ant_ext_sw_en pa_ext_en ddov ant_ext_sw_en pa_ext_en pvoe ant_ext_sw_en pa_ext_en pvov dig1 dig3 dieoe 0 0 dieov 0 0 di ? ? aio ? ? 14.4 register description for a detailed description of register mcucr see ch apter "mcucr ? mcu control register" on page 217 . 14.4.1 mcucr ? mcu control register bit 7 6 5 4 3 2 1 0 $35 ($55) pud mcucr read/write rw initial value 0 the mcu control register contains control bits of t he general microcontroller unit functions. ? bit 4 ? pud - pull-up disable when this bit is written to one, the i/o ports pull -up resistors are disabled even if the ddxn and portxn registers are configured to enable the pull-up resistor ({ddxn, portxn} = 2'b01). see section "ports as general dig ital i/o" for more details about this feature. 14.4.2 dpds0 ? port driver strength register 0 bit 7 6 5 4 3 2 1 0 na ($136) pfdrv1 pfdrv0 pedrv1 pedrv0 pddrv1 pddrv0 pbdrv1 pbdrv0 dpds0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output driver strength can be set individually for each digital i/o port. the following tables show output current levels for a typical sup ply voltage of devdd = 3.3v. refer to section "electrical characteristics" for details. ? bit 7:6 ? pfdrv1:0 - driver strength port f 206 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-18 pfdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pfdrv1:0 3 8 ma ? bit 5:4 ? pedrv1:0 - driver strength port e table 14-19 pedrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pedrv1:0 3 8 ma ? bit 3:2 ? pddrv1:0 - driver strength port d table 14-20 pddrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pddrv1:0 3 8 ma ? bit 1:0 ? pbdrv1:0 - driver strength port b table 14-21 pbdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pbdrv1:0 3 8 ma 14.4.3 dpds1 ? port driver strength register 1 bit 7 6 5 4 3 2 1 0 na ($137) res5 res4 res3 res2 res1 res0 pgdrv1 pgdrv0 dpds1 read/write r r r r r r rw rw initial value 0 0 0 0 0 0 0 0 the output driver strength can be set individually for each digital i/o port. the following table shows output current levels for a typical sup ply voltage of devdd = 3.3v. refer to section "electrical characteristics" for details. ? bit 7:2 ? res5:0 - reserved ? bit 1:0 ? pgdrv1:0 - driver strength port g driver strength can be set for port g except the po rt pins pg3 and pg4. the leakage current of the ports pg3 and pg4 is reduced. 207 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 14-22 pgdrv register bits register bits value description 0 2 ma 1 4 ma 2 6 ma pgdrv1:0 3 8 ma 14.4.4 portb ? port b data register bit 7 6 5 4 3 2 1 0 $05 ($25) portb7:0 portb read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 if portbn is written logic one when the portb pin n is configured as an input pin, the pull-up resistor is activated. to switch the pull-u p resistor off, portbn has to be written logic zero or the pin has to be configured as an ou tput pin. if portbn is written logic one when the pin is configured as an output pin, th e port pin is driven high (one). if portbn is written logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). ? bit 7:0 ? portb7:0 - port b data register value 14.4.5 ddrb ? port b data direction register bit 7 6 5 4 3 2 1 0 $04 ($24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ddbn bit in the ddrb register selects the direc tion of the portb pin n. if ddbn is written logic one, pbn is configured as an outpu t pin. if ddbn is written logic zero, pbn is configured as an input pin. ? bit 7:0 ? ddb7:0 - port b data direction register v alue 14.4.6 pinb ? port b input pins address bit 7 6 5 4 3 2 1 0 $03 ($23) pinb7:0 pinb read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register allows access to the portb pins indep endent of the setting of the data direction bit ddbn. the port pin can be read throug h the pinbn register bit, and writing a logic one to pinbn toggles the value of p ortbn. ? bit 7:0 ? pinb7:0 - port b input pins value 208 8266c-mcu wireless-08/11 ATMEGA128RFA1 14.4.7 portd ? port d data register bit 7 6 5 4 3 2 1 0 $0b ($2b) portd7:0 portd read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 if portdn is written logic one when the portd pin n is configured as an input pin, the pull-up resistor is activated. to switch the pull-u p resistor off, portdn has to be written logic zero or the pin has to be configured as an ou tput pin. if portdn is written logic one when the pin is configured as an output pin, th e port pin is driven high (one). if portdn is written logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). ? bit 7:0 ? portd7:0 - port d data register value 14.4.8 ddrd ? port d data direction register bit 7 6 5 4 3 2 1 0 $0a ($2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the dddn bit in the ddrd register selects the direc tion of the portd pin n. if dddn is written logic one, pdn is configured as an outpu t pin. if dddn is written logic zero, pdn is configured as an input pin. ? bit 7:0 ? ddd7:0 - port d data direction register v alue 14.4.9 pind ? port d input pins address bit 7 6 5 4 3 2 1 0 $09 ($29) pind7:0 pind read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register allows access to the portd pins indep endent of the setting of the data direction bit dddn. the port pin can be read throug h the pindn register bit, and writing a logic one to pindn toggles the value of p ortdn. ? bit 7:0 ? pind7:0 - port d input pins value 14.4.10 porte ? port e data register bit 7 6 5 4 3 2 1 0 $0e ($2e) porte7:0 porte read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 209 8266c-mcu wireless-08/11 ATMEGA128RFA1 if porten is written logic one when the porte pin n is configured as an input pin, the pull-up resistor is activated. to switch the pull-u p resistor off, porten has to be written logic zero or the pin has to be configured as an ou tput pin. if porten is written logic one when the pin is configured as an output pin, th e port pin is driven high (one). if porten is written logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). ? bit 7:0 ? porte7:0 - port e data register value 14.4.11 ddre ? port e data direction register bit 7 6 5 4 3 2 1 0 $0d ($2d) dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the dden bit in the ddre register selects the direc tion of the porte pin n. if dden is written logic one, pen is configured as an outpu t pin. if dden is written logic zero, pen is configured as an input pin. ? bit 7:0 ? dde7:0 - port e data direction register v alue 14.4.12 pine ? port e input pins address bit 7 6 5 4 3 2 1 0 $0c ($2c) pine7:0 pine read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register allows access to the porte pins indep endent of the setting of the data direction bit dden. the port pin can be read throug h the pinen register bit, and writing a logic one to pinen toggles the value of p orten. ? bit 7:0 ? pine7:0 - port e input pins value 14.4.13 portf ? port f data register bit 7 6 5 4 3 2 1 0 $11 ($31) portf7:0 portf read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 if portfn is written logic one when the portf pin n is configured as an input pin, the pull-up resistor is activated. to switch the pull-u p resistor off, portfn has to be written logic zero or the pin has to be configured as an ou tput pin. if portfn is written logic one when the pin is configured as an output pin, th e port pin is driven high (one). if portfn is written logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). ? bit 7:0 ? portf7:0 - port f data register value 210 8266c-mcu wireless-08/11 ATMEGA128RFA1 14.4.14 ddrf ? port f data direction register bit 7 6 5 4 3 2 1 0 $10 ($30) ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ddfn bit in the ddrf register selects the direc tion of the portf pin n. if ddfn is written logic one, pfn is configured as an output p in. if ddfn is written logic zero, pfn is configured as an input pin. ? bit 7:0 ? ddf7:0 - port f data direction register v alue 14.4.15 pinf ? port f input pins address bit 7 6 5 4 3 2 1 0 $0f ($2f) pinf7:0 pinf read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register allows access to the portf pins indep endent of the setting of the data direction bit ddfn. the port pin can be read throug h the pinfn register bit, and writing a logic one to pinfn toggles the value of portfn. ? bit 7:0 ? pinf7:0 - port f input pins value 14.4.16 portg ? port g data register bit 7 6 5 4 3 2 1 0 $14 ($34) res1 res0 portg5 portg4 portg3 portg2 portg1 portg0 portg read/write r r rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 if portgn is written logic one when the portg pin n is configured as an input pin, the pull-up resistor is activated. to switch the pull-u p resistor off, portgn has to be written logic zero or the pin has to be configured as an ou tput pin. if portgn is written logic one when the pin is configured as an output pin, th e port pin is driven high (one). if portgn is written logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5:0 ? portg5:0 - port g data register value 211 8266c-mcu wireless-08/11 ATMEGA128RFA1 14.4.17 ddrg ? port g data direction register bit 7 6 5 4 3 2 1 0 $13 ($33) res1 res0 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/write r r rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ddgn bit in the ddrg register selects the direc tion of the portg pin n. if ddgn is written logic one, pgn is configured as an outpu t pin. if ddgn is written logic zero, pgn is configured as an input pin. ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5:0 ? ddg5:0 - port g data direction register v alue 14.4.18 ping ? port g input pins address bit 7 6 5 4 3 2 1 0 $12 ($32) res1 res0 ping5 ping4 ping3 ping2 ping1 ping0 ping read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 this register allows access to the portg pins indep endent of the setting of the data direction bit ddgn. the port pin can be read throug h the pingn register bit, and writing a logic one to pingn toggles the value of p ortgn. ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5:0 ? ping5:0 - port g input pins value 212 8266c-mcu wireless-08/11 ATMEGA128RFA1 15 interrupts this section describes the specifics of the interru pt handling as performed in ATMEGA128RFA1. for a general explanation of the avr interrupt handling, refer to "reset and interrupt handling" on page 15 . 15.1 interrupt vectors in ATMEGA128RFA1 table 15-1 . reset and interrupt vectors vector no. program address (2) source interrupt definition 0 $0000 (1) reset external pin, power-on reset, brown-out reset, watchdog reset, and jtag avr reset 1 $0002 int0 external interrupt request 0 2 $0004 int1 external interrupt request 1 3 $0006 int2 external interrupt request 2 4 $0008 int3 external interrupt request 3 5 $000a int4 external interrupt request 4 6 $000c int5 external interrupt request 5 7 $000e int6 external interrupt request 6 8 $0010 int7 external interrupt request 7 9 $0012 pcint0 pin change interrupt request 0 10 $0014 pcint1 pin change interrupt request 1 11 $0016 (3) pcint2 pin change interrupt request 2 12 $0018 wdt watchdog time-out interrupt 13 $001a timer2_compa timer/counter2 compare matc h a 14 $001c timer2_compb timer/counter2 compare matc h b 15 $001e timer2_ovf timer/counter2 overflow 16 $0020 timer1_capt timer/counter1 capture event 17 $0022 timer1_compa timer/counter1 compare matc h a 18 $0024 timer1_compb timer/counter1 compare matc h b 19 $0026 timer1_compc timer/counter1 compare matc h c 20 $0028 timer1_ovf timer/counter1 overflow 21 $002a timer0_compa timer/counter0 compare matc h a 22 $002c timer0_compb timer/counter0 compare matc h b 23 $002e timer0_ovf timer/counter0 overflow 24 $0030 spi_stc spi serial transfer complete 25 $0032 usart0_rx usart0 rx complete 26 $0034 usart0_udre usart0 data register empty 27 $0036 usart0_tx usart0 tx complete 28 $0038 analog_comp analog comparator 213 8266c-mcu wireless-08/11 ATMEGA128RFA1 vector no. program address (2) source interrupt definition 29 $003a adc adc conversion complete 30 $003c ee_ready eeprom ready 31 $003e timer3_capt timer/counter3 capture event 32 $0040 timer3_compa timer/counter3 compare match a 33 $0042 timer3_compb timer/counter3 compare match b 34 $0044 timer3_compc timer/counter3 compare match c 35 $0046 timer3_ovf timer/counter3 overflow 36 $0048 usart1_rx usart1 rx complete 37 $004a usart1_udre usart1 data register empty 38 $004c usart1_tx usart1 tx complete 39 $004e twi 2-wire serial interface 40 $0050 spm_ready store program memory ready 41 $0052 (3) timer4_capt timer/counter4 capture event 42 $0054 timer4_compa timer/counter4 compare match a 43 $0056 timer4_compb timer/counter4 compare match b 44 $0058 timer4_compc timer/counter4 compare match c 45 $005a timer4_ovf timer/counter4 overflow 46 $005c (3) timer5_capt timer/counter5 capture event 47 $005e timer5_compa timer/counter5 compare match a 48 $0060 timer5_compb timer/counter5 compare match b 49 $0062 timer5_compc timer/counter5 compare match c 50 $0064 timer5_ovf timer/counter5 overflow 51 $0066 (3) reserved 52 $0068 (3) reserved 53 $006a (3) reserved 54 $006c (3) reserved 55 $006e (3) ) reserved 56 $0070 (3) reserved 57 $0072 trx24_pll_lock transceiver pll lock 58 $0074 trx24_pll_unlock transceiver pll unlock 59 $0076 trx24_rx_start transceiver receive start 60 $0078 trx24_rx_end transceiver receive end 61 $007a trx24_cca_ed_done transceiver ccaed meassu rement finished 62 $007c trx24_xah_ami transceiver frame address ma tch 63 $007e trx24_tx_end transceiver transmit end 64 $0080 trx24_awake transceiver wakeup finished 214 8266c-mcu wireless-08/11 ATMEGA128RFA1 vector no. program address (2) source interrupt definition 65 $0082 scnt_cmp1 symbol counter compare match 1 66 $0084 scnt_cmp 2 symbol counter compare match 2 67 $0086 scnt_cmp 3 symbol counter compare match 3 68 $0088 scnt_ovfl symbol counter overflow 69 $008a scnt_backoff symbol counter backoff slot c ounter 70 $008c aes_ready aes encryption ready 71 $008e bat_low batterie monitor allert note: 1. when the bootrst fuse is programmed, the d evice will jump to the boot loader address at reset, see "memory programming" on page 465 . 2. when the ivsel bit in mcucr is set, interrupt ve ctors will be moved to the start of the boot flash section. the address of each inte rrupt vector will then be the address in this table added to the start address of the boot flash section. 3. not usefull in ATMEGA128RFA1 due to limited pin count. 15.2 reset and interrupt vector placement table 15-2 below shows reset and interrupt vectors placement for th e various combinations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not use d, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. table 15-2. reset and interrupt vectors placement ( 1 ) bootrst ivsel reset address interrupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x00 02 note: 1. the boot reset address is shown in table 30-7 on page 462 through table 30-6 on page 461 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in ATMEGA128RFA1 is: address labels code comments 0x0000 jmp reset ;reset handler 0x0002 jmp int0 ;irq0 handler 0x0004 jmp int1 ;irq1 handler 0x0006 jmp int2 ;irq2 handler 0x0008 jmp int3 ;irq3 handler 0x000a jmp int4 ;irq4 handler 0x000c jmp int5 ;irq5 handler 0x000e jmp int6 ;irq6 handler 0x0010 jmp int7 ;irq7 handler 0x0012 jmp pcint0 ;pcint0 handler 0x0014 jmp pcint1 ;pcint1 handler 0x0016 jmp pcint2 ;pcint2 handler 215 8266c-mcu wireless-08/11 ATMEGA128RFA1 0x0018 jmp wdt ;watchdog timeout handler 0x001a jmp tim2_compa ;timer2 comparea handler 0x001c jmp tim2_compb ;timer2 compareb handler 0x001e jmp tim2_ovf ;timer2 overflow handler 0x0020 jmp tim1_capt ;timer1 capture handler 0x0022 jmp tim1_compa ;timer1 comparea handler 0x0024 jmp tim1_compb ;timer1 compareb handler 0x0026 jmp tim1_compc ;timer1 comparec handler 0x0028 jmp tim1_ovf ;timer1 overflow handler 0x002a jmp tim0_compa ;timer0 comparea handler 0x002c jmp tim0_compb ;timer0 compareb handler 0x002e jmp tim0_ovf ;timer0 overflow handler 0x0030 jmp spi_stc ;spi transfer complete handler 0x0032 jmp usart0_rx ;usart0 rx complete handler 0x0034 jmp usart0_udre ;usart0,udr empty handler 0x0036 jmp usart0_tx ;usart0 tx complete handler 0x0038 jmp ana_comp ;analog comparator handler 0x003a jmp adc ;adc conversion complete handler 0x003c jmp ee_rdy ;eeprom ready handler 0x003e jmp tim3_capt ;timer3 capture handler 0x0040 jmp tim3_compa ;timer3 comparea handler 0x0042 jmp tim3_compb ;timer3 compareb handler 0x0044 jmp tim3_compc ;timer3 comparec handler 0x0046 jmp tim3_ovf ;timer3 overflow handler 0x0048 jmp usart1_rx ;usart1 rx complete handler 0x004a jmp usart1_udre ;usart1,udr empty handler 0x004c jmp usart1_tx ;usart1 tx complete handler 0x004e jmp twi ;2-wire serial handler 0x0050 jmp spm_rdy ;spm ready handler 0x0052 jmp tim4_capt ;timer4 capture handler 0x0054 jmp tim4_compa ;timer4 comparea handler 0x0056 jmp tim4_compb ;timer4 compareb handler 0x0058 jmp tim4_compc ;timer4 comparec handler 0x005a jmp tim4_ovf ;timer4 overflow handler 0x005c jmp tim5_capt ;timer5 capture handler 0x005e jmp tim5_compa ;timer5 comparea handler 0x0060 jmp tim5_compb ;timer5 compareb handler 0x0062 jmp tim5_compc ;timer5 comparec handler 0x0064 jmp tim5_ovf ;timer5 overflow handler 0x0066 jmp 0x15e ;0x15e <__bad_interrupt> 0x0068 jmp 0x15e ;0x15e <__bad_interrupt> 0x006a jmp 0x15e ;0x15e <__bad_interrupt> 0x006c jmp 0x15e ;0x15e <__bad_interrupt> 0x006e jmp 0x15e ;0x15e <__bad_interrupt> 0x0070 jmp 0x15e ;0x15e <__bad_interrupt> 0x0072 jmp trx24_pll_lock ;transceiver pll lock handler 0x0074 jmp trx24_pll_unlock ;transceiver pll unlock handler 0x0076 jmp trx24_rx_start ;transceiver rx start handler 0x0078 jmp trx24_rx_end ;transceiver rx end handler 0x007a jmp trx24_cca_ed_done ;transceiver ccaed done handler 0x007c jmp trx24_xah_ami ;transceiver addr. match handler 0x007e jmp trx24_tx_end ;transceiver transmit end handler 0x0080 jmp trx24_awake ;transceiver wake up handler 0x0082 jmp scnt_cmp1 ;symbol counter compare match 1 0x0084 jmp scnt_cmp2 ;symbol counter compare match 2 0x0086 jmp scnt_cmp3 ;symbol counter compare match 3 0x0088 jmp scnt_ovfl ;symbol counter overflow handler 0x008a jmp scnt_backoff ;symbol backoff slot counter h. 216 8266c-mcu wireless-08/11 ATMEGA128RFA1 0x008c jmp aes_ready ;encryption/decryption ready h. 0x008e jmp bat_low ;batterie monitor alert handler ; 0x0090 reset: ldi r16, high(ramend) ;main program start 0x0091 out sph,r16 ;set stack pointer to top of ram 0x0092 ldi r16, low(ramend) 0x0093 out spl,r16 0x0094 sei ;enable interrupts 0x0095 217 8266c-mcu wireless-08/11 ATMEGA128RFA1 0xf073 out sph,r16 ;set stack pointer to top of ram 0xf074 ldi r16,low(ramend) 0xf075 out spl,r16 0xf076 sei ;enable interrupts 0xfo77 219 8266c-mcu wireless-08/11 ATMEGA128RFA1 16 external interrupts the external interrupts are triggered by the int7:0 pin or any of the pcint8:0 pins. observe that if enabled, the interrupts will trigge r even if the int7:0 or pcint8:0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the pin change interrupt pci0 will trigger if any e nabled pcint7:0 pin toggles, pin change interrupt pci1 if the enabled pcint8 toggles . pcint23:9 have no function inside the ATMEGA128RFA1. their corresponding i/o p ort are not implemented. pcmsk1 and pcmsk0 registers control which pins cont ribute to the pin change interrupts. pci2 and pcmsk2 associated to pcint23:1 6 have no task in this design. pin change interrupts on pcint8:0 are detected asyn chronously. this implies that these interrupts can be used for waking the part al so from sleep modes other than idle mode. the external interrupts can be triggered by a falli ng or rising edge or a low level. this is set up as indicated in the specification for the ex ternal interrupt control registers ? eicra (int3:0) and eicrb (int7:4). when the externa l interrupt is enabled and is configured as level triggered, the interrupt will t rigger as long as the pin is held low. note that recognition of falling or rising edge int errupts on int7:4 requires the presence of an i/o clock, described in "overview" on page 3 . low level interrupts and the edge interrupt on int3:0 are detected asynchronously. th is implies that these interrupts can be used for waking the part also from sleep modes o ther than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used fo r wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be genera ted. the start-up time is defined by the sut and cksel fuses as described in "clock sources" on page 149 . 16.1 pin change interrupt timing an example of timing of a pin change interrupt is s hown in figure 16-1 below . figure 16-1. normal pin change interrupt clk pcint(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag pcif pcint(0) pin_sync pcint_syn pin_lat d q le pcint_setflag pcif clk clk pcint(0) in pcmsk(x) pcint_in_(0) 0 x 220 8266c-mcu wireless-08/11 ATMEGA128RFA1 16.2 register description 16.2.1 eicra ? external interrupt control register a bit 7 6 5 4 3 2 1 0 na ($69) isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eic ra read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk i s set. the level and edges on the external pins that activate the interrupts are defi ned in the following tables. edges on int3:0 are registered asynchronously. pulses on int 3:0 pins wider than the minimum pulse width of typical 50 ns will generate an inter rupt. shorter pulses are not guaranteed to generate an interrupt. if low level i nterrupt is selected, the low level must be held until the completion of the currently execu ting instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. when changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing it s interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finall y, the intn interrupt flag should be cleared by writing a logical one to its interrupt f lag bit (intfn) in the eifr register before the interrupt is re-enabled. when changing t he iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable b it in the eimsk register. otherwise an interrupt can occur when the bits are changed. ? bit 7:6 ? isc31:30 - external interrupt 3 sense con trol bit table 16-127 isc3 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc31:30 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 5:4 ? isc21:20 - external interrupt 2 sense con trol bit table 16-128 isc2 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc21:20 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 3:2 ? isc11:10 - external interrupt 1 sense con trol bit 221 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 16-129 isc1 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc11:10 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 1:0 ? isc01:00 - external interrupt 0 sense con trol bit table 16-130 isc0 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc01:00 0x03 the rising edge of intn generates asynchronously an interrupt request. 16.2.2 eicrb ? external interrupt control register b bit 7 6 5 4 3 2 1 0 na ($6a) isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eic rb read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the external interrupts 7 - 4 are activated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk i s set. the level and edges on the external pins that activate the interrupts are defi ned in the following tables. edges on int7:4 are registered asynchronously. pulses on int 7:4 pins wider than the minimum pulse width of typical 50 ns will generate an inter rupt. shorter pulses are not guaranteed to generate an interrupt. if low level i nterrupt is selected, the low level must be held until the completion of the currently execu ting instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. when changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing it s interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finall y, the intn interrupt flag should be cleared by writing a logical one to its interrupt f lag bit (intfn) in the eifr register before the interrupt is re-enabled. when changing t he iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable b it in the eimsk register. otherwise an interrupt can occur when the bits are changed. ? bit 7:6 ? isc71:70 - external interrupt 7 sense con trol bit table 16-131 isc7 register bits register bits value description isc71:70 0x00 the low level of intn generates an in terrupt 222 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 5:4 ? isc61:60 - external interrupt 6 sense con trol bit table 16-132 isc6 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc61:60 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 3:2 ? isc51:50 - external interrupt 5 sense con trol bit table 16-133 isc5 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc51:50 0x03 the rising edge of intn generates asynchronously an interrupt request. ? bit 1:0 ? isc41:40 - external interrupt 4 sense con trol bit table 16-134 isc4 register bits register bits value description 0x00 the low level of intn generates an interrupt request. 0x01 any edge of intn generates asynchronously an interrupt request. 0x02 the falling edge of intn generates asynchronously an interrupt request. isc41:40 0x03 the rising edge of intn generates asynchronously an interrupt request. 223 8266c-mcu wireless-08/11 ATMEGA128RFA1 16.2.3 eimsk ? external interrupt mask register bit 7 6 5 4 3 2 1 0 $1d ($3d) int7 int6 int5 int4 int3 int2 int1 int0 eimsk read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 when an int7:0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ei cra and eicrb define whether the external interrupt is activated on rising or fallin g edge or level sensed. activity on any of these pins will trigger an interrupt request even i f the pin is enabled as an output. this provides a way of generating a software interrupt. ? bit 7:0 ? int7:0 - external interrupt request enabl e table 16-135 int register bits register bits value description 0x00 all external pin interrupts are disabled. int7:0 0xff all external pin interrupts are enabled. 16.2.4 eifr ? external interrupt flag register bit 7 6 5 4 3 2 1 0 $1c ($3c) intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 eif r read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 when an edge or logic change on the int7:0 pin trig gers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the cor responding interrupt enable bit int7:0 in eimsk are set (one), the mcu will jump to the interrupt vector. the flag is cleared when the interrupt routine is executed. alt ernatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int7:0 are configured as level interrupt. note that when entering sleep m ode with the int3:0 interrupts disabled, the input buffers on these pins will be d isabled. this may cause a logic change in internal signals which will set the intf3 :0 flags. see "digital input enable and sleep modes" for more information. ? bit 7:0 ? intf7:0 - external interrupt flag table 16-136 intf register bits register bits value description 0x00 no edge or logic change on int7:0 occurred. 0x01 a edge or logic change on int0 occurred and triggered an interrupt request. 0x02 ... intf7:0 0x80 a edge or logic change on int7 occurred and triggered an interrupt request. 224 8266c-mcu wireless-08/11 ATMEGA128RFA1 16.2.5 pcicr ? pin change interrupt control registe r bit 7 6 5 4 3 2 1 0 na ($68) res4 res3 res2 res1 res0 pcie2 pcie1 pcie0 pcicr read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? pcie2 - pin change interrupt enable 2 when the pcie2 bit is set (one) and the i-bit in th e status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on an y enabled pcint23:16 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci2 interrupt vector. pcint23:16 pins are enabled individually by the pcmsk2 register. note that the i/o ports corres ponding to pcint23:16 are not implemented. therefore pcie2 has no function in thi s device. ? bit 1 ? pcie1 - pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in th e status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on an y enabled pcint15:8 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint15:8 pins are enabled individually by the pcmsk1 register. note that the i/o ports corres ponding to pcint15:9 are not implemented. ? bit 0 ? pcie0 - pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in th e status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on an y enabled pcint7:0 pin will cause an interrupt. the corresponding interrupt of pin ch ange interrupt request is executed from the pci0 interrupt vector. pcint7:0 pins are e nabled individually by the pcmsk0 register. 16.2.6 pcifr ? pin change interrupt flag register bit 7 6 5 4 3 2 1 0 $1b ($3b) res4 res3 res2 res1 res0 pcif2 pcif1 pcif0 pcifr read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? pcif2 - pin change interrupt flag 2 when a logic change on any pcint23:16 pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pci e2 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector . the flag is cleared when the interrupt routine is executed. alternatively, the f lag can be cleared by writing a logical one to it. note that the i/o ports corresponding to pcint23:16 are not implemented. therefore pcif2 has no function in this device. 225 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 1 ? pcif1 - pin change interrupt flag 1 when a logic change on any pcint15:8 pin triggers a n interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pci e1 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector . the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. note that the i/o ports corresponding to pcint15:9 are not implemented. ? bit 0 ? pcif0 - pin change interrupt flag 0 when a logic change on any pcint7:0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pci e0 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector . the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. 16.2.7 pcmsk2 ? pin change mask register 2 bit 7 6 5 4 na ($6d) pcint23 pcint22 pcint21 pcint20 pcmsk2 read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($6d) pcint19 pcint18 pcint17 pcint16 pcmsk2 read/write rw rw rw rw initial value 0 0 0 0 note that the pcmsk2 register has no function in th is device. the i/o ports associated to pcint23:16 are not implemented. normally each bi t pcint23:16 selects whether the pin change interrupt is enabled on the correspo nding i/o pin. if pcint23:16 is set and the pcie2 bit in pcicr is set, the pin change i nterrupt is enabled on the corresponding i/o pin. if pcint23:16 is cleared, th e pin change interrupt on the corresponding i/o pin is disabled. ? bit 7:0 ? pcint23:16 - pin change enable mask 16.2.8 pcmsk1 ? pin change mask register 1 bit 7 6 5 4 na ($6c) pcint15 pcint14 pcint13 pcint12 pcmsk1 read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($6c) pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write rw rw rw rw initial value 0 0 0 0 bit pcint8 selects whether the pin change interrupt is enabled on the corresponding i/o pin. if pcint8 is set and the pcie1 bit in pcic r is set, the pin change interrupt is enabled on the corresponding i/o pin. if pcint8 is cleared, the pin change interrupt on the corresponding i/o pin is disabled. 226 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 7:1 ? pcint15:9 - pin change enable mask bits 15:9 of the pcmsk1 register have no function i n this device. the i/o ports associated to pcint15:9 are not implemented. ? bit 0 ? pcint8 - pin change enable mask 8 if this bit is set to one the pin change interrupt on the corresponding i/o pin is enabled. if this bit is set to zero the pin change interrupt is disabled. 16.2.9 pcmsk0 ? pin change mask register 0 bit 7 6 5 4 3 2 1 0 na ($6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pc int0 pcmsk0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 each bit pcint7:0 selects whether the pin change in terrupt is enabled on the corresponding i/o pin. if pcint7:0 is set and the p cie0 bit in pcicr is set, the pin change interrupt is enabled on the corresponding i/ o pin. if pcint7:0 is cleared, the pin change interrupt on the corresponding i/o pin is di sabled. ? bit 7:0 ? pcint7:0 - pin change enable mask 227 8266c-mcu wireless-08/11 ATMEGA128RFA1 17 8-bit timer/counter0 with pwm 17.1 features ? two independent output compare units ? double buffered output compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (p wm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, a nd ocf0b) 17.2 overview timer/counter0 is a general purpose 8-bit timer/cou nter module with two independent output compare units and with pwm support. it allow s accurate program execution timing (event management) and wave generation. a simplified block diagram of the 8-bit timer/count er is shown in figure 17-1. for the actual placement of i/o pins refer to section "pin configurations" on page 2 . cpu accessible i/o registers, including i/o bits and i/ o pins, are shown in bold. the device- specific i/o register and bit locations are listed in the "register description" on page 239. figure 17-1. 8-bit timer/counter block diagram clock select timer/counter dat a bus ocrna ocrnb = = tcntn wav eform generation wav eform generation ocna ocnb = fixed top val ue control logic = 0 top bottom count clear direction tov n (int.req.) ocna(int.req.) ocnb(int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 228 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.2.1 registers the timer/counter (tcnt0) and output compare regist ers (ocr0a and ocr0b) are 8-bit registers. interrupt request signals (abbrevi ated to int.req. in the figure) are all visible in the timer interrupt flag register (tifr0 ). all interrupts are individually masked with the timer interrupt mask register (tims k0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrem ent) its value. the timer/counter is inactive when no clock source is selected. the o utput from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the resu lt of the compare can be used by the waveform generator to generate a pwm or variable fr equency output on the output compare pins (oc0a and oc0b); see "output compare unit" on page 229 for details. the compare match event will also set the compare f lag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 17.2.2 definitions many register and bit references in this section ar e written in general form. a lower case ? n ? replaces the timer/counter number (in this case 0 ). a lower case ? x ? replaces the output compare unit (in this case compare unit a or compare unit b). however when using the register or bit defines in a program, the precise form must be used i.e., tcnt0 for accessing timer/counter0 counter value an d so on. the definitions in table 17-1 are also used extensi vely throughout the document. table 17-1. definitions bottom the counter reaches the bottom when it becom es 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equ al to the highest value in the count sequence. the top value can be assigned t o be the fixed value 0xff (max) or the value stored in the ocr0a registe r. the assignment is dependent on the mode of operation. 17.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0b). for details on clock sources and prescaler see timer/counter 0, 1, 3, 4, and 5 prescaler on page 3 05 17.4 counter unit the main part of the 8-bit timer/counter is the pro grammable bi-directional counter unit. figure 17-2 shows a block diagram of the coun ter and its surroundings. 229 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 17-2. counter unit block diagram data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear signal description (internal signals): count increment or decrement tcnt0 by 1; direction select between increment and decrement; clear clear tcnt0 (set all bits to zero); clk tn timer/counter clock referred to as clk t0 in the following text; top signalize that tcnt0 has reached maximum value; bottom signalize that tcnt0 has reached minimum value (zer o); depending of the mode of operation used, the counte r is cleared, incremented or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. howe ver, the tcnt0 value can be accessed by the cpu regardless of whether clk t0 is present or not. a cpu write access overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr 0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). ther e are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc0a and oc0b. for more details abo ut advanced counting sequences and waveform generation, see "modes of operation" on page 233. the timer/counter overflow flag (tov0) is set accor ding to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 17.5 output compare unit the 8-bit comparator continuously compares tcnt0 wi th the output compare registers (ocr0a and ocr0b). the comparator signals a match whenever tcnt0 equals ocr0a or ocr0b. a match will set the output compare flag (ocf0a or ocf0b) at the next clock cycle of the timer. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the inte rrupt is executed. the flag can alternatively be software-cleared by writing a logi cal one to its i/o bit location. the waveform generator uses the match signal to generat e an output according to the operating mode set by the wgm02:0 bits and compare output mode (com0 x 1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes o f operation (refer to "modes of operation" on page 233). 230 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 17-3. output compare unit, block diagram ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom the ocr0 x registers are double buffered when using any of th e pulse width modulation (pwm) modes. for the normal and clear ti mer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr0 x compare registers to either top or bottom of the c ounting sequence. the synchronization prevents the occurren ce of odd-length, non-symmetrical pwm pulses and thereby making the output glitch-fre e. the ocr0 x register access may seem complex, but this is not the case. when the double buffering is enabled, the cpu has access to the ocr0 x buffer register. if double buffering is disabled the cpu will access th e ocr0 x directly. 17.5.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (foc0 x ) bit. forcing compare match will not set the ocf0 x flag or reload/clear the timer, but the oc0 x pin will be updated as if a real compare match had occurred (th e com0 x 1:0 bits settings define whether the oc0 x pin is set, cleared or toggled). 17.5.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0 x to be initialized to the same value as tcnt0 witho ut triggering an interrupt when the timer/counter clock is enabled. 17.5.3 using the output compare unit since writing tcnt0 in any mode of operation will b lock all compare matches for one timer clock cycle, there are risks involved when ch anging tcnt0 while using the output compare unit, independently of whether the timer/co unter is running or not. if the value written to tcnt0 equals the ocr0 x value, the compare match will be missed resulting in an incorrect waveform generation. simi larly, do not write the tcnt0 value equal to bottom when the counter is down-counting. the setup of the oc0 x should be performed before setting the data direct ion register for the port pin to output. the easiest way of sett ing the oc0 x value is to use the force output compare (foc0 x ) strobe bits in normal mode. the oc0 x registers keep their values even when changing between waveform generati on modes. 231 8266c-mcu wireless-08/11 ATMEGA128RFA1 be aware that the com0 x 1:0 bits are not double buffered together with the compare value. a change of the com0 x 1:0 bits will take effect immediately. 17.6 compare match output unit the compare output mode (com0 x 1:0) bits have two functions. the waveform generator uses the com0 x 1:0 bits for defining the output compare (oc0 x ) state at the next compare match. the com0x1:0 bits control also the oc0x pin output source. figure 17-4 shows a simplified schematic of the log ic affected by the com0 x 1:0 bit setting. the i/o registers, i/o bits and i/o pins i n the figure are shown in bold. only the parts of the general i/o port control registers (dd r and port) affected by the com0 x 1:0 bits are shown. when referring to the oc0 x state, the reference is to the internal oc0 x register and not to the oc0 x pin. the oc0 x register is reset to ?0? if a system reset occurs. figure 17-4. compare match output unit schematic port ddr d q d q ocnx pin ocnx d q waveform generator comnx1comnx0 0 1 data bus focn clk i/o the general i/o port function is overridden by the output compare (oc0 x ) from the waveform generator if either of the com0 x 1:0 bits are set. however the oc0 x pin direction (input or output) is still controlled by the data direction register (ddr) of the port pin. the data direction register bit of the oc 0 x pin (ddr_oc0 x ) must be set as output before the oc0 x value is visible at the pin. the port override fun ction is independent of the waveform generation mode. the design of the output compare pin logic allows i nitializing the oc0 x state before the output is enabled. note that some com0 x 1:0 bit settings are reserved for certain modes of operation (see "register description" on page 239). 17.6.1 compare output mode and waveform generation the waveform generator uses the com0 x 1:0 bits differently in normal, ctc and pwm modes. a setting of com0 x 1:0 = 0 tells the waveform generator in all modes t hat no action on the oc0 x register is to be performed on the next compare ma tch. for compare output actions in the non-pwm modes refer t o table 17-2. for fast pwm mode refer to table 17-3 and for phase correct pwm refer to table 17-4. 232 8266c-mcu wireless-08/11 ATMEGA128RFA1 a state change of the com0 x 1:0 bits will have effect at the first compare matc h after the bits are written. for non-pwm modes the action can be forced to have immediate effect by using the foc0 x strobe bits. the following table shows the com0 x 1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 17-2. compare output mode, non-pwm mode com0a1 com0b1 com0a0 com0b0 description 0 0 normal port operation, oc0 x disconnected; 0 1 toggle oc0 x on compare match; 1 0 clear oc0 x on compare match; 1 1 set oc0 x on compare match; table 17-3 shows the com0 x 1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. table 17-3. compare output mode, fast pwm mode com0a1 com0b1 com0a0 com0b0 description 0 0 normal port operation, oc0 x disconnected. 0 1 wgm02 = 0: normal port operation, oc0a disconnected . wgm02 = 1: toggle oc0a on compare match. oc0b: not applicable, reserved function; 1 0 clear oc0 x on compare match, set oc0 x at bottom, (non- inverting mode). 1 1 set oc0 x on compare match, clear oc0 x at bottom, (inverting mode). note: a special case occurs when ocr0 x equals top and com0 x 1 is set. in this case, the compare match is ignored, but the set or clear is d one at bottom. see "fast pwm mode" on page 234. table 17-4 shows the com0 x 1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. table 17-4. compare output mode, phase correct pwm mode com0a1 com0b1 com0a0 com0b0 description 0 0 normal port operation, oc0 x disconnected. 0 1 wgm02 = 0: normal port operation, oc0a disconnected . wgm02 = 1: toggle oc0a on compare match. oc0b: not applicable, reserved function; 1 0 clear oc0 x on compare match when up-counting. set oc0 x on compare match when down-counting. 1 1 set oc0 x on compare match when up-counting. clear oc0 x on compare match when down-counting. note: a special case occurs when ocr0 x equals top and com0 x 1 is set. in this case, the compare match is ignored, but the set or clear is d one at top. see "fast pwm mode" on page 234 for more details. 233 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.7 modes of operation the mode of operation i.e., the behavior of the tim er/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0 x 1:0) bits. the compare output mode bits do not affe ct the counting sequence while the waveform generation mode bits do. the com0 x 1:0 bits control whether the pwm output generated shoul d be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0 x 1:0 bits control whether the output should be set, cleared, or toggled at a comp are match (see "output compare unit" on page 229). for detailed timing information see "timer/counter timing diagrams" on page 237. table 17-5 shows the function of the wgm2:0 bits of registers tccr0a and tccr0b. these bits control the counting sequence of the cou nter, the source for maximum (top) counter value, and what type of waveform gene ration to be used. table 17-5. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (0,0) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4 1 0 0 reserved ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top notes: 1. max = 0xff 2. bottom = 0x00 17.7.1 normal mode the simplest mode of operation is the normal mode ( wgm02:0 = 0). in this mode the counting direction is always up (incrementing) and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operatio n the timer/counter overflow flag (tov0) will be set at the same timer clock cyc le when the tcnt0 becomes zero. the tov0 flag in this case behaves like a 9 th bit, except that it is only set and not cleared. however, the timer resolution can be incre ased by software utilizing the timer overflow interrupt that automatically clears the to v0 flag. there are no special cases to consider in the normal mode. a new counter value can be written at anytime. the output compare unit can be used to generate int errupts at some given time. it is not recommended to use the output compare for wavef orm generation in normal mode, since this will occupy too much cpu time. 17.7.2 clear timer on compare match (ctc) mode in clear timer on compare (ctc) mode (wgm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode t he counter is cleared to zero when the counter value (tcnt0) matches ocr0a. the ocr0a value defines the top value 234 8266c-mcu wireless-08/11 ATMEGA128RFA1 for the counter, hence also its resolution. this mo de allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in fig ure 17-5. the counter value (tcnt0) increases until a compare match occurs betw een tcnt0 and ocr0a. the counter (tcnt0) is then cleared. figure 17-5. ctc mode timing diagram tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can update the top value. however, changing top to a va lue close to bottom when the counter is running with no or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature . if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its m aximum value (0xff) and wrap around starting at 0x00 before the compare match ca n occur. for generating a waveform output in ctc mode, the o c0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction of the pin is set to output. the generated waveform will have a maximum frequency of f oc0 = f clki/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: ) 0 1( 2 / 0 x ocr n f f o clki x oc + ? ? = the n variable represents the prescaler factor (1, 8, 64, 256 or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter changes from max to 0x00. 17.7.3 fast pwm mode the fast pulse width modulation (pwm) mode (wgm02:0 = 3 or 7) provides a high frequency pwm waveform generation option. the fast pwm mode differs from the other pwm modes by its single-slope operation. the counter counts from bottom to top and then restarts from bottom. top is defined a s 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare out put mode the output compare (oc0 x ) is cleared on the compare match between tcnt0 and ocr0 x and set at bottom. in inverting compare output mode the output is set on compare match and cleared at bottom. due to the single-slop e operation, the operating frequency of the fast pwm mode can be twice as high as in the phase correct pwm mode that uses dual-slope operation. this high freq uency operation makes the fast 235 8266c-mcu wireless-08/11 ATMEGA128RFA1 pwm mode well suited for power regulation, rectific ation and dac applications. the high frequency allows physically small sized extern al components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 17-6. the tcnt0 value is shown in the timing diagram as a histogram illustrating the sing le-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0 x and tcnt0. figure 17-6. fast pwm mode timing diagram tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 the timer/counter overflow flag (tov0) is set each time the counter reaches top. the interrupt handler routine can be used for updat ing the compare value if the interrupt is enabled. in fast pwm mode the compare unit allows generating pwm waveforms on the oc0 x pins. setting the com0 x 1:0 bits to 2 will produce a non-inverted pwm. an i nverted pwm output can be generated by setting the com0 x 1:0 to 3. setting the com0a1:0 bits to 1 allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 17-3 on page 232). the actual oc0 x value will only be visible at the port pin if the data direction of the port pin is set to output. the pwm waveform is generated by setting (o r clearing) the oc0 x register at the compare match between ocr0 x and tcnt0, and by clearing (or setting) the oc0 x register at the timer clock cycle when the counter is cleared (changes from top to bottom). the pwm frequency for the output f oc0xpwm can be calculated with the following equation: 256 / 0 ? = n f f o clki xpwm oc the n variable represents the prescale factor (1, 8 , 64, 256 or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 ti mer clock cycle. setting the ocr0a 236 8266c-mcu wireless-08/11 ATMEGA128RFA1 equal to max will result in a constantly high or lo w output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency with 50% duty cycle waveform output in fast pwm mode can be achieved by setting oc0 x to toggle its logical level on each compare match (com0 x 1:0 = 1). the generated waveform will have a maximum frequency of f oc0xpwm = f clki/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except that in the fast pwm mode the double buffer feature of the outp ut compare unit is enabled. 17.7.4 phase correct pwm mode the phase correct pulse-width modulation (pwm) mode (wgm02:0 = 1 or 5) provides a phase-correct, high-resolution pwm waveform generat ion option. the phase correct pwm mode is based on a dual-slope operation. the co unter counts repeatedly from bottom to top and then from top to bottom. top is d efined as 0xff when wgm2:0 = 1 and top = ocr0a when wgm2:0 = 5. in non- inverting compare output mode, the output compare (oc0x) is cleared on the c ompare match between tcnt0 and ocr0 x while up-counting, and oc0 x is set on the compare match while down- counting. the operation is inverted in inverting ou tput compare mode. the dual-slope operation has a lower maximum operation frequency t han single-slope operation. however, due to the symmetric feature of the dual-s lope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremente d until the counter value matches top. the counter changes the direction when reachin g top. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown in figure 17-7 below . the tcnt0 value is shown in the timing diagram as a histogram illustrating the dual-slope operatio n. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0 x and tcnt0. figure 17-7. phase correct pwm mode timing diagram tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) ocrnx update the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. 237 8266c-mcu wireless-08/11 ATMEGA128RFA1 in phase correct pwm mode, the compare unit allows generating pwm waveforms on the oc0 x pins. setting the com0 x 1:0 bits to 2 will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0 x 1:0 to 3. setting the com0a0 bits to 1 allows the oc0a pin to toggle on c ompare matches if the wgm02 bit is set. this option is not available for the oc 0b pin (see table 17-4 on page 232). the actual oc0 x value will only be visible at the port pin if the data direction for the port pin is set to output. the pwm waveform is generated by clearing (or setting) the oc0 x register at the compare match between ocr0 x and tcnt0 when the counter increments, and by setting (or clearing) the oc0 x register at compare match between ocr0 x and tcnt0 when the counter decrements. the pwm fre quency for the output f oc0xpcpwm when using phase-correct pwm can be calculated wit h the following equation: 510 / 0 ? = n f f o clki xpcpwm oc the n variable represents the prescale factor (1, 8 , 64, 256 or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase-correct pwm mode . if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 17-7 oc nx has a transition from high to low even though there is no compare match. the reason of thi s transition is to guarantee symmetry around bottom. there are two cases that gi ve a transition without compare match: ? ocr0 x changes its value from max like in figure 17-7 on page 236. when the ocr0 x value is max the oc0 x pin value is the same as the result of a down- counting compare match. to ensure symmetry around b ottom the oc0 x value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr0 x . for that reason it misses the compare match and hence the oc 0 x change that would have happened on the way up. 17.8 timer/counter timing diagrams the timer/counter is a synchronous design and the t imer clock (clk t0 ) is therefore shown as a clock enable signal in the following fig ures. the figures include information on when interrupt flags are set. figure 17-8 contai ns timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 17-8. timer/counter timing diagram, no prescaling clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 238 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 17-9 shows the same timing data, but with th e prescaler enabled. figure 17-9. timer/counter timing diagram with prescaler (f clki/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) figure 17-10 shows the setting of ocf0b and ocf0a i n all modes except ctc and pwm mode, where ocr0a is top. figure 17-10. timer/counter timing diagram, setting of ocf0 x with prescaler (f clki/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) figure 17-11 shows the setting of ocf0a and the cle aring of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 17-11. timer/counter timing diagram, clear timer on compa re match mode with prescaler (f clki/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 239 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.9 register description 17.9.1 gtccr ? general timer/counter control regist er bit 7 6 5 4 3 2 1 0 $23 ($43) tsm res4 res3 res2 res1 res0 psrasy psrsync gtccr read/write rw r r r r r r rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? tsm - timer/counter synchronization mode writing the tsm bit to one activates the timer/coun ter synchronization mode. in this mode the value that is written to the psrasy and ps rsync bits is kept, hence keeping the corresponding prescaler reset signals a sserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during th e configuration. when the tsm bit is written to zero, the psrasy and psrsync bits are cl eared by hardware and the timer/counters simultaneously start counting. ? bit 6:2 ? res4:0 - reserved this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 1 ? psrasy - prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is writ ten when timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. ? bit 0 ? psrsync - prescaler reset for synchronous t imer/counters when this bit is one, the timer/counter0, timer/cou nter1, timer/counter3, timer/counter4 and timer/counter5 prescaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is s et. note that timer/counter0, timer/counter1, timer/counter3, timer/counter4 and timer/counter5 share the same prescaler and a reset of this prescaler will affect all timers. 17.9.2 tccr0a ? timer/counter0 control register a bit 7 6 5 4 3 2 1 0 $24 ($44) com0a1 com0a0 com0b1 com0b0 res1 res0 wgm01 wgm00 tccr0a read/write rw rw rw rw r r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com0a1:0 - compare match output a mode these bits control the output compare pin (oc0a) be havior. if one or both of the com0a1:0 bits are set, the oc0a output overrides th e normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the c om0a1:0 bits depends on the wgm02:0 bit setting. the following shows the com0a1 :0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-p wm). for the functionality in other modes refer to section "operating modes". 240 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 17-6 com0a register bits register bits value description 0 normal port operation, oc0a disconnected 1 toggle oc0a on compare match 2 clear oc0a on compare match com0a1:0 3 set oc0a on compare match ? bit 5:4 ? com0b1:0 - compare match output b mode these bits control the output compare pin (oc0b) be havior. if one or both of the com0b1:0 bits are set, the oc0b output overrides th e normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the c om0b1:0 bits depends on the wgm02:0 bit setting. the following shows the com0b1 :0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-p wm). for the functionality in other modes refer to section "operating modes". table 17-7 com0b register bits register bits value description 0 normal port operation, oc0b disconnected 1 toggle oc0b on compare match 2 clear oc0b on compare match com0b1:0 3 set oc0b on compare match ? bit 3:2 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 1:0 ? wgm01:00 - waveform generation mode combined with the wgm02 bit found in the tccr0b reg ister, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used accordi ng to the following table. modes of operation supported by the timer/counter0 unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section "modes of operation" for d etails). table 17-8 wgm0 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, top=0xff 0x2 ctc, top = ocra 0x3 fast pwm, top=0xff 0x4 reserved 0x5 pwm, phase correct, top = ocra 0x6 reserved wgm01:00 0x7 fast pwm, top=ocra 241 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.9.3 tccr0b ? timer/counter0 control register b bit 7 6 5 4 3 2 1 0 $25 ($45) foc0a foc0b res1 res0 wgm02 cs02 cs01 cs00 tccr0b read/write w w r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc0a - force output compare a the foc0a bit is only active when the wgm02:0 bits specify a non-pwm mode. however, for ensuring compatibility with future dev ices, this bit must be set to zero when tccr0b is written in a pwm operation mode. whe n writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1: 0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the for ced compare. a foc0a strobe will not generate any interrupt nor will it clear the ti mer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b - force output compare b the foc0b bit is only active when the wgm02:0 bits specify a non-pwm mode. however, for ensuring compatibility with future dev ices, this bit must be set to zero when tccr0b is written in a pwm operation mode. whe n writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1: 0 bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the for ced compare. a foc0b strobe will not generate any interrupt nor will it clear the ti mer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bit 5:4 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? wgm02 - combined with the wgm01:0 bit found in the tccr0a r egister, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section "modes of operation"). ? bit 2:0 ? cs02:00 - clock select the three clock select bits select the clock source to be used by the timer/counter0 according to the following table.if external pin mo des are used for timer/counter0, transitions on the t0 pin will clock the counter ev en if the pin is configured as an output. this feature allows software control of the countin g. table 17-9 cs0 register bits register bits value description 0x00 no clock source (timer/counter0 stopped) 0x01 clk_io/1 (no prescaling) 0x02 clk_io/8 (from prescaler) cs02:00 0x03 clk_io/64 (from prescaler) 242 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x04 clk_io/256 (from prescaler) 0x05 clk_io/1024 (from prescaler) 0x06 external clock source on t0 pin, clock on falling edge 0x07 external clock source on t0 pin, clock on rising edge 17.9.4 tcnt0 ? timer/counter0 register bit 7 6 5 4 $26 ($46) tcnt0_7 tcnt0_6 tcnt0_5 tcnt0_4 tcnt0 read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 $26 ($46) tcnt0_3 tcnt0_2 tcnt0_1 tcnt0_0 tcnt0 read/write rw rw rw rw initial value 0 0 0 0 the timer/counter register gives direct access, bot h for read and write operations, to the timer/counter0 unit 8-bit counter. writing to t he tcnt0 register blocks (removes) the compare match on the following timer clock. mod ifying the counter (tcnt0) while the counter is running, introduces a risk of missin g a compare match between tcnt0 and the ocr0x registers. ? bit 7:0 ? tcnt0_7:0 - timer/counter0 byte 17.9.5 ocr0a ? timer/counter0 output compare regist er bit 7 6 5 4 $27 ($47) ocr0a_7 ocr0a_6 ocr0a_5 ocr0a_4 ocr0a read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 $27 ($47) ocr0a_3 ocr0a_2 ocr0a_1 ocr0a_0 ocr0a read/write rw rw rw rw initial value 0 0 0 0 the output compare register a contains an 8-bit val ue that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. ? bit 7:0 ? ocr0a_7:0 - output compare register 243 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.9.6 ocr0b ? timer/counter0 output compare regist er b bit 7 6 5 4 $28 ($48) ocr0b_7 ocr0b_6 ocr0b_5 ocr0b_4 ocr0b read/write rw rw rw rw initial value 0 0 0 0 bit 3 2 1 0 $28 ($48) ocr0b_3 ocr0b_2 ocr0b_1 ocr0b_0 ocr0b read/write rw rw rw rw initial value 0 0 0 0 the output compare register b contains an 8-bit val ue that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. ? bit 7:0 ? ocr0b_7:0 - output compare register 17.9.7 timsk0 ? timer/counter0 interrupt mask regis ter bit 7 6 5 4 3 2 1 0 na ($6e) res4 res3 res2 res1 res0 ocie0b ocie0a toie0 timsk0 read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? ocie0b - timer/counter0 output compare matc h b interrupt enable when the ocie0b bit is written to one, and the i-bi t in the status register is set, the timer/counter0 compare match b interrupt is enabled . the corresponding interrupt is executed if a compare match in timer/counter0 occur s, i.e., when the ocf0b bit is set in the timer/counter0 interrupt flag register tifr0 . ? bit 1 ? ocie0a - timer/counter0 output compare matc h a interrupt enable when the ocie0a bit is written to one, and the i-bi t in the status register is set, the timer/counter0 compare match a interrupt is enabled . the corresponding interrupt is executed if a compare match in timer/counter0 occur s, i.e., when the ocf0a bit is set in the timer/counter0 interrupt flag register tifr0 . ? bit 0 ? toie0 - timer/counter0 overflow interrupt e nable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the c orresponding interrupt is executed if an overflow in timer/counter0 occurs i.e., when the tov0 bit is set in the timer/counter0 interrupt flag register tifr0. 244 8266c-mcu wireless-08/11 ATMEGA128RFA1 17.9.8 tifr0 ? timer/counter0 interrupt flag regist er bit 7 6 5 4 3 2 1 0 $15 ($35) res4 res3 res2 res1 res0 ocf0b ocf0a tov0 tifr0 read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? ocf0b - timer/counter0 output compare b mat ch flag the ocf0b bit is set when a compare match occurs be tween the timer/counter0 and the data in ocr0b output compare register. ocf0b is cleared by hardware when executing the corresponding interrupt handling vect or. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable) and ocf0b are set , the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a - timer/counter0 output compare a mat ch flag the ocf0a bit is set when a compare match occurs be tween the timer/counter0 and the data in ocr0a output compare register. ocf0a is cleared by hardware when executing the corresponding interrupt handling vect or. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter compare a match interrupt enable) and ocf0a are set , the timer/counter compare match interrupt is executed. ? bit 0 ? tov0 - timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in time r/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable) and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. 245 8266c-mcu wireless-08/11 ATMEGA128RFA1 18 16-bit timer/counter (timer/counter 1, 3, 4, and 5) 18.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? three independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceller ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (p wm) ? variable pwm period ? frequency generator ? external event counter ? numerous independent interrupt sources o tov1, ocf1a, ocf1b, ocf1c, icf1 o tov3, ocf3a, ocf3b, ocf3c, icf3 o tov4, ocf4a, ocf4b, ocf4c o tov5, ocf5a, ocf5b, ocf5c 18.2 overview the 16-bit timer/counter unit allows accurate progr am execution timing (event management), wave generation and signal timing meas urement. most register and bit references in this section ar e written in general form. a lower case ? n ? replaces the timer/counter number, and a lower ca se ? x ? replaces the output compare unit channel. however when using the regist er or bit defines in a program, the precise form must be used i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/coun ter is shown in figure 18-1. for the actual placement of i/o pins, see section "pin configurations" on page 2 . cpu accessible i/o registers, including i/o bits and i/ o pins are shown in bold. the device- specific i/o register and bit locations are listed in the section "register description" on page 267. the power reduction timer/counter1 bit, prtim1, in "prr0 ? power reduction register0" on page 169 must be written to zero to enable timer/counter1 m odule. the power reduction bits of timer/counter3 (prtim3) , timer/counter4 bit (prtim4) and timer/counter5 (prtim5) in "prr1 ? power reduction register 1" on page 169 must be written to zero to enable the respective ti mer/counter module. note, note the complete timer/counter i/o functiona lity is provided for each timer/counter module depending on the available i/o pins. 246 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-1. 16-bit timer/counter block diagram (1) clock select timer/counter data bus ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna(int.req.) ocnb(int.req.) icfn (int.req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn notes: 1. refer to figure 1-1 on page 2 , table 14-3 on page 195 and table 14-9 on page 199 for timer/counter1, 2 and 3 pin placements and des cription. 18.2.1 registers the timer/counter (tcnt n ) output compare registers (ocr n a/b/c) and input capture register (icr n ) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedur es are described in the section "accessing 16-bit registers" on page 247. the timer/counter control registers (tccr n a/b/c) are 8-bit registers and have no cpu access r estrictions. interrupt requests (shorten as int.req.) signals are all visi ble in the timer interrupt flag register (tifr n ). all interrupts are individually masked with the timer interrupt mask register (timsk n ). tifr n and timsk n are not shown in the figure since these registers are shared by other timer units. the timer/counter can be clocked internally, via th e prescaler or by an external clock source on the tn pin. the clock select logic block controls which clock source and which clock edge the timer/counter uses to incremen t (or decrement) its value. the timer/counter is inactive when no clock source is s elected. the output from the clock select logic is referred to as the timer clock (clk tn ). the double buffered output compare registers (ocr n a/b/c) are compared with the 247 8266c-mcu wireless-08/11 ATMEGA128RFA1 timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable fr equency output on the output compare pin (oc n a/b/c). see section "output compare units" on page 253 for details. the compare match event will also set the compare m atch flag (ocf n a/b/c) which can be used to generate an output compare interrupt request. the input capture register can capture the timer/co unter value at a given external (edge triggered) event on either the input capture pin (icp n ) or on the analog comparator pins (see "ac ? analog comparator" on page 408 ). the input capture unit includes a digital filtering unit (noise canceller) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr n a register, the icr n register or by a set of fixed values. when using ocr n a as top value in a pwm mode, the ocr n a register can not be used for generating a pwm output. however the top v alue will in this case be double buffered allowing the top value to be changed at ru n time. if a fixed top value is required, the icr n register can be used as an alternative, freeing th e ocr n a to be used as pwm output. 18.2.2 definitions the following definitions are used extensively thro ughout the document: table 18-1. definitions bottom the counter reaches the bottom when it becom es 0x0000. max the counter reaches its maximum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equ al to the highest value in the count sequence. the top value can be assigned t o be one of the fixed values: 0x00ff, 0x01ff, 0x03ff or to the value stor ed in the ocr n a or icr n register. the assignment is dependent of the mode o f operation. 18.3 accessing 16-bit registers the tcnt n , ocr n a/b/c and icr n are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a s ingle 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit tim er. accessing the low byte triggers the 16-bit read or write operation. when the low byte o f a 16-bit register is written by the cpu, the written low byte and the high byte stored in the temporary register are both copied into the 16-bit register in the same clock c ycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 1 6-bit register is copied into the temporary register in the same clock cycle as the l ow byte is read. not all 16-bit accesses use the temporary register for the high byte. reading the ocr n a/b/c 16-bit registers does not involve using the t emporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupt updates the temporary register. t he same principle can be used directly for accessing the ocr n a/b/c and icr n registers. note that when using the c- programming language, the compiler handles the 16-b it access. 248 8266c-mcu wireless-08/11 ATMEGA128RFA1 assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... notes: 1. see "about code examples" on page 8 . the assembly code example returns the tcnt n value in the r17:r16 register pair. it is important to notice that accessing 16-bit reg isters are atomic operations. if an interrupt occurs between the two instructions acces sing the 16-bit register and the interrupt code updates the temporary register by ac cessing the same or any other of the 16-bit timer registers, then the result of the acce ss outside the interrupt will be corrupted. therefore the main code must disable the interrupts during the 16-bit access when both the main code and the interrupt code upda te the temporary register. the following code examples show how to do an atomi c read of the tcnt n register contents. reading any of the ocr n a/b/c or icr n registers can be done by using the same principle. the assembly code example returns the tcnt n value in the r17:r16 register pair. assembly code examples (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret 249 8266c-mcu wireless-08/11 ATMEGA128RFA1 c code examples (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } notes: 1. see "about code examples" on page 8 . the following code examples show how to do an atomi c write of the tcnt n register contents. writing any of the ocr n a/b/c or icr n registers can be done by using the same principle. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcnt n . assembly code examples (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret 250 8266c-mcu wireless-08/11 ATMEGA128RFA1 c code examples (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } notes: 1. see "about code examples" on page 8 . 18.3.1 reusing the temporary high byte register if writing to more than one 16-bit register where t he high byte is the same for all registers written, then the high byte only needs to be written once. however note that the same rule of atomic operation described previou sly also applies in this case. 18.4 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs n 2:0) bits located in the timer/counter control regi ster b (tccr n b). for details on clock sources and prescaler, see "timer/counter 0, 1, 3, 4, and 5 prescaler" on page 305 . 18.5 counter unit the main part of the 16-bit timer/counter is the pr ogrammable 16-bit bi-directional counter unit. the following figure shows a block di agram of the counter and its surroundings. figure 18-2. counter unit block diagram temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn signal description (internal signals): count increment or decrement tcnt n by 1; direction select between increment and decrement; 251 8266c-mcu wireless-08/11 ATMEGA128RFA1 clear clear tcnt n (set all bits to zero); clk tn timer/counter clock; top signalize that tcnt n has reached maximum value; bottom signalize that tcnt n has reached minimum value (zero); the 16-bit counter is mapped into two 8-bit i/o mem ory locations: counter high (tcnt n h) contains the upper eight bits of the counter and counter low (tcnt n l) contains the lower eight bits. the tcnt n h register can only be indirectly accessed by the cpu. when the cpu does an access to the tcnt n h i/o location, the cpu accesses the high byte temporary register (temp). t he temporary register is updated with the tcnt n h value when the tcnt n l is read and tcnt n h is updated with the temporary register value when tcnt n l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cy cle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt n register giving unpredictable results when the counter is running. these special cases are described in the sections of their importance. depending on the mode of operation, the counter is cleared, incremented or decremented at each timer clock (clk tn ). the clk tn can be generated from an external or internal clock source selected by the clock select bits (cs n 2:0). the timer is stopped when no clock source is selected (cs n 2:0 = 0). however, the tcnt n value can be accessed by the cpu independent of whether clk tn is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the settings of the waveform generation mode bits (wgm n 3:0) located in the timer/counter control registers a and b (tccr n a and tccr n b). there are close connections between how the cou nter behaves (counts) and how waveforms are generated on the output compare outputs oc n x. for more details about advanced counting sequenc es and waveform generation, see "modes of operation" on page 257. the timer/counter overflow flag (tov n ) is set according to the mode of operation selected by the wgm n 3:0 bits. tov n can be used for generating a cpu interrupt. 18.6 input capture unit the timer/counter incorporates an input capture uni t that can capture external events and give them a time-stamp indicating time of occur rence. the external signal indicating an event, or multiple events, can be applied via th e icp n pin or alternatively, for the timer/counter1 only, via the analog comparator unit . the time-stamps can then be used to calculate frequency, duty-cycle and other f eatures of the signal applied. alternatively the time-stamps can be used for creat ing a log of the events. the input capture unit is illustrated by the block diagram shown in figure 18-3. the elements of the block diagram not direct parts of t he input capture unit are gray shaded. the small ?n? in register and bit names indicates t he timer/counter number. a capture will be triggered when a change of the lo gic level (an event) occurs on the input capture pin (icp n ), or alternatively on the analog comparator output (aco), and this change matches the setting of the edge detecto r. when a capture is triggered, the 16-bit value of the counter (tcnt n ) is written to the input capture register (icr n ). the input capture flag (icf n ) is set at the same system clock as the tcnt n value is copied into icr n register. if enabled (ticie n = 1), the input capture flag generates an input capture interrupt. the icf n flag is automatically cleared when the interrupt i s executed. alternatively the icf n flag can be software-cleared by writing a logical one to its i/o bit location. 252 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-3. input capture unit block diagram icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* note: 1. the analog comparator output (aco) can onl y trigger the timer/counter1 icp ? not timer/counter3, 4 or 5. reading the 16-bit value in the input capture regis ter (icr n ) is done by first reading the low byte (icr n l) and then the high byte (icr n h). when the low byte is read the high byte is copied into the high byte temporary re gister (temp). the cpu will access the temp register when reading the icr n h i/o location. the icr n register can only be written when using a waveform generation mode that utilizes the icr n register for defining the counter?s top value. in these cases the waveform generation mode (wgmn3:0) bits must be set before the top value can be written to the icr n register. when writing the icr n register the high byte must be written to the icr n h i/o location before the low byte is written to ic r n l. for more information on how to access the 16-bit re gisters refer to "accessing 16-bit registers" on page 247. 18.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp n ). timer/counter1 can alternatively use the analog com parator output as trigger source for the input capture unit. the analog comparator is se lected as trigger source by setting the analog comparator input capture (acic) bit in t he analog comparator control and status register (acsr). be aware that changing trig ger source can trigger a capture. the input capture flag must therefore be cleared af ter the change. both the input capture pin (icp n ) and the analog comparator output (aco) inputs are sampled using the same technique as for the t n pin ( figure 19-1 on page 305 ). the edge detector is also identical. however, when the noise canceller is enabled, additional logic is inserted before the edge detect or increasing the delay by four system 253 8266c-mcu wireless-08/11 ATMEGA128RFA1 clock cycles. note that the input of the noise canc eller and edge detector is always enabled unless the timer/counter is set in a wavefo rm generation mode that uses icr n to define top. an input capture can be software-triggered by contr olling the port of the icp n pin. 18.6.2 noise canceller the noise canceller improves noise immunity by usin g a simple digital filtering scheme. the noise canceller input is monitored over four sa mples and all four must be equal for changing the output that in turn is used by the edg e detector. the noise canceller is enabled by setting the input capture noise canceller (icnc n ) bit in timer/counter control register b (tccr n b). when enabled the noise canceller introduces additional four system clock cycles of d elay from a change applied to the input to the update of the icr n register. the noise canceller uses the system cloc k and is therefore not affected by the prescaler. 18.6.3 using the input capture unit the main challenge when using the input capture uni t is to assign enough processor capacity for handling the incoming events. the time between two events is critical. the icr n will be overwritten with a new value if the proces sor has not read the captured value in the icr n register before the next event occurs. in this cas e the result of the capture will be incorrect. when using the input capture interrupt, the icr n register should be read as early in the interrupt handler routine as possible. even tho ugh the input capture interrupt has relatively high priority, the maximum interrupt res ponse time is dependent on the maximum number of clock cycles it takes to handle a ny of the other interrupt requests. it is not recommended to use the input capture unit in any mode of operation where the top value (resolution) is actively changed while co unting. measurement of the duty cycle of an external signal requires that the trigger edge is changed after each capture. changing the edge sensi ng must be done as early as possible after the icr n register has been read. after a change of the edge , the input capture flag (icf n ) must be cleared by software (writing a logical on e to the i/o bit location). for measuring frequency only, the cleari ng of the icf n flag is not required (if an interrupt handler is used). 18.7 output compare units the 16-bit comparator continuously compares tcnt n with the output compare register (ocr nx ). if tcntn equals ocr nx the comparator signals a match. a match will set the output compare flag (ocf nx ) at the next clock cycle of the timer. if enabled (ocie nx = 1), the output compare flag generates an output compare interrupt. the ocf nx flag is automatically cleared when the interrupt i s executed. alternatively the ocf nx flag can be software-cleared by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to the waveform generation mode bits (wgm n 3:0) and compare output mode bits (com nx 1:0). the top and bottom signals are used by the wa veform generator for handling the special cases of the ext reme values in some modes of operation (see "modes of operation" on page 257). a special feature of output compare unit a allows i t to define the timer/counter top value i.e., the counter resolution. in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. 254 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-4 shows a block diagram of the output com pare unit. the small ? n ? in the register and bit names indicates the device number ( n = timer/counter n ), and the ? x ? indicates output compare unit a, b or c. the elemen ts of the block diagram not direct parts of the output compare unit are gray shaded. figure 18-4. output compare unit block diagram ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom the ocr nx register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear ti mer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr nx compare register to either top or bottom of the co unting sequence. the synchronization prevents the occurren ce of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr nx register access may seem complex, but this is not the case. when the double buffering is enabled, the cpu has access to the ocr nx buffer register. if double buffering is disabled the cpu will access th e ocr nx directly. the content of the ocr1 x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automat ically as the tcnt1 and icr1 register). therefore ocr1 x is not read via the high byte temporary register ( temp). however, it is a good practice to read the low byte first similar to accessing other 16-bit registers. writing the ocr nx registers must be done via the temp register since the compare of all 16 bits is done continuously. the hi gh byte (ocr nx h) has to be written first. the temp register will be updated with the v alue written by the cpu to the high byte i/o location. then when the low byte (ocr nx l) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr nx buffer or ocr nx compare register in the same system clock cycle. for more information of how to access the 16-bit re gisters refer to "accessing 16-bit registers" on page 247. 255 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.7.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (foc nx ) bit. forcing compare match will not set the ocf nx flag or reload/clear the timer, but the oc nx pin will be updated as if a real compare match had occurred (th e com n 1:0 bits settings define whether the oc nx pin is set, cleared or toggled). 18.7.2 compare match blocking by tcntn write all cpu writes to the tcnt n register will block any compare match that occurs in the next clock cycle of the timer even when the timer i s stopped. this feature allows ocr nx to be initialized to the same value as tcnt n without triggering an interrupt when the timer/counter clock is enabled. 18.7.3 using the output compare unit since writing tcnt n in any mode of operation will block all compare ma tches for one timer clock cycle, there are risks involved when ch anging tcnt n using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt n equals the ocr nx value, the compare match will be missed resulting in incorrect waveform generation. do not write the tcnt n equal to top in pwm modes with variable top values. the comp are match for the top will be ignored and the counter will continue to 0xffff. si milarly, do not write the tcnt n value equal to bottom when the counter is down-coun ting. the setup of the oc nx should be performed before setting the data direct ion register for the port pin to output. the easiest way of sett ing the oc nx value is to use the force output compare (foc nx ) strobe bits in normal mode. the oc nx register keeps its value even when changing between waveform generatio n modes. be aware that the com nx 1:0 bits are not double buffered together with the compare value. a change of the com nx 1:0 bits will immediately take effect. 18.8 compare match output unit the compare output mode (com nx 1:0) bits have two functions. the waveform generator uses the com nx 1:0 bits for defining the output compare (oc nx ) state at the next compare match. secondly the com nx 1:0 bits control the oc nx pin output source. figure 18-5 shows a simplified schematic of the log ic affected by the com nx 1:0 bit setting. the i/o registers, i/o bits and i/o pins i n the figure are shown in bold. only the parts of the general i/o port control registers (dd r and port) that are affected by the com nx 1:0 bits are shown. when referring to the oc nx state, the reference is to the internal oc nx register and not to the oc nx pin. after a system reset the oc nx register will have a value of ?0?. the general i/o port function is overridden by the output compare (oc nx ) from the waveform generator if either of the com nx 1:0 bits are set. however, the oc nx pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the o c nx pin (ddr_oc nx ) must be set as output before the oc nx value is visible on the pin. the port override fun ction is generally independent of the waveform generation mo de, but there are some exceptions. refer to table 18-2, table 18-3 and table 18-4 on page 257 for details. the design of the output compare pin logic allows i nitialization of the oc nx state before the output is enabled. note that some com nx 1:0 bit settings are reserved for certain modes of operation (see section "register description" on page 267). the com nx 1:0 bits have no effect on the input capture unit. 256 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-5. compare match output unit, schematic port ddr d q d q ocnx pin ocnx d q waveform generator comnx1comnx0 0 1 data bus focnx clk i/o 18.8.1 compare output mode and waveform generation the waveform generator uses the com nx 1:0 bits differently in normal, ctc and pwm modes. a setting of com nx 1:0 = 0 tells the waveform generator in all modes t hat no action on the oc nx register is to be performed on the next compare ma tch. for compare output actions in the non-pwm modes refer t o table 18-2. for fast pwm mode refer to table 18-3 and for phase-correct and phase-and-frequency-correct pwm refer to table 18-4. a change of the com nx 1:0 bits state will have effect at the first compar e match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc nx strobe bits. table 18-2 shows the com nx 1:0 bit functionality when the wgm n 3:0 bits are set to a normal or a ctc mode (non-pwm). table 18-2. compare output mode, non-pwm comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 0 0 normal port operation, oc n a/oc n b/oc n c disconnected. 0 1 toggle oc n a/oc n b/oc n c on compare match. 1 0 clear oc n a/oc n b/oc n c on compare match (set output to low level). 1 1 set oc n a/oc n b/oc n c on compare match (set output to high level). table 18-3 shows the com nx 1:0 bit functionality when the wgm n 3:0 bits are set to the fast pwm mode. 257 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 18-3. compare output mode, fast pwm comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 0 0 normal port operation, oc n a/oc n b/oc n c disconnected. 0 1 wgm13:0 = 14 or 15: toggle oc1a on compare match, o c1b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c dis connected. 1 0 clear oc n a/oc n b/oc n c on compare match; set oc n a/oc n b/oc n c at bottom (non-inverting mode). 1 1 set oc n a/oc n b/oc n c on compare match, clear oc n a/oc n b/oc n c at bottom (inverting mode). note: 1. a special case occurs when ocr n a/ocr n b/ocr n c equals top and com n a1/com n b1/com n c1 is set. in this case the compare match is ignore d, but the set or clear is done at bottom. see "fast pwm mode" on page 259 for more details. table 18-4 shows the com nx 1:0 bit functionality when the wgm n 3:0 bits are set to the phase correct and phase and frequency correct pwm m ode. table 18-4. compare output mode, phase correct and phase/frequ ency correct pwm comna1 comnb1 comnc1 comna0 comnb0 comnc0 description 0 0 normal port operation, oc n a/oc n b/oc n c disconnected. 0 1 wgm13:0 =9 or 11: toggle oc1a on compare match, oc1 b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c dis connected. 1 0 clear oc n a/oc n b/oc n c on compare match when up-counting. set oc n a/oc n b/oc n c on compare match when down-counting. 1 1 set oc n a/oc n b/oc n c on compare match when up-counting. clear oc n a/oc n b/oc n c on compare match when down-counting. note: 1. a special case occurs when ocr n a/ocr n b/ocr n c equals top and com n a1/com n b1/com n c1 is set. see "phase and frequency correct pwm mode" on page 263 for more details. 18.9 modes of operation the mode of operation i.e., the behavior of the tim er/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm n 3:0) and the compare output mode (com n x1:0) bits. the compare output mode bits do not affect the counting sequence, but the waveform gene ration mode bits do. the com nx 1:0 bits control whether the pwm output generated s hould be inverted or not (inverted or non-inverted pwm). for non-pwm modes t he com nx 1:0 bits control if the output should be set, cleared or toggle at a compar e match (see "compare match output unit" on page 255) 258 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 18-5. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0) (pwmn0) timer/counter mode of operation top update of ocrnx at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bott om 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bott om 3 0 0 1 1 pwm, phase correct, 10-bit 0x3ff top bott om 4 0 1 0 0 ctc ocr n a immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff bottom top 6 0 1 1 0 fast pwm, 9-bit 0x01ff bottom top 7 0 1 1 1 fast pwm, 10-bit 0x03ff bottom top 8 1 0 0 0 pwm, phase and frequency correct icr n bottom bottom 9 1 0 0 1 pwm, phase and frequency correct ocr n a bottom bottom 10 1 0 1 0 pwm, phase correct icr n top bottom 11 1 0 1 1 pwm, phase correct ocr n a top bottom 12 1 1 0 0 ctc icr n immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icr n bottom top 15 1 1 1 1 fast pwm ocr n a bottom top notes: 1. the ctc n and pwm n 1:0 bit definition names are obsolete. use the wgm n 2:0 definitions. however, the functionality and location of these bits are compatible with prev ious versions of the timer. for detailed timing information refer to "timer/counter timing diagrams" on page 265. 18.9.1 normal mode the simplest mode of operation is the normal mode ( wgm n 3:0 = 0). in this mode the counting direction is always up (incrementing) and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal o peration the timer/counter overflow flag (tov n ) will be set in the same timer clock cycle as the tcnt n becomes zero. in this case the tov n flag behaves like a 17 th bit, except that it is only set and not cleared. however the timer resolution can be increa sed by software when combined with the timer overflow interrupt that automaticall y clears the tov n flag. there are no special cases to consider in the normal mode. a new counter value can be written anytime. the input capture unit is easy to use in normal mod e. however it is important to note that the maximum interval between the external even ts must not exceed the resolution of the counter. the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit if the intervals be tween events are too long. the output compare units can be used to generate in terrupts at some given time. using the output compare to generate waveforms in n ormal mode is not recommended because this will occupy too much cpu t ime. 18.9.2 clear timer on compare match (ctc) mode in clear timer on compare (ctc) mode (wgm n 3:0 = 4 or 12), the ocr n a or icr n register are used to manipulate the counter resolut ion. in ctc mode the counter is 259 8266c-mcu wireless-08/11 ATMEGA128RFA1 cleared to zero when the counter value (tcnt n ) matches either the ocr n a (wgm n 3:0 = 4) or the icr n (wgm n 3:0 = 12). the ocr n a or icr n define the top value for the counter, hence also its resolution. this mode allow s greater control of the compare match output frequency. it also simplifies the oper ation of counting external events. the timing diagram for the ctc mode is shown in the following figure. the counter value (tcnt n ) increases until a compare match occurs with eithe r ocr n a or icr n , and then counter (tcnt n ) is cleared. figure 18-6. ctc mode timing diagram tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) each time the counter reaches the top value an inte rrupt can be generated by either the ocf n a or icf n flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bo ttom when the counter is running with no or a low prescaler value must be do ne with care since the ctc mode does not have the double buffering feature. the cou nter will miss the compare match if the new value written to ocr n a or icr n is lower than the current value of tcnt n . the counter will then have to count to its maximum valu e (0xffff) and wrap around starting at 0x0000 before the compare match can occ ur. in many cases this feature is not desirable. the fast pwm mode is available as an alternative using ocr n a for defining top (wgmn3:0 = 15). the ocr n a then will be double buffered. for generating a waveform output in ctc mode, the o c n a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com n a1:0 = 1). the oc n a value will not be visible on the port pin unless the data direction for the pin is set to output (dd r_oc n a = 1). the waveform generated will have a maximum frequency of f ocna = f clki/o /2 when ocr n a is set to zero (0x0000). the waveform frequency is given by the fo llowing equation: ) 1( 2 / ocrna n f f o clki ocna + ? ? = the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov n flag is set in the same clock cycle of the timer when the counter changes from max to 0x00 00. 18.9.3 fast pwm mode the fast pulse width modulation (pwm) mode (wgm n 3:0 = 5, 6, 7, 14 or 15) provides a high frequency pwm waveform generation option. th e fast pwm differs from the other pwm options by its single-slope operation. th e counter counts from bottom to top then restarts from bottom. in non-inverting com pare output mode, the output compare (oc nx ) is cleared on the compare match between tcnt n and ocr nx , and 260 8266c-mcu wireless-08/11 ATMEGA128RFA1 oc nx is set at bottom. in inverting compare output mode output is set on compare match and cleared at bottom. due to the single-slop e operation, the operating frequency of the fast pwm mode can be twice as high as the phase-correct and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regul ation, rectification and dac applications. high frequency allows physically smal l sized external components (coils, capacitors), hence reducing total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr n or ocr n a. the minimum resolution allowed is 2-bit (icr n or ocr n a set to 0x0003), and the maximum resolution is 16-bit (icr n or ocr n a set to max). the pwm resolution r fpwm in bits can be calculated with the following equat ion: )2 log( )1 log( + = top r fpwm in fast pwm mode the counter is incremented until t he counter value matches either one of the fixed values 0x00ff, 0x01ff or 0x03ff (w gm n 3:0 = 5, 6 or 7), the value in icr n (wgm n 3:0 = 14) or the value in ocr n a (wgm n 3:0 = 15). the counter is then cleared at the following timer clock cycle. the tim ing diagram for the fast pwm mode is shown in figure 18-7. the figure shows fast pwm mod e when ocr n a or icr n is used to define top. the tcnt n value is in the timing diagram shown as a histogra m for illustrating the single-slope operation. the diagra m includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt n slopes represent compare matches between ocr nx and tcnt n . the oc nx interrupt flag will be set when a compare match occurs. figure 18-7. fast pwm mode timing diagram tcntn ocrnx / top update and t ovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top ) 1 7 per iod 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) the timer/counter overflow flag (tov n ) is set each time the counter reaches top. in addition the oc n a or icf n flag is set at the same timer clock cycle as tov n is set when either ocr n a or icr n is used to define the top value. if one of the int errupts are enabled, the interrupt handler routine can be utili zed for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. a compare match will never occur between the tcnt n and the ocr nx if the top value is lower than any of the compare registers. note that when working with fixed top values the unused bits are masked to zero when any of the ocr nx registers are written. 261 8266c-mcu wireless-08/11 ATMEGA128RFA1 the procedure for updating icr n differs from updating ocr n a when used for defining the top value. the icr n register is not double buffered. this means that i f icr n is changed to a low value while the counter is running with no or a low prescaler value, there is a risk that the newly written icr n value is lower than the current value of tcnt n . in consequence the counter will miss the compare match at the top value. the counter must then count to the max value (0xfff f) and wrap around starting at 0x0000 before the compare match can occur. the ocr n a register is double buffered though. this feature allows writing the ocr n a i/o location at anytime. when the ocr n a i/o location is written the new value will be put first into the ocr n a buffer register. the ocr n a compare register will then be updated with the va lue in the buffer register at the next clock cycle of the time r when tcnt n matches top. the update is done at the same timer clock cycle as the tcnt n is cleared and the tov n flag is set. the definition of top with the icr n register works well for fixed top values. combined with icr n , the ocr n a register is free to be used for generating a pwm output on oc n a. however, if the base pwm frequency is actively c hanged (by modifying the top value), working with the ocr n a as top is clearly a better choice due to its double buffer feature. in fast pwm mode the compare units allow the genera tion of pwm waveforms on the oc nx pins. setting the com nx 1:0 bits to 2 will produce a non-inverted pwm and a n inverted pwm output can be generated by setting the com nx 1:0 to 3 (see table 18-3 on page 257). the actual oc nx value will only be visible on the port pin if the data direction of the port pin is set to output (ddr_oc nx ). the pwm waveform is generated by setting (or clearing) the oc nx register at the compare match between ocr nx and tcnt n , and by clearing (or setting) the oc nx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency of the output f ocnxpwm can be calculated with the following equation: ) 1( / top n f f o clki ocnxpwm + ? = the n variable represents the prescaler divider (1, 8, 64, 256 or 1024). the extreme values for the ocr nx register represent special cases when generating a pwm waveform output in the fast pwm mode. if the oc r nx is set equal to bottom (0x0000), the output will be a narrow spike for eac h top+1 timer clock cycle. setting the ocr nx equal to top will result in a constant high or low output (depending on the polarity of the output set by the com nx 1:0 bits.) a frequency (with 50% duty cycle) waveform output i n fast pwm mode can be achieved by setting oc n a to toggle its logical level on each compare match (com n a1:0 = 1). this applies only if ocr1a is used to define the to p value (wgm13:0 = 15). the waveform generated will have a maximum frequency of f ocna = f clki/o /2 when ocr n a is set to zero (0x0000). this feature is similar to th e oc n a toggle in ctc mode, except the double buffer feature of the output compare uni t is enabled in the fast pwm mode. 18.9.4 phase correct pwm mode the phase correct pulse width modulation (pwm) mode (wgm n 3:0 = 1, 2, 3, 10 or 11) provides a high resolution phase correct pwm wavefo rm generation option. the phase correct pwm mode is, like the phase and frequency c orrect pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compa re output mode, the output compare (oc nx ) is cleared on the compare match between tcnt n and ocr nx while 262 8266c-mcu wireless-08/11 ATMEGA128RFA1 up-counting, and set on the compare match while dow n-counting. in inverting output compare mode, the operation is inverted. the dual-s lope operation has a lower maximum operation frequency than single slope opera tion. however these modes are preferred for motor control applications due to the symmetric feature of the dual-slope pwm modes. the pwm resolution for the phase correct pwm mode c an be fixed to 8, 9 or 10 bit, or be defined by either icr n or ocr n a. the minimum resolution allowed is 2 bit (icr n or ocrna set to 0x0003), and the maximum resolution is 16-bit (icr n or ocr n a set to max). the pwm resolution r pcpwm in bits can be calculated with the following equat ion: )2 log( )1 log( + = top r pcpwm in phase correct pwm mode the counter is incremente d until the counter value matches either one of the fixed values 0x00ff, 0x01ff or 0x 03ff (wgm n 3:0 = 1, 2, or 3), the value in icr n (wgm n 3:0 = 10) or the value in ocr n a (wgm n 3:0 = 11). the counter has then reached the top and changes the count dire ction. the tcnt n value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 18-8 below . the figure shows phase correct pwm mode when ocr n a or icr n is used to define top. the tcnt n value is shown in the timing diagram as a histogram illustrating the dual-slope operation. the diagram includes non- inverted and inverted pwm outputs. the small horizo ntal line marks on the tcnt n slopes represent compare matches between ocr nx and tcnt n . the oc nx interrupt flag will be set when a compare match occurs. figure 18-8. phase correct pwm mode timing diagram ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) the timer/counter overflow flag (tov n ) is set each time the counter reaches bottom. when either ocr n a or icr n is used for defining the top value, the oc n a or icf n flag is set accordingly at the same timer clock cy cle as the ocr nx registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the 263 8266c-mcu wireless-08/11 ATMEGA128RFA1 tcnt n and the ocr nx . note that when working with fixed top values, the unused bits are masked to zero when any of the ocr nx registers are written. as the third period shown in figure 18-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an asymmetrical output. the reason for this can be found in the update time of the ocr nx register. since the ocr nx update occurs at top, the pwm period starts and ends at to p. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when thes e two values are not equal the two slopes of the period will differ in length. the difference in length gives the asymmetrical result of the output. it is recommended to use the phase and frequency co rrect mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no d ifferences between the two modes of operation. in phase correct pwm mode, the compare units allow generating pwm waveforms on the oc nx pins. setting the com nx 1:0 bits to 2 will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com nx 1:0 to 3 (see table 18-4 on page 257). the actual oc nx value will only be visible on the port pin if the data direction of the port pin is set to output (ddr_oc nx ). the pwm waveform is generated by setting (or clearing) the oc nx register at the compare match between ocr nx and tcnt n when the counter increments, and by clearing (or s etting) the oc nx register at compare match between ocr nx and tcnt n when the counter decrements. the pwm frequency of the output f ocnxpcpwm when using phase-correct pwm can be calculated with the following equation: ) 2 / top n f f o clki ocnxpcpwm ? ? = the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr nx register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr nx is set equal to bottom the output will be continuously low and if s et equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. if ocr1a is used to defi ne the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 18.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulat ion (pwm) mode (wgm n 3:0 = 8 or 9) provides a high resolution phase and frequenc y correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bo ttom. in non-inverting compare output mode, the output compare (oc nx ) is cleared on the compare match between tcnt n and ocr nx while up-counting, and set on the compare match wh ile down-counting. in inverting compare output mode, th e operation is inverted. the dual- slope operation gives a lower maximum operation fre quency compared to the single- slope operation. however these modes are preferred for motor control applications due to the symmetric feature of the dual-slope pwm mode s. the main difference between the phase correct and t he phase and frequency correct pwm mode is the time the ocr nx register is updated by the ocr nx buffer register, (see figure 18-8 on page 262 and figure 18-9 on page 264). 264 8266c-mcu wireless-08/11 ATMEGA128RFA1 the pwm resolution for the phase and frequency corr ect pwm mode can be defined by either icr n or ocr n a. the minimum resolution allowed is 2 bit (icr n or ocr n a set to 0x0003), and the maximum resolution is 16 bit (icr n or ocr n a set to max). the pwm resolution r pfcpwm in bits can be calculated with the following equat ion: )2 log( )1 log( + = top r pfcpwm in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr n (wgm n 3:0 = 8), or the value in ocr n a (wgm n 3:0 = 9). the counter has then reached top and chan ges the count direction. the tcnt n value will be equal to top for one timer clock cyc le. the timing diagram for the phase correct and frequency correct pwm mode is shown in figure 18-9 below . the figure shows phase and frequency correct pwm mo de when ocr n a or icr n is used to define top. the tcnt n value is shown in the timing diagram as a histogra m for illustrating the dual-slope operation. the diag ram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt n slopes represent compare matches between ocr nx and tcnt n . the oc nx interrupt flag will be set when a compare match occurs. figure 18-9. phase and frequency correct pwm mode timing diagra m ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) the timer/counter overflow flag (tov n ) is set at the timer clock cycle when the ocr nx registers are updated with the double-buffered val ue (at bottom). the oc n a or icf n flag is set after tcnt n has reached top when either ocr n a or icr n is used for defining the top value. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt n and the ocr nx . as figure 18-9 shows the output generated is, in co ntrast to the phase correct mode, symmetrical in all periods. since the ocr nx registers are updated at bottom, the length of the rising and the falling slopes will al ways be equal. this gives symmetrical output pulses and is therefore frequency correct. 265 8266c-mcu wireless-08/11 ATMEGA128RFA1 the definition of top with the icr n register works well when using fixed top values. combined with icr n the ocr n a register is available for generating a pwm output on oc n a. however, if the base pwm frequency is actively c hanged by modifying the top value, using the ocr n a as top is clearly a better choice due to its doub le buffer feature. in phase and frequency correct pwm mode, the compar e units allow generating pwm waveforms on the oc nx pins. setting the com nx 1:0 bits to 2 will produce a non- inverted pwm. an inverted pwm output can be generat ed by setting the com nx 1:0 to 3 (see table 18-4 on page 257). the actual oc nx value will only be visible at the port pin if the data direction of the port pin is set to output (ddr_oc nx ). the pwm waveform is generated by setting (or clearing) the oc nx register at the compare match between ocr nx and tcnt n when the counter increments, and by clearing (or s etting) the oc nx register at compare match between ocr nx and tcnt n when the counter decrements. the pwm frequency of the output f ocnxpfcpwm when using phase and frequency correct pwm can be calculated with the fo llowing equation: ) 2 / top n f f o clki ocnxpfcpwm ? ? = the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr nx register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr nx is set equal to bottom the output will be continuously low and if s et equal to top the output will be set to high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define t he top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50 % duty cycle. 18.10 timer/counter timing diagrams the timer/counter is a synchronous design and the t imer clock (clk tn ) is therefore shown as a clock enable signal in the following fig ures. the figures include information on when interrupt flags are set and when the ocr nx register is updated with the ocr nx buffer value (only for modes utilizing double buff ering). figure 18-10 shows a timing diagram for the setting of ocf nx . figure 18-10. timer/counter timing diagram, setting of ocf nx , no prescaling clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 266 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-11 shows the same timing data, but with t he prescaler enabled. figure 18-11. timer/counter timing diagram, setting of ocf nx with prescaler (f clki/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) figure 18-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocr nx register is updated at bottom. the timing diagrams will be the same, but top shoul d be replaced by bottom, top- 1 by bottom+1 and so on. the same renaming applies for modes that set the tov n flag at bottom. figure 18-12. timer/counter timing diagram, no prescaling tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o 267 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 18-13 shows the same timing data, but with t he prescaler enabled. figure 18-13. timer/counter timing diagram with prescaler (f clki/o /8) tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 18.11 register description 18.11.1 tccr1a ? timer/counter1 control register a bit 7 6 5 4 3 2 1 0 na ($80) com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 tccr1a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com1a1:0 - compare output mode for channe l a the com1a1:0 bits control the output compare behavi or of pin oc1a. if one or both of the com1a1:0 bits are written to one, the oc1a outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc1a pin mu st be set in order to enable the output driver. when the oc1a is connected to the pi n, the function of the com1a1:0 bits is dependent of the wgm13:0 bits setting. the following table shows the com1a1:0 bit functionality when the wgm13:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-6 com1a register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com1a1:0 3 set ocna/ocnb/ocnc on compare match (set output to high level). ? bit 5:4 ? com1b1:0 - compare output mode for channe l b 268 8266c-mcu wireless-08/11 ATMEGA128RFA1 the com1b1:0 bits control the output compare behavi or of pin oc1b. if one or both of the com1b1:0 bits are written to one, the oc1b outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc1b pin mu st be set in order to enable the output driver. when the oc1a is connected to the pi n, the function of the com1b1:0 bits is dependent of the wgm13:0 bits setting. the following table shows the com1b1:0 bit functionality when the wgm13:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-7 com1b register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com1b1:0 3 set ocna/ocnb/ocnc on compare match (set output to high level). ? bit 3:2 ? com1c1:0 - compare output mode for channe l c the com1c1:0 bits control the output compare behavi or of pin oc1c. if one or both of the com1c1:0 bits are written to one, the oc1c outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc1c pin mu st be set in order to enable the output driver. when the oc1a is connected to the pi n, the function of the com1c1:0 bits is dependent of the wgm13:0 bits setting. the following table shows the com1c1:0 bit functionality when the wgm13:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-8 com1c register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com1c1:0 3 set ocna/ocnb/ocnc on compare match (set output to high level). ? bit 1:0 ? wgm11:10 - waveform generation mode combined with the wgm13:2 bits found in the tccr1b register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". table 18-9 wgm1 register bits register bits value description 0x0 normal mode of operation wgm11:10 0x1 pwm, phase correct, 8-bit 269 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna 18.11.2 tccr1b ? timer/counter1 control register b bit 7 6 5 4 3 2 1 0 na ($81) icnc1 ices1 res wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write rw rw r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? icnc1 - input capture 1 noise canceller setting this bit (to one) activates the input captu re noise canceler. when the noise canceler is activated, the input from the input cap ture pin (icp1) is filtered. the filter function requires four successive equal valued samp les of the icp1 pin for changing its output. the input capture is therefore delayed by f our oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1 - input capture 1 edge select this bit selects which edge on the input capture pi n (icp1) that is used to trigger a capture event. when the ices1 bit is written to zer o, a falling (negative) edge is used as trigger. when the ices1 bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to t he ices1 setting, the counter value is copied into the input capture register (icr1). t he event will also set the input capture flag (icf1). this can be used to cause an i nput capture interrupt, if this interrupt is enabled. when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b r egister), the icp1 is disconnected and consequently the input capture fun ction is disabled. ? bit 5 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 4:3 ? wgm11:10 - waveform generation mode 270 8266c-mcu wireless-08/11 ATMEGA128RFA1 combined with the wgm11:0 bits found in the tccr1a register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". table 18-10 wgm1 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn wgm11:10 0xf fast pwm, top = ocrna ? bit 2:0 ? cs12:10 - clock select the three clock select bits select the clock source to be used by the timer/counter1 according to the following table. if external pin m odes are used for the timer/counter1, transitions on the t1 pin will clock the counter ev en if the pin is configured as an output. this feature allows software control of the countin g. table 18-11 cs1 register bits register bits value description 0x00 no clock source (timer/counter stopped) 0x01 clk_io/1 (no prescaling) 0x02 clk_io/8 (from prescaler) 0x03 clk_io/64 (from prescaler) 0x04 clk_io/256 (from prescaler) 0x05 clk_io/1024 (from prescaler) 0x06 external clock source on tn pin, clock on falling edge cs12:10 0x07 external clock source on tn pin, clock on rising edge 271 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.3 tccr1c ? timer/counter1 control register c bit 7 6 5 4 3 2 1 0 na ($82) foc1a foc1b foc1c res4 res3 res2 res1 res0 tccr1c read/write rw rw rw r r r r r initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc1a - force output compare for channel a the foc1a bit is only active when the wgm13:0 bits specify a non-pwm mode. when writing a logical one to the foc1a bit, an immediat e compare match is forced on the waveform generation unit. the oc1a output is change d according to its com1a1:0 bits setting. note that the foc1a bits are implemented a s strobes. therefore it is the value present in the com1a1:0 bits that determine the eff ect of the forced compare. a foc1a strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the fo c1a bits are always read as zero. ? bit 6 ? foc1b - force output compare for channel b the foc1b bit is only active when the wgm13:0 bits specify a non-pwm mode. when writing a logical one to the foc1b bit, an immediat e compare match is forced on the waveform generation unit. the oc1b output is change d according to its com1b1:0 bits setting. note that the foc1b bits are implemented a s strobes. therefore it is the value present in the com1b1:0 bits that determine the eff ect of the forced compare. a foc1b strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr1b as top. the fo c1b bits are always read as zero. ? bit 5 ? foc1c - force output compare for channel c the foc1c bit is only active when the wgm13:0 bits specify a non-pwm mode. when writing a logical one to the foc1c bit, an immediat e compare match is forced on the waveform generation unit. the oc1c output is change d according to its com1c1:0 bits setting. note that the foc1c bits are implemented a s strobes. therefore it is the value present in the com1c1:0 bits that determine the eff ect of the forced compare. a foc1c strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr1c as top. the fo c1c bits are always read as zero. ? bit 4:0 ? res4:0 - reserved these bits are reserved for future use. 18.11.4 tcnt1h ? timer/counter1 high byte bit 7 6 5 4 3 2 1 0 na ($85) tcnt1h7:0 tcnt1h read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt1h and tcn t1l, combined tcnt1) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 272 8266c-mcu wireless-08/11 ATMEGA128RFA1 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt1) while the counter is running introd uces a risk of missing a compare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt1h7:0 - timer/counter1 high byte 18.11.5 tcnt1l ? timer/counter1 low byte bit 7 6 5 4 3 2 1 0 na ($84) tcnt1l7:0 tcnt1l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt1h and tcn t1l, combined tcnt1) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt1) while the counter is running introd uces a risk of missing a compare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt1l7:0 - timer/counter1 low byte 18.11.6 ocr1ah ? timer/counter1 output compare regi ster a high byte bit 7 6 5 4 3 2 1 0 na ($89) ocr1ah7:0 ocr1ah read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1a pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1ah7:0 - timer/counter1 output compare register high byte 18.11.7 ocr1al ? timer/counter1 output compare regi ster a low byte bit 7 6 5 4 3 2 1 0 na ($88) ocr1al7:0 ocr1al read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 273 8266c-mcu wireless-08/11 ATMEGA128RFA1 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1a pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1al7:0 - timer/counter1 output compare register low byte 18.11.8 ocr1bh ? timer/counter1 output compare regi ster b high byte bit 7 6 5 4 3 2 1 0 na ($8b) ocr1bh7:0 ocr1bh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1b pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1bh7:0 - timer/counter1 output compare register high byte 18.11.9 ocr1bl ? timer/counter1 output compare regi ster b low byte bit 7 6 5 4 3 2 1 0 na ($8a) ocr1bl7:0 ocr1bl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1b pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1bl7:0 - timer/counter1 output compare register low byte 274 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.10 ocr1ch ? timer/counter1 output compare reg ister c high byte bit 7 6 5 4 3 2 1 0 na ($8d) ocr1ch7:0 ocr1ch read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1c pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1ch7:0 - timer/counter1 output compare register high byte 18.11.11 ocr1cl ? timer/counter1 output compare reg ister c low byte bit 7 6 5 4 3 2 1 0 na ($8c) ocr1cl7:0 ocr1cl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1c pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr1cl7:0 - timer/counter1 output compare register low byte 18.11.12 icr1h ? timer/counter1 input capture regis ter high byte bit 7 6 5 4 3 2 1 0 na ($87) icr1h7:0 icr1h read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the input capture register is updated with the coun ter (tcnt1) value each time an event occurs on the icp1 pin or on the analog compa rator output. the input capture register can be used for defining the counter top v alue. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously when the cpu accesses these registers, the access is per formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? icr1h7:0 - timer/counter1 input capture r egister high byte 275 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.13 icr1l ? timer/counter1 input capture regis ter low byte bit 7 6 5 4 3 2 1 0 na ($86) icr1l7:0 icr1l read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the input capture register is updated with the coun ter (tcnt1) value each time an event occurs on the icp1 pin or on the analog compa rator output. the input capture register can be used for defining the counter top v alue. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously when the cpu accesses these registers, the access is per formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? icr1l7:0 - timer/counter1 input capture r egister low byte 18.11.14 timsk1 ? timer/counter1 interrupt mask reg ister bit 7 6 5 4 3 2 1 0 na ($6f) res1 res0 icie1 res ocie1c ocie1b ocie1a toie1 tims k1 read/write r r rw r r r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icie1 - timer/counter1 input capture interr upt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector is executed when the icf1 flag, located in tifr1, is set. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocie1c - timer/counter1 output compare c ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compar e c match interrupt is enabled. the corresponding interrupt vector is executed when the ocf1c flag, located in tifr1, is set. ? bit 2 ? ocie1b - timer/counter1 output compare b ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compar e b match interrupt is enabled. the corresponding interrupt vector is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a - timer/counter1 output compare a ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compar e a match interrupt is enabled. 276 8266c-mcu wireless-08/11 ATMEGA128RFA1 the corresponding interrupt vector is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1 - timer/counter1 overflow interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow inte rrupt is enabled. the corresponding interrupt vector is executed when the tov1 flag, lo cated in tifr1, is set. 18.11.15 tifr1 ? timer/counter1 interrupt flag regi ster bit 7 6 5 4 3 2 1 0 $16 ($36) res1 res0 icf1 res ocf1c ocf1b ocf1a tov1 tifr1 read/write r r rw r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icf1 - timer/counter1 input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alterna tively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocf1c - timer/counter1 output compare c mat ch flag this flag is set in the timer clock cycle after the counter (tcnt1) value matches the output compare register c (ocr1c). note that a forc ed output compare (foc1c) strobe will not set the ocf1c flag. ocf1c is automa tically cleared when the output compare match c interrupt vector is executed. alter natively, ocf1c can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf1b - timer/counter1 output compare b mat ch flag this flag is set in the timer clock cycle after the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forc ed output compare (foc1b) strobe will not set the ocf1b flag. ocf1b is automa tically cleared when the output compare match b interrupt vector is executed. alter natively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a - timer/counter1 output compare a mat ch flag this flag is set in the timer clock cycle after the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forc ed output compare (foc1a) strobe will not set the ocf1a flag. ocf1a is automa tically cleared when the output compare match a interrupt vector is executed. alter natively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1 - timer/counter1 overflow flag the setting of this flag is dependent of the wgm13: 0 bits setting of the timer/counter1 control register. in normal and ctc modes, the tov1 flag is set when the timer 277 8266c-mcu wireless-08/11 ATMEGA128RFA1 overflows. tov1 is automatically cleared when the timer/counter1 overflow interrupt vector is executed. alternatively, tov1 can be clea red by writing a logic one to its bit location. 18.11.16 tccr3a ? timer/counter3 control register a bit 7 6 5 4 3 2 1 0 na ($90) com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 tccr3a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com3a1:0 - compare output mode for channe l a the com3a1:0 bits control the output compare behavi or of pin oc3a. if one or both of the com3a1:0 bits are written to one, the oc3a outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc3a pin mu st be set in order to enable the output driver. when the oc3a is connected to the pi n, the function of the com3a1:0 bits is dependent of the wgm33:0 bits setting. the following table shows the com3a1:0 bit functionality when the wgm33:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-12 com3a register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com3a1:0 3 set ocna/ocnb/ocnc on compare match (set output to high level). ? bit 5:4 ? com3b1:0 - compare output mode for channe l b the com3b1:0 bits control the output compare behavi or of pin oc3b. if one or both of the com3b1:0 bits are written to one, the oc3b outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc3b pin mu st be set in order to enable the output driver. when the oc3b is connected to the pi n, the function of the com3b1:0 bits is dependent of the wgm33:0 bits setting. the following table shows the com3b1:0 bit functionality when the wgm33:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-13 com3b register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com3b1:0 3 set ocna/ocnb/ocnc on compare match 278 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description (set output to high level). ? bit 3:2 ? com3c1:0 - compare output mode for channe l c the com3c1:0 bits control the output compare behavi or of pin oc3c. if one or both of the com3c1:0 bits are written to one, the oc3c outp ut overrides the normal port functionality of the i/o pin it is connected to. ho wever note that the data direction register (ddr) bit corresponding to the oc3c pin mu st be set in order to enable the output driver. when the oc3c is connected to the pi n, the function of the com3c1:0 bits is dependent of the wgm33:0 bits setting. the following table shows the com3c1:0 bit functionality when the wgm33:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-14 com3c register bits register bits value description 0 normal port operation, ocna/ocnb/ocnc disconnected. 1 toggle ocna/ocnb/ocnc on compare match. 2 clear ocna/ocnb/ocnc on compare match (set output to low level). com3c1:0 3 set ocna/ocnb/ocnc on compare match (set output to high level). ? bit 1:0 ? wgm31:30 - waveform generation mode combined with the wgm33:2 bits found in the tccr3b register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". table 18-15 wgm3 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna wgm31:30 0xd reserved 279 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna 18.11.17 tccr3b ? timer/counter3 control register b bit 7 6 5 4 3 2 1 0 na ($91) icnc3 ices3 res wgm33 wgm32 cs32 cs31 cs30 tccr3b read/write rw rw r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? icnc3 - input capture 3 noise canceller setting this bit (to one) activates the input captu re noise canceler. when the noise canceler is activated, the input from the input cap ture pin (icp3) is filtered. the filter function requires four successive equal valued samp les of the icp3 pin for changing its output. the input capture is therefore delayed by f our oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices3 - input capture 3 edge select this bit selects which edge on the input capture pi n (icp3) that is used to trigger a capture event. when the ices3 bit is written to zer o, a falling (negative) edge is used as trigger. when the ices3 bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to t he ices3 setting, the counter value is copied into the input capture register (icr3). t he event will also set the input capture flag (icf3). this can be used to cause an i nput capture interrupt, if this interrupt is enabled. when the icr3 is used as top value (see description of the wgm33:0 bits located in the tccr3a and the tccr3b r egister), the icp3 is disconnected and consequently the input capture fun ction is disabled. ? bit 5 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 4:3 ? wgm31:30 - waveform generation mode combined with the wgm31:0 bits found in the tccr3a register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". table 18-16 wgm3 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit wgm31:30 0x6 fast pwm, 9-bit 280 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna ? bit 2:0 ? cs32:30 - clock select the three clock select bits select the clock source to be used by the timer/counter3 according to the following table. if external pin m odes are used for the timer/counter3, transitions on the t3 pin will clock the counter ev en if the pin is configured as an output. this feature allows software control of the countin g. table 18-17 cs3 register bits register bits value description 0x00 no clock source (timer/counter stopped) 0x01 clk_io/1 (no prescaling) 0x02 clk_io/8 (from prescaler) 0x03 clk_io/64 (from prescaler) 0x04 clk_io/256 (from prescaler) 0x05 clk_io/1024 (from prescaler) 0x06 external clock source on tn pin, clock on falling edge cs32:30 0x07 external clock source on tn pin, clock on rising edge 18.11.18 tccr3c ? timer/counter3 control register c bit 7 6 5 4 3 2 1 0 na ($92) foc3a foc3b foc3c res4 res3 res2 res1 res0 tccr3c read/write rw rw rw r r r r r initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc3a - force output compare for channel a the foc3a bit is only active when the wgm33:0 bits specify a non-pwm mode. when writing a logical one to the foc3a bit, an immediat e compare match is forced on the waveform generation unit. the oc3a output is change d according to its com3a1:0 bits setting. note that the foc3a bits are implemented a s strobes. therefore it is the value present in the com3a1:0 bits that determine the eff ect of the forced compare. a foc3a strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr3a as top. the fo c3a bits are always read as zero. 281 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 6 ? foc3b - force output compare for channel b the foc3b bit is only active when the wgm33:0 bits specify a non-pwm mode. when writing a logical one to the foc3b bit, an immediat e compare match is forced on the waveform generation unit. the oc3b output is change d according to its com3b1:0 bits setting. note that the foc3b bits are implemented a s strobes. therefore it is the value present in the com3b1:0 bits that determine the eff ect of the forced compare. a foc3b strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr1b as top. the fo c3b bits are always read as zero. ? bit 5 ? foc3c - force output compare for channel c the foc3c bit is only active when the wgm33:0 bits specify a non-pwm mode. when writing a logical one to the foc3c bit, an immediat e compare match is forced on the waveform generation unit. the oc3c output is change d according to its com3c1:0 bits setting. note that the foc3c bits are implemented a s strobes. therefore it is the value present in the com3c1:0 bits that determine the eff ect of the forced compare. a foc3c strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr3c as top. the fo c3c bits are always read as zero. ? bit 4:0 ? res4:0 - reserved these bits are reserved for future use. 18.11.19 tcnt3h ? timer/counter3 high byte bit 7 6 5 4 3 2 1 0 na ($95) tcnt3h7:0 tcnt3h read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt3h and tcn t3l, combined tcnt3) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt3) while the counter is running introd uces a risk of missing a compare match between tcnt3 and one of the ocr3x registers. writing to the tcnt3 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt3h7:0 - timer/counter3 high byte 18.11.20 tcnt3l ? timer/counter3 low byte bit 7 6 5 4 3 2 1 0 na ($94) tcnt3l7:0 tcnt3l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 282 8266c-mcu wireless-08/11 ATMEGA128RFA1 the two timer/counter i/o locations (tcnt3h and tcn t3l, combined tcnt3) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt3) while the counter is running introd uces a risk of missing a compare match between tcnt3 and one of the ocr3x registers. writing to the tcnt3 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt3l7:0 - timer/counter3 low byte 18.11.21 ocr3ah ? timer/counter3 output compare reg ister a high byte bit 7 6 5 4 3 2 1 0 na ($99) ocr3ah7:0 ocr3ah read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3a pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3ah7:0 - timer/counter3 output compare register high byte 18.11.22 ocr3al ? timer/counter3 output compare reg ister a low byte bit 7 6 5 4 3 2 1 0 na ($98) ocr3al7:0 ocr3al read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3a pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3al7:0 - timer/counter3 output compare register low byte 283 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.23 ocr3bh ? timer/counter3 output compare reg ister b high byte bit 7 6 5 4 3 2 1 0 na ($9b) ocr3bh7:0 ocr3bh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3b pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3bh7:0 - timer/counter3 output compare register high byte 18.11.24 ocr3bl ? timer/counter3 output compare reg ister b low byte bit 7 6 5 4 3 2 1 0 na ($9a) ocr3bl7:0 ocr3bl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3b pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3bl7:0 - timer/counter3 output compare register low byte 18.11.25 ocr3ch ? timer/counter3 output compare reg ister c high byte bit 7 6 5 4 3 2 1 0 na ($9d) ocr3ch7:0 ocr3ch read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3c pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3ch7:0 - timer/counter3 output compare register high byte 284 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.26 ocr3cl ? timer/counter3 output compare reg ister c low byte bit 7 6 5 4 3 2 1 0 na ($9c) ocr3cl7:0 ocr3cl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc3c pin. the output compare registers are 16-bit in size. to ensure that both t he high and low bytes are written simultaneously when the cpu writes to these registe rs, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit registers" for details. ? bit 7:0 ? ocr3cl7:0 - timer/counter3 output compare register low byte 18.11.27 icr3h ? timer/counter3 input capture regis ter high byte bit 7 6 5 4 3 2 1 0 na ($97) icr3h7:0 icr3h read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the input capture register is updated with the coun ter (tcnt3) value each time an event occurs on the icp3 pin. the input capture reg ister can be used for defining the counter top value. the input capture register is 16 -bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary hi gh byte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? icr3h7:0 - timer/counter3 input capture r egister high byte 18.11.28 icr3l ? timer/counter3 input capture regis ter low byte bit 7 6 5 4 3 2 1 0 na ($96) icr3l7:0 icr3l read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the input capture register is updated with the coun ter (tcnt3) value each time an event occurs on the icp3 pin. the input capture reg ister can be used for defining the counter top value. the input capture register is 16 -bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary hi gh byte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? icr3l7:0 - timer/counter3 input capture r egister low byte 285 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.29 timsk3 ? timer/counter3 interrupt mask reg ister bit 7 6 5 4 3 2 1 0 na ($71) res1 res0 icie3 res ocie3c ocie3b ocie3a toie3 tims k3 read/write r r rw r r r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icie3 - timer/counter3 input capture interr upt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter3 input capture interrupt is enabled. the corresponding interrupt vector is executed when the icf3 flag, located in tifr3, is set. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocie3c - timer/counter3 output compare c ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter3 output compar e c match interrupt is enabled. the corresponding interrupt vector is executed when the ocf3c flag, located in tifr3, is set. ? bit 2 ? ocie3b - timer/counter3 output compare b ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter3 output compar e b match interrupt is enabled. the corresponding interrupt vector is executed when the ocf3b flag, located in tifr3, is set. ? bit 1 ? ocie3a - timer/counter3 output compare a ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter3 output compar e a match interrupt is enabled. the corresponding interrupt vector is executed when the ocf3a flag, located in tifr3, is set. ? bit 0 ? toie3 - timer/counter3 overflow interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter3 overflow inte rrupt is enabled. the corresponding interrupt vector is executed when the tov3 flag, lo cated in tifr3, is set. 18.11.30 tifr3 ? timer/counter3 interrupt flag regi ster bit 7 6 5 4 3 2 1 0 $18 ($38) res1 res0 icf3 res ocf3c ocf3b ocf3a tov3 tifr3 read/write r r rw r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit 286 8266c-mcu wireless-08/11 ATMEGA128RFA1 this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icf3 - timer/counter3 input capture flag this flag is set when a capture event occurs on the icp3 pin. when the input capture register (icr3) is set by the wgm33:0 to be used as the top value, the icf3 flag is set when the counter reaches the top value. icf3 is automatically cleared when the input capture interrupt vector is executed. alterna tively, icf3 can be cleared by writing a logic one to its bit location. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocf3c - timer/counter3 output compare c mat ch flag this flag is set in the timer clock cycle after the counter (tcnt3) value matches the output compare register c (ocr3c). note that a forc ed output compare (foc3c) strobe will not set the ocf3c flag. ocf3c is automa tically cleared when the output compare match c interrupt vector is executed. alter natively, ocf3c can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf3b - timer/counter3 output compare b mat ch flag this flag is set in the timer clock cycle after the counter (tcnt3) value matches the output compare register b (ocr3b). note that a forc ed output compare (foc3b) strobe will not set the ocf3b flag. ocf3b is automa tically cleared when the output compare match b interrupt vector is executed. alter natively, ocf3b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf3a - timer/counter3 output compare a mat ch flag this flag is set in the timer clock cycle after the counter (tcnt3) value matches the output compare register a (ocr3a). note that a forc ed output compare (foc3a) strobe will not set the ocf3a flag. ocf3a is automa tically cleared when the output compare match a interrupt vector is executed. alter natively, ocf3a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov3 - timer/counter3 overflow flag the setting of this flag is dependent of the wgm33: 0 bits setting of the timer/counter3 control register. in normal and ctc modes, the tov3 flag is set when the timer overflows. tov3 is automatically cleared when the timer/counter3 overflow interrupt vector is executed. alternatively, tov3 can be clea red by writing a logic one to its bit location. 18.11.31 tccr4a ? timer/counter4 control register a bit 7 6 5 4 3 2 1 0 na ($a0) com4a1 com4a0 com4b1 com4b0 com4c1 com4c0 wgm41 wgm40 tccr4a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com4a1:0 - compare output mode for channe l a the timer/counter4 has only limited functionality. therefore the com4a1:0 bits do not control the output compare behavior of any pin. the following table shows the 287 8266c-mcu wireless-08/11 ATMEGA128RFA1 com4a1:0 bit functionality when the wgm43:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-18 com4a register bits register bits value description 0 normal operation 1 reserved 2 reserved com4a1:0 3 reserved ? bit 5:4 ? com4b1:0 - compare output mode for channe l b the timer/counter4 has only limited functionality. therefore the com4b1:0 bits do not control the output compare behavior of any pin. the following table shows the com4b1:0 bit functionality when the wgm43:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-19 com4b register bits register bits value description 0 normal operation 1 reserved 2 reserved com4b1:0 3 reserved ? bit 3:2 ? com4c1:0 - compare output mode for channe l c the timer/counter4 has only limited functionality. therefore the com4c1:0 bits do not control the output compare behavior of any pin. the following table shows the com4c1:0 bit functionality when the wgm43:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-20 com4c register bits register bits value description 0 normal operation 1 reserved 2 reserved com4c1:0 3 reserved ? bit 1:0 ? wgm41:40 - waveform generation mode combined with the wgm43:2 bits found in the tccr4b register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". note that timer/counter4 has only limited functionality. it cannot be connected to any i/o pin. table 18-21 wgm4 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit wgm41:40 0x4 ctc, top = ocrna 288 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna 18.11.32 tccr4b ? timer/counter4 control register b bit 7 6 5 4 3 2 1 0 na ($a1) icnc4 ices4 res wgm43 wgm42 cs42 cs41 cs40 tccr4b read/write rw rw r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? icnc4 - input capture 4 noise canceller timer/counter4 has only limited functionality. it i s not connected to any input capture pin. therefore this bit has no meaningful function. ? bit 6 ? ices4 - input capture 4 edge select timer/counter4 has only limited functionality. it i s not connected to any input capture pin. therefore this bit has no meaningful function. ? bit 5 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 4:3 ? wgm41:40 - waveform generation mode combined with the wgm41:0 bits found in the tccr4a register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". note that timer/counter4 has only limited functionality. it cannot be connected to any i/o pin. table 18-22 wgm4 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit wgm41:40 0x3 pwm, phase correct, 10-bit 289 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna ? bit 2:0 ? cs42:40 - clock select the three clock select bits select the clock source to be used by the timer/counter4 according to the following table. external pin mode s cannot be used for the timer/counter4. table 18-23 cs4 register bits register bits value description 0x00 no clock source (timer/counter stopped) 0x01 clk_io/1 (no prescaling) 0x02 clk_io/8 (from prescaler) 0x03 clk_io/64 (from prescaler) 0x04 clk_io/256 (from prescaler) 0x05 clk_io/1024 (from prescaler) 0x06 reserved cs42:40 0x07 reserved 18.11.33 tccr4c ? timer/counter4 control register c bit 7 6 5 4 3 2 1 0 na ($a2) foc4a foc4b foc4c res4 res3 res2 res1 res0 tccr4c read/write rw rw rw r r r r r initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc4a - force output compare for channel a the foc4a bit is only active when the wgm43:0 bits specify a non-pwm mode. when writing a logical one to the foc4a bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter4 the match has no direct impact on any output pin. note that the foc4a bits are implemente d as strobes. therefore it is the value present in the com4a1:0 bits that determine t he effect of the forced compare. a foc4a strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on 290 8266c-mcu wireless-08/11 ATMEGA128RFA1 compare match (ctc) mode using ocr4a as top. the fo c4a bits are always read as zero. ? bit 6 ? foc4b - force output compare for channel b the foc4b bit is only active when the wgm43:0 bits specify a non-pwm mode. when writing a logical one to the foc4b bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter4 the match has no direct impact on any output pin. note that the foc4b bits are implemente d as strobes. therefore it is the value present in the com4b1:0 bits that determine t he effect of the forced compare. a foc4b strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr4b as top. the fo c4b bits are always read as zero. ? bit 5 ? foc4c - force output compare for channel c the foc4c bit is only active when the wgm43:0 bits specify a non-pwm mode. when writing a logical one to the foc4c bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter4 the match has no direct impact on any output pin. note that the foc4c bits are implemente d as strobes. therefore it is the value present in the com4c1:0 bits that determine t he effect of the forced compare. a foc4c strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr4c as top. the fo c4c bits are always read as zero. ? bit 4:0 ? res4:0 - reserved these bits are reserved for future use. 18.11.34 tcnt4h ? timer/counter4 high byte bit 7 6 5 4 3 2 1 0 na ($a5) tcnt4h7:0 tcnt4h read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt4h and tcn t4l, combined tcnt4) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt4) while the counter is running introd uces a risk of missing a compare match between tcnt4 and one of the ocr4x registers. writing to the tcnt4 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt4h7:0 - timer/counter4 high byte 18.11.35 tcnt4l ? timer/counter4 low byte bit 7 6 5 4 3 2 1 0 na ($a4) tcnt4l7:0 tcnt4l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 291 8266c-mcu wireless-08/11 ATMEGA128RFA1 the two timer/counter i/o locations (tcnt4h and tcn t4l, combined tcnt4) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt4) while the counter is running introd uces a risk of missing a compare match between tcnt4 and one of the ocr4x registers. writing to the tcnt4 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt4l7:0 - timer/counter4 low byte 18.11.36 ocr4ah ? timer/counter4 output compare reg ister a high byte bit 7 6 5 4 3 2 1 0 na ($a9) ocr4ah7:0 ocr4ah read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4ah7:0 - timer/counter4 output compare register high byte 18.11.37 ocr4al ? timer/counter4 output compare reg ister a low byte bit 7 6 5 4 3 2 1 0 na ($a8) ocr4al7:0 ocr4al read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4al7:0 - timer/counter4 output compare register low byte 292 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.38 ocr4bh ? timer/counter4 output compare reg ister b high byte bit 7 6 5 4 3 2 1 0 na ($ab) ocr4bh7:0 ocr4bh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4bh7:0 - timer/counter4 output compare register high byte 18.11.39 ocr4bl ? timer/counter4 output compare reg ister b low byte bit 7 6 5 4 3 2 1 0 na ($aa) ocr4bl7:0 ocr4bl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4bl7:0 - timer/counter4 output compare register low byte 18.11.40 ocr4ch ? timer/counter4 output compare reg ister c high byte bit 7 6 5 4 3 2 1 0 na ($ad) ocr4ch7:0 ocr4ch read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4ch7:0 - timer/counter4 output compare register high byte 293 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.41 ocr4cl ? timer/counter4 output compare reg ister c low byte bit 7 6 5 4 3 2 1 0 na ($ac) ocr4cl7:0 ocr4cl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt4). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr4cl7:0 - timer/counter4 output compare register low byte 18.11.42 icr4h ? timer/counter4 input capture regis ter high byte bit 7 6 5 4 3 2 1 0 na ($a7) icr4h7:0 icr4h read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the timer/counter4 has only limited functionality. it is not connected to any i/o pin. therefore the contents of this register is never up dated with the counter (tcnt4) value. the input capture register is 16-bit in size. to en sure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte regist er (temp). this temporary register is shared by all the other 16-bit registers. see se ction "accessing 16-bit registers" for details. ? bit 7:0 ? icr4h7:0 - timer/counter4 input capture r egister high byte 18.11.43 icr4l ? timer/counter4 input capture regis ter low byte bit 7 6 5 4 3 2 1 0 na ($a6) icr4l7:0 icr4l read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the timer/counter4 has only limited functionality. it is not connected to any i/o pin. therefore the contents of this register is never up dated with the counter (tcnt4) value. the input capture register is 16-bit in size. to en sure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte regist er (temp). this temporary register is shared by all the other 16-bit registers. see se ction "accessing 16-bit registers" for details. ? bit 7:0 ? icr4l7:0 - timer/counter4 input capture r egister low byte 294 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.44 timsk4 ? timer/counter4 interrupt mask reg ister bit 7 6 5 4 3 2 1 0 na ($72) res1 res0 icie4 res ocie4c ocie4b ocie4a toie4 tims k4 read/write r r rw r r r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icie4 - timer/counter4 input capture interr upt enable the timer/counter4 has only limited functionality. it does not have an input capture pin. therefore this bit has no useful meaning. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocie4c - timer/counter4 output compare c ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter4 output compar e c match interrupt is enabled. the corresponding interrupt vector is executed when the ocf4c flag, located in tifr4, is set. ? bit 2 ? ocie4b - timer/counter4 output compare b ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter4 output compar e b match interrupt is enabled. the corresponding interrupt vector is executed when the ocf4b flag, located in tifr4, is set. ? bit 1 ? ocie4a - timer/counter4 output compare a ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter4 output compar e a match interrupt is enabled. the corresponding interrupt vector is executed when the ocf4a flag, located in tifr4, is set. ? bit 0 ? toie4 - timer/counter4 overflow interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter4 overflow inte rrupt is enabled. the corresponding interrupt vector is executed when the tov4 flag, lo cated in tifr4, is set. 18.11.45 tifr4 ? timer/counter4 interrupt flag regi ster bit 7 6 5 4 3 2 1 0 $19 ($39) res1 res0 icf4 res ocf4c ocf4b ocf4a tov4 tifr4 read/write r r rw r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. 295 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 5 ? icf4 - timer/counter4 input capture flag the timer/counter4 has only limited functionality. it does not have an input capture pin. therefore this bit has no useful meaning. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocf4c - timer/counter4 output compare c mat ch flag this flag is set in the timer clock cycle after the counter (tcnt4) value matches the output compare register c (ocr4c). note that a forc ed output compare (foc4c) strobe will not set the ocf4c flag. ocf4c is automa tically cleared when the output compare match c interrupt vector is executed. alter natively, ocf4c can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf4b - timer/counter4 output compare b mat ch flag this flag is set in the timer clock cycle after the counter (tcnt4) value matches the output compare register b (ocr4b). note that a forc ed output compare (foc4b) strobe will not set the ocf4b flag. ocf4b is automa tically cleared when the output compare match b interrupt vector is executed. alter natively, ocf4b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf4a - timer/counter4 output compare a mat ch flag this flag is set in the timer clock cycle after the counter (tcnt4) value matches the output compare register a (ocr4a). note that a forc ed output compare (foc4a) strobe will not set the ocf4a flag. ocf4a is automa tically cleared when the output compare match a interrupt vector is executed. alter natively, ocf4a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov4 - timer/counter4 overflow flag the setting of this flag is dependent of the wgm43: 0 bits setting of the timer/counter4 control register. in normal and ctc modes, the tov4 flag is set when the timer overflows. tov4 is automatically cleared when the timer/counter4 overflow interrupt vector is executed. alternatively, tov4 can be clea red by writing a logic one to its bit location. 18.11.46 tccr5a ? timer/counter5 control register a bit 7 6 5 4 3 2 1 0 na ($120) com5a1 com5a0 com5b1 com5b0 com5c1 com5c0 wgm51 wgm50 tccr5a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com5a1:0 - compare output mode for channe l a the timer/counter5 has only limited functionality. therefore the com5a1:0 bits do not control the output compare behavior of any pin. the following table shows the com5a1:0 bit functionality when the wgm53:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-24 com5a register bits register bits value description com5a1:0 0 normal operation 296 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 1 reserved 2 reserved 3 reserved ? bit 5:4 ? com5b1:0 - compare output mode for channe l b the timer/counter5 has only limited functionality. therefore the com5b1:0 bits do not control the output compare behavior of any pin. the following table shows the com5b1:0 bit functionality when the wgm53:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-25 com5b register bits register bits value description 0 normal operation 1 reserved 2 reserved com5b1:0 3 reserved ? bit 3:2 ? com5c1:0 - compare output mode for channe l c the timer/counter5 has only limited functionality. therefore the com5c1:0 bits do not control the output compare behavior of any pin. the following table shows the com5c1:0 bit functionality when the wgm53:0 bits ar e set to a normal or a ctc mode (non-pwm). for the other functionality refer to sec tion "modes of operation". table 18-26 com5c register bits register bits value description 0 normal operation 1 reserved 2 reserved com5c1:0 3 reserved ? bit 1:0 ? wgm51:50 - waveform generation mode combined with the wgm53:2 bits found in the tccr5b register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". note that timer/counter5 has only limited functionality. it cannot be connected to any i/o pin. table 18-27 wgm5 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit 0x6 fast pwm, 9-bit wgm51:50 0x7 fast pwm, 10-bit 297 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna 18.11.47 tccr5b ? timer/counter5 control register b bit 7 6 5 4 3 2 1 0 na ($121) icnc5 ices5 res wgm53 wgm52 cs52 cs51 cs50 tccr5b read/write rw rw r rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? icnc5 - input capture 5 noise canceller timer/counter5 has only limited functionality. it i s not connected to any input capture pin. therefore this bit has no meaningful function. ? bit 6 ? ices5 - input capture 5 edge select timer/counter5 has only limited functionality. it i s not connected to any input capture pin. therefore this bit has no meaningful function. ? bit 5 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 4:3 ? wgm51:50 - waveform generation mode combined with the wgm51:0 bits found in the tccr5a register, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode (counter), clea r timer on compare match (ctc) mode, and three types of pulse width modulation (pw m) modes. for more information on the different modes see section "modes of operat ion". note that timer/counter5 has only limited functionality. it cannot be connected to any i/o pin. table 18-28 wgm5 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, 8-bit 0x2 pwm, phase correct, 9-bit 0x3 pwm, phase correct, 10-bit 0x4 ctc, top = ocrna 0x5 fast pwm, 8-bit wgm51:50 0x6 fast pwm, 9-bit 298 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x7 fast pwm, 10-bit 0x8 pwm, phase and frequency correct, top = icrn 0x9 pwm, phase and frequency correct, top = ocrna 0xa pwm, phase correct, top = icrn 0xb pwm, phase correct, top = ocrna 0xc ctc, top = ocrna 0xd reserved 0xe fast pwm, top = icrn 0xf fast pwm, top = ocrna ? bit 2:0 ? cs52:50 - clock select the three clock select bits select the clock source to be used by the timer/counter5 according to the following table. external pin mode s cannot be used for the timer/counter5. table 18-29 cs5 register bits register bits value description 0x00 no clock source (timer/counter stopped) 0x01 clk_io/1 (no prescaling) 0x02 clk_io/8 (from prescaler) 0x03 clk_io/64 (from prescaler) 0x04 clk_io/256 (from prescaler) 0x05 clk_io/1024 (from prescaler) 0x06 reserved cs52:50 0x07 reserved 18.11.48 tccr5c ? timer/counter5 control register c bit 7 6 5 4 3 2 1 0 na ($122) foc5a foc5b foc5c res4 res3 res2 res1 res0 tccr5c read/write rw rw rw r r r r r initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc5a - force output compare for channel a the foc5a bit is only active when the wgm53:0 bits specify a non-pwm mode. when writing a logical one to the foc5a bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter5 the match has no direct impact on any output pin. note that the foc5a bits are implemente d as strobes. therefore it is the value present in the com5a1:0 bits that determine t he effect of the forced compare. a foc5a strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr5a as top. the fo c5a bits are always read as zero. ? bit 6 ? foc5b - force output compare for channel b 299 8266c-mcu wireless-08/11 ATMEGA128RFA1 the foc5b bit is only active when the wgm53:0 bits specify a non-pwm mode. when writing a logical one to the foc5b bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter5 the match has no direct impact on any output pin. note that the foc5b bits are implemente d as strobes. therefore it is the value present in the com5b1:0 bits that determine t he effect of the forced compare. a foc5b strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr5b as top. the fo c5b bits are always read as zero. ? bit 5 ? foc5c - force output compare for channel c the foc5c bit is only active when the wgm53:0 bits specify a non-pwm mode. when writing a logical one to the foc5c bit, an immediat e compare match is forced. due to the limited functionality of the timer/counter5 the match has no direct impact on any output pin. note that the foc5c bits are implemente d as strobes. therefore it is the value present in the com5c1:0 bits that determine t he effect of the forced compare. a foc5c strobe will not generate any interrupt nor wi ll it clear the timer in clear timer on compare match (ctc) mode using ocr5c as top. the fo c5c bits are always read as zero. ? bit 4:0 ? res4:0 - reserved these bits are reserved for future use. 18.11.49 tcnt5h ? timer/counter5 high byte bit 7 6 5 4 3 2 1 0 na ($125) tcnt5h7:0 tcnt5h read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt5h and tcn t5l, combined tcnt5) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt5) while the counter is running introd uces a risk of missing a compare match between tcnt5 and one of the ocr5x registers. writing to the tcnt5 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt5h7:0 - timer/counter5 high byte 18.11.50 tcnt5l ? timer/counter5 low byte bit 7 6 5 4 3 2 1 0 na ($124) tcnt5l7:0 tcnt5l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the two timer/counter i/o locations (tcnt5h and tcn t5l, combined tcnt5) give direct access, both for read and for write operatio ns, to the timer/counter unit 16-bit 300 8266c-mcu wireless-08/11 ATMEGA128RFA1 counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access i s performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see section "accessing 16-bit reg isters" for details. modifying the counter (tcnt5) while the counter is running introd uces a risk of missing a compare match between tcnt5 and one of the ocr5x registers. writing to the tcnt5 register blocks (removes) the compare match on the following timer clock for all compare units. ? bit 7:0 ? tcnt5l7:0 - timer/counter5 low byte 18.11.51 ocr5ah ? timer/counter5 output compare reg ister a high byte bit 7 6 5 4 3 2 1 0 na ($129) ocr5ah7:0 ocr5ah read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5ah7:0 - timer/counter5 output compare register high byte 18.11.52 ocr5al ? timer/counter5 output compare reg ister a low byte bit 7 6 5 4 3 2 1 0 na ($128) ocr5al7:0 ocr5al read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5al7:0 - timer/counter5 output compare register low byte 18.11.53 ocr5bh ? timer/counter5 output compare reg ister b high byte bit 7 6 5 4 3 2 1 0 na ($12b) ocr5bh7:0 ocr5bh read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 301 8266c-mcu wireless-08/11 ATMEGA128RFA1 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5bh7:0 - timer/counter5 output compare register high byte 18.11.54 ocr5bl ? timer/counter5 output compare reg ister b low byte bit 7 6 5 4 3 2 1 0 na ($12a) ocr5bl7:0 ocr5bl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5bl7:0 - timer/counter5 output compare register low byte 18.11.55 ocr5ch ? timer/counter5 output compare reg ister c high byte bit 7 6 5 4 3 2 1 0 na ($12d) ocr5ch7:0 ocr5ch read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5ch7:0 - timer/counter5 output compare register high byte 302 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.56 ocr5cl ? timer/counter5 output compare reg ister c low byte bit 7 6 5 4 3 2 1 0 na ($12c) ocr5cl7:0 ocr5cl read/write r rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt5). a match can be used to generate an output compare interrupt. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the c pu writes to these registers, the access is performed using an 8-bit temporary high b yte register (temp). this temporary register is shared by all the other 16-bi t registers. see section "accessing 16- bit registers" for details. ? bit 7:0 ? ocr5cl7:0 - timer/counter5 output compare register low byte 18.11.57 icr5h ? timer/counter5 input capture regis ter high byte bit 7 6 5 4 3 2 1 0 na ($127) icr5h7:0 icr5h read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the timer/counter5 has only limited functionality. it is not connected to any i/o pin. therefore the contents of this register is never up dated with the counter (tcnt5) value. the input capture register is 16-bit in size. to en sure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte regist er (temp). this temporary register is shared by all the other 16-bit registers. see se ction "accessing 16-bit registers" for details. ? bit 7:0 ? icr5h7:0 - timer/counter5 input capture r egister high byte 18.11.58 icr5l ? timer/counter5 input capture regis ter low byte bit 7 6 5 4 3 2 1 0 na ($126) icr5l7:0 icr5l read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 the timer/counter5 has only limited functionality. it is not connected to any i/o pin. therefore the contents of this register is never up dated with the counter (tcnt5) value. the input capture register is 16-bit in size. to en sure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte regist er (temp). this temporary register is shared by all the other 16-bit registers. see se ction "accessing 16-bit registers" for details. ? bit 7:0 ? icr5l7:0 - timer/counter5 input capture r egister low byte 303 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.11.59 timsk5 ? timer/counter5 interrupt mask reg ister bit 7 6 5 4 3 2 1 0 na ($73) res1 res0 icie5 res ocie5c ocie5b ocie5a toie5 tims k5 read/write r r rw r r r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 5 ? icie5 - timer/counter5 input capture interr upt enable the timer/counter5 has only limited functionality. it does not have an input capture pin. therefore this bit has no useful meaning. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocie5c - timer/counter5 output compare c ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter5 output compar e c match interrupt is enabled. the corresponding interrupt vector is executed when the ocf5c flag, located in tifr5, is set. ? bit 2 ? ocie5b - timer/counter5 output compare b ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter5 output compar e b match interrupt is enabled. the corresponding interrupt vector is executed when the ocf5b flag, located in tifr5, is set. ? bit 1 ? ocie5a - timer/counter5 output compare a ma tch interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter5 output compar e a match interrupt is enabled. the corresponding interrupt vector is executed when the ocf5a flag, located in tifr5, is set. ? bit 0 ? toie5 - timer/counter5 overflow interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter5 overflow inte rrupt is enabled. the corresponding interrupt vector is executed when the tov5 flag, lo cated in tifr5, is set. 18.11.60 tifr5 ? timer/counter5 interrupt flag regi ster bit 7 6 5 4 3 2 1 0 $1a ($3a) res1 res0 icf5 res ocf5c ocf5b ocf5a tov5 tifr5 read/write r r rw r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? res1:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. 304 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 5 ? icf5 - timer/counter5 input capture flag the timer/counter5 has only limited functionality. it does not have an input capture pin. therefore this bit has no useful meaning. ? bit 4 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3 ? ocf5c - timer/counter5 output compare c mat ch flag this flag is set in the timer clock cycle after the counter (tcnt5) value matches the output compare register c (ocr5c). note that a forc ed output compare (foc5c) strobe will not set the ocf5c flag. ocf5c is automa tically cleared when the output compare match c interrupt vector is executed. alter natively, ocf5c can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf5b - timer/counter5 output compare b mat ch flag this flag is set in the timer clock cycle after the counter (tcnt5) value matches the output compare register b (ocr5b). note that a forc ed output compare (foc5b) strobe will not set the ocf5b flag. ocf5b is automa tically cleared when the output compare match b interrupt vector is executed. alter natively, ocf5b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf5a - timer/counter5 output compare a mat ch flag this flag is set in the timer clock cycle after the counter (tcnt5) value matches the output compare register a (ocr5a). note that a forc ed output compare (foc5a) strobe will not set the ocf5a flag. ocf5a is automa tically cleared when the output compare match a interrupt vector is executed. alter natively, ocf5a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov5 - timer/counter5 overflow flag the setting of this flag is dependent of the wgm53: 0 bits setting of the timer/counter5 control register. in normal and ctc modes, the tov5 flag is set when the timer overflows. tov5 is automatically cleared when the timer/counter5 overflow interrupt vector is executed. alternatively, tov5 can be clea red by writing a logic one to its bit location. 305 8266c-mcu wireless-08/11 ATMEGA128RFA1 19 timer/counter 0, 1, 3, 4, and 5 prescaler timer/counter 0, 1, 3, 4, and 5 share the same pres caler module, but the timer/counters can have different prescaler setting s. the description below applies to all timer/counters. t n is used as a general name, n = 0, 1, 3, 4, or 5. 19.1 internal clock source the timer/counter can be clocked directly by the sy stem clock (by setting the cs n 2:0 = 1). this provides the fastest operation with a maxi mum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively one of four taps from the prescaler can be used as a clock source. the presca led clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256 or f clk_i/o /1024. 19.2 prescaler reset the prescaler is free running, i.e., operates indep endently of the clock select logic of the timer/counter, and it is shared by the timer/co unter t n . since the prescaler is not affected by the timer/counter?s clock select, the s tate of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and cloc ked by the prescaler (6 > cs n 2:0 > 1). the number of system clock cycles from the mome nt the timer is enabled until the first count occurs can be from 1 to n+1 system cloc k cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synch ronizing the timer/counter to program execution. however care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset w ill affect the prescaler period for all connected timer/counters. 19.3 external clock source an external clock source applied to the t n pin can be used as timer/counter clock (clk tn ). the t n pin is sampled once every system clock cycle by th e pin synchronization logic. the synchronized (sampled) signal is then pa ssed through the edge detector. figure 19-1 shows a functional equivalent block dia gram of the t n synchronization and edge detector logic. the registers are clocked at t he positive edge of the internal system clock (clk i/o ). the latch is transparent in the high period of t he internal system clock. the edge detector generates one clk tn pulse for each positive (cs n 2:0 = 7) or negative (cs n 2:0 = 6) edge it detects. figure 19-1. tn/t0 pin sampling tn_sync (to clock select logic) edge detector synchronization d q d q le d q tn clk i/o the synchronization and edge detector logic introdu ces a delay of 2.5 to 3.5 system clock cycles from an edge applied to the t n pin to the counter being updated. 306 8266c-mcu wireless-08/11 ATMEGA128RFA1 enabling and disabling of the clock input must be d one when t n has been stable for at least one system clock cycle. otherwise there is a risk of generating a false timer/counter clock pulse. each half period of the applied, external clock mus t be longer than one system clock cycle to ensure correct sampling. the external cloc k must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum freque ncy of a detectable external clock is half the sampling frequency (nyquist sampl ing theorem). however due to variation of the system clock frequency and duty cy cle caused by oscillator source (crystal, resonator and capacitors) tolerances, it is recommended to limit the maximum frequency of an external clock source to less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 19-2. prescaler for synchronous timer/counters psr10 clear tn tn clk i/o synchronization synchronization timer/countern clock source clk tn timer/countern clock source clk tn csn0 csn1 csn2 csn0 csn1 csn2 19.4 register description 19.4.1 gtccr ? general timer/counter control regist er bit 7 6 5 4 3 2 1 0 $23 ($43) tsm res4 res3 res2 res1 res0 psrasy psrsync gtccr read/write rw r r r r r r rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? tsm - timer/counter synchronization mode writing the tsm bit to one activates the timer/coun ter synchronization mode. in this mode the value that is written to the psrasy and ps rsync bits is kept, hence keeping the corresponding prescaler reset signals a sserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during th e configuration. when the tsm bit is written to zero, the psrasy and psrsync bits are cl eared by hardware and the timer/counters simultaneously start counting. ? bit 6:2 ? res4:0 - reserved 307 8266c-mcu wireless-08/11 ATMEGA128RFA1 this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 1 ? psrasy - prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is writ ten when timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. ? bit 0 ? psrsync - prescaler reset for synchronous t imer/counters when this bit is one, the timer/counter0, timer/cou nter1, timer/counter3, timer/counter4 and timer/counter5 prescaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is s et. note that timer/counter0, timer/counter1, timer/counter3, timer/counter4 and timer/counter5 share the same prescaler and a reset of this prescaler will affect all timers. 308 8266c-mcu wireless-08/11 ATMEGA128RFA1 20 output compare modulator (ocm1c0a) 20.1 overview the output compare modulator (ocm) allows generatio n of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare un it of the 8-bit timer/counter0. for more details about these timer/counters see "timer/counter 0, 1, 3, 4, and 5 prescaler" on page 305 and "8-bit timer/counter2 with pwm and asynchronous operation" on page 310 . figure 20-1. output compare modulator, block diagram oc1c pin oc1c / oc0a / pb7 timer/counter 1 timer/counter 0 oc0a when the modulator is enabled, the two output compa re channels are modulated together as shown in the block diagram ( figure 20-1 above ). 20.2 description the output compare unit 1c and output compare unit 2 share the pb7 port pin for output. the outputs of the output compare units (oc 1c and oc0a) override the normal portb7 register when one of them is enabled (i.e., when comnx1:0 is not equal to zero). when both oc1c and oc0a are enabled at the same time, the modulator is automatically enabled. the functional equivalent schematic of the modulato r is shown on in the following figure. the schematic includes part of the timer/co unter units and the port b bit 7 output driver circuit. figure 20-2. output compare modulator, schematic portb7 ddrb7 d q d q pin coma01coma00 databus oc1c / oc0a/ pb7 com1c1com1c0 modulator 1 0 oc1c d q oc0a d q ( from waveform generator )( from waveform generator ) 0 1 vcc 309 8266c-mcu wireless-08/11 ATMEGA128RFA1 when the modulator is enabled the type of modulatio n (logical and or or) can be selected by the portb7 register. note that the ddrb 7 controls the direction of the port independent of the comnx1:0 bit setting. 20.3 timing example figure 20-3 below illustrates the modulator in action. in this examp le the timer/counter1 is set to operate in fast pwm mode ( non-inverted) and timer/counter0 uses ctc waveform mode with toggle compare output m ode (comnx1:0 = 1). figure 20-3. output compare modulator, timing diagram 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o in this example timer/counter2 provides the carrier while the modulating signal is generated by the output compare unit c of the timer /counter1. the resolution of the pwm signal (oc1c) is reduced by the modulation. the reduction factor is equal to the number of system clock cycle s of one period of the carrier (oc0a). in this example the resolution is reduced by a fact or of two. the reason for the reduction is illustrated in figure 20-3 above at the second and third period of the pb7 output when portb7 equals zero. the period 2 high t ime is one cycle longer than the period 3 high time, but the result on the pb7 outpu t is equal in both periods. 310 8266c-mcu wireless-08/11 ATMEGA128RFA1 21 8-bit timer/counter2 with pwm and asynchronous o peration 21.1 features timer/counter2 is a general purpose, single channel , 8-bit timer/counter module. the main features are: ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase-correct pulse-width modulator (p wm) ? frequency generator ? 10 bit clock prescaler ? overflow and compare match interrupt sources (tov2, ocf2a and ocf2b) ? able to run with external 32 khz watch crystal inde pendent of the i/o clock 21.2 overview a simplified block diagram of the 8-bit timer/count er is shown on figure 21-1 on page 311. for the current placement of i/o pins, see cha pter "pin configurations" on page 2 . cpu accessible i/o registers, including i/o bits an d i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the "register description" on page 324. the power reduction timer/counter2 bit prtim2 in re gister prr0 (see "prr0 ? power reduction register0" on page 169 ) must be written to zero to enable timer/counter2 module. note: oc2b is implemented but not routed to a pin a nd for this reason it can?t be used. 21.2.1 registers the timer/counter (tcnt2) and output compare regist er (ocr2a and ocr2b) are 8 bit registers. interrupt request (abbreviated to in t.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrup ts are individually masked with the timer interrupt mask register (timsk2). tifr2 and t imsk2 are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler, asynchronously clocked from the tosc1/2 pins or alternatively from the aut omated meter reading (amr) pin as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock sele ct logic block controls which clock source the timer/counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is s elected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the resu lt of the compare can be used by the waveform generator to generate a pwm or variable fr equency output on the output compare pins (oc2a and oc2b). see chapter "output compare unit" on page 317 for details. the compare match event will also set the compare flag (ocf2a or ocf2b) which can be used to generate an output compare int errupt request. 21.2.2 definitions many register and bit references in this document a re written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the 311 8266c-mcu wireless-08/11 ATMEGA128RFA1 register or bit defines in a program, the precise f orm must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. figure 21-1. 8-bit timer/counter block diagram the definitions in table table 21-1 below are also used extensively throughout the section. table 21-1. definitions bottom the counter reaches the bottom when it becom es zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equ al to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assi gnment is dependent on the mode of operation. 21.3 timer/counter clock sources the timer/counter can be clocked by an internal syn chronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is either taken from the timer/counter oscil lator connected to tosc1 and tosc2 or from the amr pin. for details on asynchron ous operation, see section 312 8266c-mcu wireless-08/11 ATMEGA128RFA1 "asynchronous operation of timer/counter2" on page 321. for details on clock sources and prescaler, see section "timer/counter prescaler" on page 323. 21.4 counter unit the main part of the 8-bit timer/counter is the pro grammable bi-directional counter unit. figure 21-2 below shows a block diagram of the counter and its surrou nding environment. figure 21-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (z ero). depending on the mode of operation used, the counte r is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). when no clock source is selected (cs22:0 = 0) the timer is stopped. howe ver, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr 2a) and the wgm22 located in the timer/counter control register b (tccr2b). there ar e close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc2a and oc2b. for more details abo ut advanced counting sequences and waveform generation, see chapter "modes of operation" below . the timer/counter overflow flag (tov2) is set accor ding to the mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. 21.5 modes of operation the mode of operation, i.e., the behaviour of the t imer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2x1:0 bits control whether the pwm output ge nerated should be inverted or 313 8266c-mcu wireless-08/11 ATMEGA128RFA1 not (inverted or non-inverted pwm). for non-pwm mod es the com2x1:0 bits control whether the output should be set, cleared, or toggl ed at a compare match (see chapter "compare match output unit" on page 318). for detailed timing information refer to chapter "timer/counter timing diagrams" on page 320. the following table shows the function of the wgm22 :0 bits of registers tccr2a and tccr2b. these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of wavef orm generation to be used. table 21-2. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1,2) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4 1 0 0 reserved ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top notes: 1. max = 0xff 2. bottom = 0x00 21.5.1 normal mode the simplest mode of operation is the normal mode ( wgm22:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8 bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operatio n the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, ex cept that it is only set, not cleared. however combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by soft ware. there are no special cases to consider in the normal mode, a new counter value ca n be written anytime. the output compare unit can be used to generate int errupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 21.5.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm22:0 = 2) , the ocr2a register is used to manipulate the counter resolution. in ctc mode t he counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the oc r2a defines the top value for the counter, hence also its resolution. this mode a llows greater control of the compare match output frequency. it also simplifies the oper ation of counting external events. the timing diagram for the ctc mode is shown in tab le 20-3. the counter value (tcnt2) increases until a compare match occurs betw een tcnt2 and ocr2a, and then counter (tcnt2) is cleared. 314 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 21 - 3 . ctc mode, timing diagram tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low pres caler value must be done with care since the ctc mode does not have the double bufferi ng feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare mat ch can occur. for generating a waveform output in ctc mode, the o c2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. th e waveform generated will have a maximum frequency of f oc2a = f clki/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation ) 1( 2 / ocrnx n f f o clki ocnx + ? ? = the n variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 21.5.3 fast pwm mode the timer/counter overflow flag (tov2) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler rou tine can be used for updating the compare value. in fast pwm mode, the compare unit allows generatio n of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will pro duce a non-inverted pwm and an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm22:0 = 3, and ocr2a when wg m22:0 = 7 (see section "register description" on page 324 for register tccr2a). the actual oc2x val ue will only be visible on the port pin if the data directi on for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc2x register at the compare match between ocr2x and tcnt2, and clearing (or set ting) the oc2x register at the timer clock cycle the counter is cleared (changes f rom top to bottom). 315 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 21-4. fast pwm mode, timing diagram tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 the pwm frequency for the output can be calculated by the following equation: 256 / ? = n f f o clki ocnxpwm the n variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 ti mer clock cycle. setting the ocr2a equal to max will result in a constantly high or lo w output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output i n fast pwm mode can be achieved by setting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the waveform generated will have a maximum frequency of f oc2a = f clki/o /2 when ocr2a is set to zero. this feature is similar to the oc2a to ggle in ctc mode, except the double buffer feature of the output compare unit is enable d in the fast pwm mode. 21.5.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provi des a high resolution phase correct pwm waveform generation option. the phase c orrect pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when wgm 22:0 = 1, and ocr2a when wgm22:0 = 5. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2 x while up-counting, and set on the compare match while down-counting. in invert ing output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremente d until the counter value matches top. when the counter reaches top, it changes the c ount direction. the tcnt2 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 21-5 on page 316. the tcnt2 value is in the timing diagram shown as a histogram for illustrating the d ual-slope operation. the diagram 316 8266c-mcu wireless-08/11 ATMEGA128RFA1 includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. figure 21 - 5 . phase correct pwm mode, timing diagram tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2)(comnx1:0 = 3) ocrnx update the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two w ill produce a non-inverted pwm. an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm22:0 = 3, and ocr2a when wg m22:0 = 7 (see section "register description" on page 324 for register tccr2a). the actual oc2x val ue will only be visible on the port pin if the data directi on for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc2x register at the compare match between ocr2x and tcnt2 when the counter incr ements, and setting (or clearing) the oc2x register at compare match betwee n ocr2x and tcnt2 when the counter decrements. the pwm frequency for the outpu t when using phase correct pwm can be calculated by the following equation: 510 / _ ? = n f f o i clk ocnxpcpwm the n variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode . if the ocr2a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 21-5 above ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that gi ve a transition without compare match. 317 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? ocr2a changes its value from max, like in figure 21-5 on page 316. when the ocr2a value is max the ocn pin value is the same as the result of a down- counting compare match. to ensure symmetry around b ottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn c hange that would have happened on the way up. 21.6 output compare unit the 8 bit comparator continuously compares tcnt2 wi th the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or o cr2b, the comparator signals a match. a match will set the output compar e flag (ocf2a or ocf2b) at the next timer clock cycle. if the corresponding interr upt is enabled, the output compare flag generates an output compare interrupt. the out put compare flag is automatically cleared when the interrupt is execute d. alternatively, the output compare flag can be cleared by software by writing a logica l one to its i/o bit location. the waveform generator uses the match signal to generat e an output according to operating mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes o f operation (chapter "modes of operation" on page 312). figure 21-6 below shows a block diagram of the output compare unit. figure 21 - 6 . output compare unit, block diagram ocfn (int.req.) = (8-bit comparator ) ocrn ocxy data bus tcntn wgmn1:0 waveform generator top focn comn1:0 bottom the ocr2x register is double buffered when using an y of the pulse width modulation (pwm) modes. for the normal and clear timer on comp are (ctc) modes of operation, the double buffering is disabled. the do uble buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurren ce of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. 318 8266c-mcu wireless-08/11 ATMEGA128RFA1 the ocr2x register access may seem complex, but thi s is not the case. when the double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is disabled the cpu will access th e ocr2x directly. 21.6.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (foc2x) bit. forcing compare match will not set the ocf2x flag or reload/clear t he timer, but the oc2x pin will be updated as if a real compare match had occurred (th e com2x1:0 bits settings define whether the oc2x pin is set, cleared or toggled). 21.6.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2x to be initialized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. 21.6.3 using the output compare unit since writing tcnt2 in any mode of operation will b lock all compare matches for one timer clock cycle, there are risks involved when ch anging tcnt2 when using the output compare channel, independently of whether th e timer/counter is running or not. if the value written to tcnt2 equals the ocr2x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is down-coun ting. the setup of the oc2x should be performed before se tting the data direction register for the port pin to output. the easiest way of sett ing the oc2x value is to use the force output compare (foc2x) strobe bit in normal mode. t he oc2x register keeps its value even when changing between waveform generatio n modes. be aware that the com2x1:0 bits are not double buff ered together with the compare value. a change of the com2x1:0 bits will take eff ect immediately. 21.7 compare match output unit the compare output mode (com2x1:0) bits have two fu nctions. the waveform generator uses the com2x1:0 bits for defining the o utput compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 20-7 shows a simplified schematic of the log ic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are shown. when referring to t he oc2x state, the reference is for the internal oc2x register, not the oc2x pin. the general i/o port function is overridden by the output compare (oc2x) from the waveform generator if either of the com2x1:0 bits a re set. however, the oc2x pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the o c2x pin (ddr_oc2x) must be set as output before the oc2x value is visible on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows i nitialization of the oc2x state before the output is enabled. note that some com2x1 :0 bit settings are reserved for certain modes of operation. see section "register description" on page 324 for details. 319 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 21 - 7 . compare match output unit, schematic port ddr d q d q ocnx pin ocnx d q waveform generator comnx1comnx0 0 1 data bus focn clk i/o 21.7.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits diffe rently in normal, ctc, and pwm modes. setting the com2x1:0 = 0 for all modes tells the waveform generator that no action on the oc2x register is to be performed on t he next compare match. for compare output actions in the non-pwm modes for fas t pwm mode and for phase correct pwm refer to section "register description" on page 324 for register tccr2a . a change of the com2x1:0 bits state will have effec t at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc2x strobe bits. the following table shows the com2 x 1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 21-3. compare output mode, non-pwm mode com2x1 com2x0 description 0 0 normal port operation, oc2 x disconnected; 0 1 toggle oc2 x on compare match; 1 0 clear oc2 x on compare match; 1 1 set oc2 x on compare match; table 17-3 shows the com2 x 1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. table 21-4. compare output mode, fast pwm mode com2x1 com2x0 description 0 0 normal port operation, oc2 x disconnected. 0 1 wgm22 = 0: normal port operation, oc2a disconnected . wgm22 = 1: toggle oc2a on compare match. oc2b: not applicable, reserved function; 320 8266c-mcu wireless-08/11 ATMEGA128RFA1 com2x1 com2x0 description 1 0 clear oc2 x on compare match, set oc2 x at bottom, (non- inverting mode). 1 1 set oc2 x on compare match, clear oc2 x at bottom, (inverting mode). note: 1. a special case occurs when ocr2 x equals top and com2 x 1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see "fast pwm mode" on page 314. table 17-4 shows the com2 x 1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. table 21-5. compare output mode, phase correct pwm mode com2x1 com2x0 description 0 0 normal port operation, oc2 x disconnected. 0 1 wgm22 = 0: normal port operation, oc2a disconnected . wgm22 = 1: toggle oc2a on compare match. oc2b: not applicable, reserved function; 1 0 clear oc2 x on compare match when up-counting. set oc2 x on compare match when down-counting. 1 1 set oc2 x on compare match when up-counting. clear oc2 x on compare match when down-counting. note: 1. a special case occurs when ocr2 x equals top and com2 x 1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see "phase correct pwm mode" on page 315 for more details. 21.8 timer/counter timing diagrams the following figures show the timer/counter in syn chronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in a synchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 21-8 below contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 21 - 8 . timer/counter timing diagram, no prescaling clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 321 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 21-9 below shows the same timing data, but with the prescaler enabled. figure 21 - 9 . timer/counter timing diagram, with prescaler (f clki/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) figure 21-10 below shows the setting of ocf2a in all modes except ctc mode. figure 21 - 10 . timer/counter timing diagram, setting of ocf2a, wit h prescaler (f clki/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) figure 21-11 below shows the setting of ocf2a and the clearing of tcn t2 in ctc mode. figure 21 - 11 . timer/counter timing diagram, clear timer on compar e match mode, with prescaler (f clki/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 21.9 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some c onsiderations must be taken. 322 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? warning: when switching between asynchronous and s ynchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, a nd tccr2x might be corrupted. a safe procedure for switching clock sou rce is: 1. disable the timer/counter2 interrupts by clearin g ocie2x and toie2. 2. select clock source by setting as2 as appropriat e. 3. write new values to tcnt2, ocr2x, and tccr2x. 4. to switch to asynchronous operation: wait for tc n2ub, ocr2xub, and tcr2xub. 5. clear the timer/counter2 interrupt flags. 6. enable interrupts, if needed. ? the cpu main clock frequency must be more than fou r times the oscillator frequency. ? when writing to one of the registers tcnt2, ocr2x, or tccr2x, the value is transferred to a temporary register, and latched af ter two positive edges on tosc1. the user should not write a new value before the co ntents of the temporary register have been transferred to its destination. each of t he five mentioned registers have their individual temporary register, which means th at e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status r egister ? assr has been implemented. ? when entering power-save or adc noise reduction mo de after having written to tcnt2, ocr2x, or tccr2x, the user must wait until t he written register has been updated if timer/counter2 is used to wake up the de vice. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if any of the output compare2 interrupt is used to wak e up the device, since the output compare function is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mod e before the corresponding ocr2xub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up fr om power-save or adc noise reduction mode, precautions must be taken if the us er wants to re-enter one of these modes: the interrupt logic needs one tosc1 cy cle to be reset. if the time between wake-up and re-entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in doubt whether the time before re-entering powersave or ad c noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 1. write a value to tccr2x, tcnt2, or ocr2x. 2. wait until the corresponding update busy flag in assr returns to zero. . 3. enter power-save or adc noise reduction mode. ? when the asynchronous operation is selected, the 3 2.768 khz oscillator for timer/counter2 is always running, except in power-d own and standby modes. after a power-up reset or wake-up from power-down or stan dby mode, the user should be aware of the fact that this oscillator might tak e as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standb y mode. the contents of all timer/counter2 registers must be considered lost af ter a wake-up from power- down or standby mode due to unstable clock signal u pon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. ? description of wake up from power-save or adc nois e reduction mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the ti mer clock, that is, the timer is always 323 8266c-mcu wireless-08/11 ATMEGA128RFA1 advanced by at least one before the processor can r ead the counter value. after wake-up, the mcu is halted for four cycles, it exec utes the interrupt routine, and resumes execution from the instruction following sl eep. ? reading of the tcnt2 register shortly after wake-u p from power-save may give an incorrect result. since tcnt2 is clocked on the asy nchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every risin g tosc1 edge. when waking up from powersave mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from po wer-save mode is essentially unpredictable, as it depends on the wake-up time. t he recommended procedure for reading tcnt2 is thus as follows: 1. write any value to either of the registers ocr2x or tccr2x. 2. wait for the corresponding update busy flag to b e cleared. 3. read tcnt2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus on e timer cycle. the timer is therefore advanced by at least one before the proce ssor can read the timer value causing the setting of the interrupt flag. the outp ut compare pin is changed on the timer clock and is not synchronized to the processo r clock. ? if the cpu wakes up from asynchronous timer and go es back to sleep again, it may wakeup multiple times or the irq is called multiple times. this may be avoided if the cpu waits with the next sleep instruction until the next asynchronous clock arrives. 21.10 timer/counter prescaler figure 21 - 12 . prescaler for timer/counter2 the register assr defines the clock source for the asynchronous timer/counter2. the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i/o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked either from the tosc1 or fro m the amr pin. this enables the use of timer/counter2 as a real time counter (rtc). 324 8266c-mcu wireless-08/11 ATMEGA128RFA1 the tosc1 pin is selected by setting the exclkamr b it in the assr register to logic zero. under this condition tosc1 and tosc2 are disc onnected from port g and a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2. the os cillator is optimized for use with a 32.768 khz crystal. by setting the exclk bit in the assr, a 32 khz external clock can be applied on tosc1. setting the exclkamr bit to logic one selects the a mr pin as the timer/counter2 clock source. thus the 32 khz oscillator can be use d by the mac symbol counter while the timer/counter2 uses pin amr as clock source, se e "mac symbol counter" on page 134 . a complete overview of the implemented asynchronous clock sources can be found in table 21-6 below . the last column mentions which pins are available for gpio functionality. for details about the assr register refer to section "register description" below . for timer/counter2, the possible pre-scaled selecti ons are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. table 21-6. asynchronous clock selection for timer/counter2 and symbol-counter as2 exclk exclkamr timer/counter2 clock source 32 khz crystal osc. (tosc1/tosc2) pg2, pg3, pg4 as gpios 0 0 0 clki/o off pg2, pg3, pg4 0 1 0 not defined not defined not defined 1 0 0 32 khz crystal osc on pg2 1 1 0 tosc1 (pg4) off pg2, pg3 0 0 1 clki/o off pg2, pg3, pg4 0 1 1 not defined not defined not defined 1 0 1 amr (pg2) on 1 1 1 amr (pg2) off pg3, pg4 21.11 register description 21.11.1 timsk2 ? timer/counter interrupt mask regis ter bit 7 6 5 4 3 2 1 0 na ($70) res4 res3 res2 res1 res0 ocie2b ocie2a toie2 timsk2 read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? ocie2b - timer/counter2 output compare matc h b interrupt enable when the ocie2b bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match b interrupt is ena bled. the corresponding interrupt is executed if a compare match in timer/counter2 oc curs, i.e., when the ocf2b bit is set in the timer/counter2 interrupt flag register t ifr2. 325 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 1 ? ocie2a - timer/counter2 output compare matc h a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is ena bled. the corresponding interrupt is executed if a compare match in timer/counter2 oc curs, i.e., when the ocf2a bit is set in the timer/counter2 interrupt flag register t ifr2. ? bit 0 ? toie2 - timer/counter2 overflow interrupt e nable when the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the c orresponding interrupt is executed if an overflow in timer/counter2 occurs i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register tifr2. 21.11.2 tifr2 ? timer/counter interrupt flag regist er bit 7 6 5 4 3 2 1 0 $17 ($37) res4 res3 res2 res1 res0 ocf2b ocf2a tov2 tifr2 read/write r r r r r rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? res4:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 2 ? ocf2b - output compare flag 2 b the ocf2b bit is set (one) when a compare match occ urs between the timer/counter2 and the data in ocr2b output compare register2. ocf 2b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. when th e i-bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), an d ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a - output compare flag 2 a the ocf2a bit is set (one) when a compare match occ urs between the timer/counter2 and the data in ocr2a output compare register2. ocf 2a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when th e i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), an d ocf2a are set (one), the timer/counter2 compare match interrupt is executed. ? bit 0 ? tov2 - timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs i n timer/counter2. tov2 is cleared by hardware when executing the corresponding interr upt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov 2 are set (one), the timer/counter2 overflow interrupt is executed. in p wm mode, this bit is set when timer/counter2 changes counting direction at 0x00. 326 8266c-mcu wireless-08/11 ATMEGA128RFA1 21.11.3 tccr2a ? timer/counter2 control register a bit 7 6 5 4 3 2 1 0 na ($b0) com2a1 com2a0 com2b1 com2b0 res1 res0 wgm21 wgm20 tccr2a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? com2a1:0 - compare match output a mode these bits control the output compare pin (oc2a) be havior. if one or both of the com2a1:0 bits are set, the oc2a output overrides th e normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the c om2a1:0 bits depends on the wgm22:0 bit setting. the following table shows the com2a1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (n on-pwm). refer to section "compare match output unit" for a description of th e functionality in the other modes. table 21-7 com2a register bits register bits value description 0 normal port operation, oc2a disconnected 1 toggle oc2a on compare match 2 clear oc2a on compare match com2a1:0 3 set oc2a on compare match ? bit 5:4 ? com2b1:0 - compare match output b mode these bits control the output compare pin (oc2b) be havior. if one or both of the com2b1:0 bits are set, the oc2b output overrides th e normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the c om2b1:0 bits depends on the wgm22:0 bit setting. the following table shows the com2b1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (n on-pwm). refer to section "compare match output unit" for a description of th e functionality in the other modes. table 21-8 com2b register bits register bits value description 0 normal port operation, oc2b disconnected 1 toggle oc2b on compare match 2 clear oc2b on compare match com2b1:0 3 set oc2b on compare match ? bit 3:2 ? res1:0 - reserved ? bit 1:0 ? wgm21:20 - waveform generation mode combined with the wgm22 bit found in the tccr2b reg ister, these bits control the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter2 unit are: normal mode (counter), cle ar timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section "modes of operation" for details). 327 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 21-9 wgm2 register bits register bits value description 0x0 normal mode of operation 0x1 pwm, phase correct, top=0xff 0x2 ctc, top = ocra 0x3 fast pwm, top=0xff 0x4 reserved 0x5 pwm, phase correct, top = ocra 0x6 reserved wgm21:20 0x7 fast pwm, top=ocra 21.11.4 tccr2b ? timer/counter2 control register b bit 7 6 5 4 3 2 1 0 na ($b1) foc2a foc2b res1 res0 wgm22 cs22 cs21 cs20 tccr2b read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? foc2a - force output compare a the foc2a bit is only active when the wgm bits spec ify a non-pwm mode. however, for ensuring compatibility with future devices, thi s bit must be set to zero when tccr2b is written in pwm mode operation. when writing a lo gical one to the foc2a bit, an immediate compare match is forced on the waveform g eneration unit. the oc2a output is changed according to its com2a1:0 bits se tting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2 a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b - force output compare b the foc2b bit is only active when the wgm bits spec ify a non-pwm mode. however, for ensuring compatibility with future devices, thi s bit must be set to zero when tccr2b is written in pwm mode operation. when writing a lo gical one to the foc2b bit, an immediate compare match is forced on the waveform g eneration unit. the oc2b output is changed according to its com2b1:0 bits se tting. note that the foc2b bit is implemented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2 b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bit 5:4 ? res1:0 - reserved ? bit 3 ? wgm22 - waveform generation mode combined with the wgm21:0 bits found in the tccr2a register, this bit controls the counting sequence of the counter, the source for ma ximum (top) counter value, and what type of waveform generation to be used. see de scription of "tccr2a - timer/counter2 control register a" for details. ? bit 2:0 ? cs22:20 - clock select the three clock select bits select the clock source to be used by the timer/counter2. if external pin modes are used for the timer/counter2, transitions on the t2 pin will clock 328 8266c-mcu wireless-08/11 ATMEGA128RFA1 the counter even if the pin is configured as an out put. this feature allows software control of the counting. table 21-10 cs2 register bits register bits value description 0x00 no clock source (timer/counter2 stopped) 0x01 clk_t2s/1 (no prescaling) 0x02 clk_t2s/8 (from prescaler) 0x03 clk_t2s/32 (from prescaler) 0x04 clk_t2s/64 (from prescaler) 0x05 clk_t2s/128 (from prescaler) 0x06 clk_t2s/256 (from prescaler) cs22:20 0x07 clk_t2s/1024 (from prescaler) 21.11.5 tcnt2 ? timer/counter2 bit 7 6 5 4 3 2 1 0 na ($b2) tcnt27:20 tcnt2 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the timer/counter register gives direct access, bot h for read and write operations, to the 8-bit counter unit of the timer/counter2. writi ng to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. ? bit 7:0 ? tcnt27:20 - timer/counter2 byte 21.11.6 ocr2a ? timer/counter2 output compare regis ter a bit 7 6 5 4 3 2 1 0 na ($b3) ocr2a7:0 ocr2a read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the output compare register a contains an 8-bit val ue that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. ? bit 7:0 ? ocr2a7:0 - output compare register 21.11.7 ocr2b ? timer/counter2 output compare regis ter b bit 7 6 5 4 3 2 1 0 na ($b4) ocr2b7:0 ocr2b read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 329 8266c-mcu wireless-08/11 ATMEGA128RFA1 the output compare register b contains an 8-bit val ue that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. ? bit 7:0 ? ocr2b7:0 - output compare register 21.11.8 assr ? asynchronous status register bit 7 6 5 4 3 2 1 0 na ($b6) exclkamr exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write rw rw rw r r r r r initial 0 0 0 0 0 0 0 0 the register assr controls the asynchronous clocks for timer/counter2 and enables the asynchronous 32khz clock for the symbol counter . three bits (as2,exclk,exclkamr) are used to control the clocks . note, to prevent clock spikes on asynchronous clock wires, every access to assr s hould change only one of the three bits. ? bit 7 ? exclkamr - enable external clock input for amr the bit exclkamr extends the available clock source s for timer/counter2. if this bit is written to one, and asynchronous clock is selected (bit as2 set), amr functionality is enabled and timer/counter2 is clocked by pin amr. ? bit 6 ? exclk - enable external clock input when exclk is written to one, and asynchronous cloc k is selected, the external clock input buffer is enabled and an external clock can b e input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the c rystal oscillator will only run when this bit is zero. ? bit 5 ? as2 - timer/counter2 asynchronous mode when as2 is written to zero, timer/counter2 is cloc ked from the i/o clock, clki/o. when as2 is written to one, timer/counter2 is clock ed from a crystal oscillator connected to the timer oscillator 1 (tosc1) pin. wh en the value of as2 is changed, the contents of tcnt2, ocr2a, ocr2b, tccr2a and tcc r2b might be corrupted. ? bit 4 ? tcn2ub - timer/counter2 update busy when timer/counter2 operates asynchronously and tcn t2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit ind icates that tcnt2 is ready to be updated with a new value. ? bit 3 ? ocr2aub - timer/counter2 output compare reg ister a update busy when timer/counter2 operates asynchronously and ocr 2a is written, this bit becomes set. when ocr2a has been updated from the t emporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub - timer/counter2 output compare reg ister b update busy when timer/counter2 operates asynchronously and ocr 2b is written, this bit becomes set. when ocr2b has been updated from the t emporary storage register, 330 8266c-mcu wireless-08/11 ATMEGA128RFA1 this bit is cleared by hardware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub - timer/counter2 control register a update busy when timer/counter2 operates asynchronously and tcc r2a is written, this bit becomes set. when tccr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub - timer/counter2 control register b update busy when timer/counter2 operates asynchronously and tcc r2b is written, this bit becomes set. when tccr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is ready to be updated with a new value. 21.11.9 gtccr ? general timer counter control regis ter bit 7 6 5 4 3 2 1 0 $23 ($43) tsm psrasy gtccr read/write rw rw initial value 0 0 ? bit 7 ? tsm - timer/counter synchronization mode writing the tsm bit to one activates the timer/coun ter synchronization mode. in this mode the value that is written to the psrasy and ps rsync bits is kept, hence keeping the corresponding prescaler reset signals a sserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during th e configuration. when the tsm bit is written to zero, the psrasy and psrsync bits are cl eared by hardware and the timer/counters simultaneously start counting. ? bit 1 ? psrasy - prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is writ ten when timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. 331 8266c-mcu wireless-08/11 ATMEGA128RFA1 22 spi- serial peripheral interface 22.1 features the serial peripheral interface (spi) allows high-s peed synchronous data transfer between the ATMEGA128RFA1 and peripheral devices or between several avr devices. the ATMEGA128RFA1 spi includes the following featur es: ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 22.2 functional description usart can also be used in master spi mode, see "usart in spi mode" on page 369 . the power reduction spi bit, prspi, in "prr0 ? power reduction register0" on page 169 must be written to zero to enable spi module. the block diagram of the spi interface is shown in figure 22-1 on page 332. the interconnection between master and slave cpus w ith spi is shown in figure 22-2 on page 332. the system consists of two shift registe rs, and a master clock generator. the spi master initiates the communication cycle wh en pulling low the slave select ss __ pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generate s the required clock pulses on the sck line to interchange data. data is always shifte d from master to slave on the master out ? slave in, mosi, line, and from slave to maste r on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss __ , line. when configured as a master, the spi interface has no automatic control of the ss __ line. this must be handled by user software before commun ication can start. when this is done, writing a byte to the spi data register start s the spi clock generator, and the hardware shifts the eight bits into the slave. afte r shifting one byte, the spi clock generator stops, setting the end of transmission fl ag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrup t is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss __ line. the last incoming byte will be kept in the b uffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss __ pin is driven high. in this state, software may up date the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven lo w. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is reques ted. the slave may continue to place new data to be sent into spdr before reading the in coming data. the last incoming byte will be kept in the buffer register for later use. 332 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 22-1. spi block diagram (1) spi2x spi2x divider /2/4/8/16/32/64/128 note: 1. refer to figure 1-1 on page 2 and table 14-3 on page 195 for spi pin placement. figure 22-2. spi master-slave interconnection shift enable the system is single buffered in the transmit direc tion and double buffered in the receive direction. this means that bytes to be tran smitted cannot be written to the spi data register before the entire shift cycle is comp leted. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the firs t byte is lost. in spi slave mode, the 333 8266c-mcu wireless-08/11 ATMEGA128RFA1 control logic will sample the incoming signal of th e sck pin. to ensure correct sampling of the clock signal, the minimum low and high perio ds should be: low period: longer than 2 cpu clock cycles high period: longer than 2 cpu clock cycles when the spi is enabled, the data direction of the mosi, miso, sck, and ss __ pins is overridden according to table 21-1. for more detail s on automatic port overrides, refer to "alternate port functions" on page 193 . table 22-1. pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input note: 1. see "alternate functions of port b" on page 194 for a detailed description of how to define the direction of the user defined spi pin s. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examp les must be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data directio n bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. assembly code example ( 1 ) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 337 8266c-mcu wireless-08/11 ATMEGA128RFA1 22.4 register description 22.4.1 spcr ? spi control register bit 7 6 5 4 3 2 1 0 $2c ($4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? spie - spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set.s ? bit 6 ? spe - spi enable when the spe bit is set (one), the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord - data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of th e data word is transmitted first. ? bit 4 ? mstr - master/slave select this bit selects master spi mode when written to on e, and slave spi mode when written logic zero. if the slave select pin is conf igured as an input and is driven low while mstr is set, mstr will be cleared and spif in spsr are set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol - clock polarity when this bit is written to one, sck is high when i dle. when cpol is written to zero, sck is low when idle. refer to the "data modes" sec tion for an example. the cpol functionality is summarized below. table 22-3 cpol register bits register bits value description 0 rising (leading edge), falling (trailing edge) cpol 1 falling (leading egde), rising (trailing edge) ? bit 2 ? cpha - clock phase the settings of the clock phase bit (cpha) determin e if data is sampled on the leading (first) or trailing (last) edge of sck. refer to th e "data modes" section for an example. the cpol functionality is summarized below. table 22-4 cpha register bits register bits value description 0 sample (leading edge), setup (trailing edge) cpha 1 setup (leading edge), sample (trailing edge) ? bit 1:0 ? spr1:0 - spi clock rate select 1 and 0 338 8266c-mcu wireless-08/11 ATMEGA128RFA1 these two bits control the sck rate of the device c onfigured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency fosc is shown in the following tabl e. table 22-5 spr register bits register bits value description 0x00 fosc/4 / fosc/2 (spi2x=0/1) 0x01 fosc/16 / fosc/8 (spi2x=0/1) 0x02 fosc/64 / fosc/32(spi2x=0/1) spr1:0 0x03 fosc/128 / fosc/64 (spi2x=0/1) 22.4.2 spsr ? spi status register bit 7 6 5 4 3 2 1 0 $2d ($4d) spif wcol res4 res3 res2 res1 res0 spi2x spsr read/write r r r r r r r rw initial value 0 0 0 0 0 0 0 0 ? bit 7 ? spif - spi interrupt flag when a serial transfer is complete, the spif flag i s set. an interrupt is generated if spie in spcr is set and global interrupts are enabl ed. the spif flag is also set if the slave select pin is an input and is driven low when the spi is in master mode. spif is cleared by hardware when executing the correspondin g interrupt handling vector. alternatively, the spif bit is cleared by first rea ding the spi status register with spif set and then accessing the spi data register (spdr) . ? bit 6 ? wcol - write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by firs t reading the spi status register with wcol set and then accessing the spi data regis ter. ? bit 5:1 ? res4:0 - reserved ? bit 0 ? spi2x - double spi speed bit when this bit is written logic one the spi speed (s ck frequency) will be doubled when the spi is in master mode. this means that the mini mum sck period will be two cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at fosc/4 or lower. the spi interface on the atmega 128rfa1 is also used for program memory and eeprom downloading or uploading. see sec tion "serial downloading" for serial programming and verification. 22.4.3 spdr ? spi data register bit 7 6 5 4 3 2 1 0 $2e ($4e) spdr7:0 spdr read/write rw rw rw rw rw rw r r initial value x x x x x x 0 0 339 8266c-mcu wireless-08/11 ATMEGA128RFA1 the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing t o the register initiates data transmission. reading the register causes the shift register receive buffer to be read. ? bit 7:0 ? spdr7:0 - spi data register 340 8266c-mcu wireless-08/11 ATMEGA128RFA1 23 usart 23.1 features ? full duplex operation (independent serial receive a nd transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data b its and 1 or 2 stop bits ? odd or even parity generation and parity check supp orted by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? 3 separate interrupts on tx complete, tx data regis ter empty and rx complete ? multi-processor communication mode ? double speed, asynchronous communication mode 23.2 overview the universal synchronous and asynchronous serial r eceiver and transmitter (usart) is a highly flexible serial communication d evice. the ATMEGA128RFA1 has two usart?s, usart0 and usart 1. the functionality for all two usart?s is described below. usart0 and usar t1 have different i/o registers as shown in "register summary" on page 498 . a simplified block diagram of the usart transmitter is shown in figure 23-1 on page 341 on page 341. cpu accessible i/o registers and i /o pins are shown in bold. the power reduction usart0 bit, prusart0, in "prr0 ? power reduction register0" on page 169 must be disabled by writing a logical zero to it. the power reduction usart1 bit, prusart1, in "prr1 ? power reduction register 1" on page 169 must be disabled by writing a logical zero to it. the dashed boxes in the block diagram figure 23-1 on page 341 separate the three main parts of the usart (listed from the top): cloc k generator, transmitter and receiver. control registers are shared by all units. the cloc k generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xck n (transfer clock) pin is only used by synchronous transfer mode. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling dif ferent serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart modu le due to its clock and data recovery units. the recovery units are used for asy nchronous data reception. in addition to the recovery units, the receiver includ es a parity checker, control logic, a shift register and a two level receive buffer (udr n ). the receiver supports the same frame formats as the transmitter, and can detect fr ame, data overrun and parity errors. 341 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 23-1. usart block diagram (1) parity generator ubrr [h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver note: 1. see "figure 1-1" on page 2 , table 14-6 on page 197 and table 14-9 on page 199 table 14-9 on page 199 for usart pin placement. 23.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operation: n ormal asynchronous, double speed asynchronous, master synchronous and slave sy nchronous mode. the umsel n bit in usart control and status register c (ucsr n c) selects between asynchronous and synchronous operation. double speed (asynchrono us mode only) is controlled by the u2x n found in the ucsr n a register. when using synchronous mode (umsel n = 1), the data direction register for the xck n pin (ddr_xck n ) controls whether the clock source is internal (master mode) or external (slave mode). the xck n pin is only active when using synchronous mode. 342 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 22-2 on page 332 shows a block diagram of the clock genera tion logic. figure 23-2. clock generation logic, block diagram prescaling down-counter /2 ubrr /4 /2 fosc ubrr+1 sync register osc xck pin txclk u2x umsel ddr_xck 01 01 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector ucpol signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for sy nchronous slave operation. xcko clock output to xck pin (internal signal). used f or synchronous master operation. f osc system clock frequency. 23.3.1 internal clock generation ? the baud rate ge nerator internal clock generation is used for the asynchron ous and the synchronous master modes of operation. the description in this section refers to figure 22-2 on page 332. the usart baud rate register (ubrr n ) and the down-counter connected to it function as a programmable prescaler or baud rate g enerator. the down-counter, running at system clock (f osc ), is loaded with the ubrr n value each time the counter has counted down to zero or when the ubrrl n register is written. a clock is generated each time the counter reaches zero. this clock is t he baud rate generator clock output (= f osc /(ubrr n +1)). the transmitter divides the baud rate generat or clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on mo de set by the state of the umsel n , u2x n and ddr_xck n bits. table 23-1 below contains equations for calculating the baud rate ( in bits per second) and for calculating the ubrr n value for each mode of operation using an internal ly generated clock source. table 23-1. equations for calculating baud rate register settin g operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous normal mode (u2x n = 0) )1 ( 16 + = ubrrn f baud osc 1 16 ? = baud f ubrrn osc asynchronous double speed mode (u2x n = 1) )1 (8 + = ubrrn f baud osc 1 8 ? = baud f ubrrn osc 343 8266c-mcu wireless-08/11 ATMEGA128RFA1 operating mode equation for calculating baud rate (1) equation for calculating ubrr value synchronous master mode )1 (2 + = ubrrn f baud osc 1 2 ? = baud f ubrrn osc note: 1. the baud rate is defined to be the transfe r rate in bit per second (bps). baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrr n contents of the ubrrh n and ubrrl n registers, (0-4095) some examples of ubrr n values for some system clock frequencies are found in table 23-14 on page 366 . 23.3.2 double speed operation (u2x n ) the transfer rate can be doubled by setting the u2x n bit in ucsr n a. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the bau d rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communi cation. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a m ore accurate baud rate setting and system clock are required when this mode is used. f or the transmitter, there are no downsides. 23.3.3 external clock external clocking is used by the synchronous slave modes of operation. the description in this section refers to figure 22-2 on page 332 for details. external clock input from the xck n pin is sampled by a synchronization register to minimize the chance of meta-stability. the output f rom the synchronization register must then pass through an edge detector before it c an be used by the transmitter and receiver. this process introduces a two cpu clock p eriod delay and therefore the maximum external xck n clock frequency is limited by the following equati on: 4 osc xck f f < note that f osc depends on the stability of the system clock sourc e. it is therefore recommended to add some margin to avoid possible lo ss of data due to frequency variations. 23.3.4 synchronous clock operation when synchronous mode is used (umsel n = 1), the xck n pin will be used as either clock input (slave) or clock output (master). the d ependency between the clock edges and data sampling or data change is the same. the b asic principle is that data input (on rxd n ) is sampled at the opposite xck n clock edge of the edge the data output (txd n ) is changed. 344 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 23-3. synchronous mode xck n timing rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample the ucpol n bit ucrsc selects which xck n clock edge is used for data sampling and which is used for data change. as figure 22-3 on page 336 shows, when ucpol n is zero the data will be changed at rising xck n edge and sampled at falling xck n edge. if ucpoln is set, the data will be changed at falling xck n edge and sampled at rising xck n edge. 23.4 frame formats a serial frame is defined to be one character of da ta bits with synchronization bits (start and stop bits), and optionally a parity bit for err or checking. the usart accepts all 30 combinations of the following as valid frame format s: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the l east significant data bit. then the next data bits, up to a total of nine, are succeeding, e nding with the most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. when a complete frame is transmitted, it can be directly f ollowed by a new frame, or the communication line can be set to an idle (high) sta te. figure 23-4 below illustrates the possible combinations of the frame formats. bits in side brackets are optional. figure 23-4. frame formats 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame st start bit, always low (n) data bits (0 to 8) p parity bit - can be odd or even sp stop bit, always high idle no transfers on the communication line (rxd n or txd n ). an idle line must be high the frame format used by the usart is set by the uc sz n 2:0, upm n 1:0 and usbs n bits in ucsr n b and ucsr n c. the receiver and transmitter use the same settin g. note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. 345 8266c-mcu wireless-08/11 ATMEGA128RFA1 the usart character size (ucsz n 2:0) bits select the number of data bits in the frame. the usart parity mode (upm n 1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbs n ) bit. the receiver ignores the second stop bit. a frame error will therefore only be detected in cases where the first stop bit is ze ro. 23.4.1 parity bit calculation the parity bit is calculated by doing an exclusive- or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. t he parity bit is located between the last data bit and first stop bit of a serial frame. the relation between the parity bit and data bits is as follows: 1 0 0 1 2 3 1 0 1 2 3 1 = = ? ? d d d d d p d d d d d p n odd n even k k p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character 23.5 usart initialization the usart has to be initialized before any communic ation can take place. the initialization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should b e cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the perio d the registers are changed. the txc n flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. note that the txc n flag must be cleared before each transmission (bef ore udr n is written) if it is used for this purpose. the following simple usart initialization code exam ples show one assembly and one c function that are equal in functionality. the exa mples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< 350 8266c-mcu wireless-08/11 ATMEGA128RFA1 c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 352 8266c-mcu wireless-08/11 ATMEGA128RFA1 read (as one), and the fe n flag will be one when the stop bit was incorrect ( zero). this flag can be used for detecting out-of-sync conditio ns, detecting break conditions and protocol handling. the fe n flag is not affected by the setting of the usbs n bit in ucsr n c since the receiver ignores all, except for the fi rst, stop bits. for compatibility with future devices, always set this bit to zero wh en writing to ucsr n a. the data overrun flag (dor n ) indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive b uffer is full (two characters), it is a new character waiting in the receive shift register , and a new start bit is detected. if the dor n flag is set there was one or more serial frame los t between the frame last read from udr n , and the next frame read from udr n . for compatibility with future devices, always write this bit to zero when writing to ucsr n a. the dor n flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error flag (upe n ) indicates that the next frame in the receive buff er had a parity error when received. if parity check is not enabled the upe n bit will always be read zero. for compatibility with future devices, a lways set this bit to zero when writing to ucsr n a. for more details see "parity bit calculation" on page 345 and "parity checker" below . 23.7.5 parity checker the parity checker is active when the high usart pa rity mode (upm n 1) bit is set. type of parity check to be performed (odd or even) is se lected by the upm n 0 bit. when enabled, the parity checker calculates the parity o f the data bits in incoming frames and compares the result with the parity bit from the se rial frame. the result of the check is stored in the receive buffer together with the rece ived data and stop bits. the parity error flag (upe n ) can then be read by software to check if the fram e had a parity error. the upe n bit is set if the next character that can be read from the receive buffer had a parity error when received .the parity checking was enabled at that point (upm n 1 = 1). this bit is valid until the receive buffer (udr n ) is read. 23.7.6 disabling the receiver in contrast to the transmitter, disabling of the re ceiver will be immediate. data from ongoing receptions will therefore be lost. when dis abled (i.e., the rxen n is set to zero) the receiver will no longer override the normal fun ction of the rxd n port pin. the receiver buffer fifo will be flushed when the recei ver is disabled. remaining data in the buffer will be lost 23.7.7 flushing the receive buffer the receiver buffer fifo will be flushed when the r eceiver is disabled, i.e., the buffer will be emptied of its contents. unread data will b e lost. if the buffer has to be flushed during normal operation, due to for instance an err or condition, read the udr n i/o location until the rxc n flag is cleared. the following code example shows how to flush the receive buffer. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush 353 8266c-mcu wireless-08/11 ATMEGA128RFA1 c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 355 8266c-mcu wireless-08/11 ATMEGA128RFA1 the following equations can be used to calculate th e ratio of the incoming data rate and internal receiver baud rate. mf fast f slow s s d s d r s s d s s d r + + + = + ? + ? + = )1 ( )2 ( 1 )1 ( d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate tha t can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate th at can be accepted in relation to the receiver baud rate. table 23-2 below and table 23-3 below list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has h igher tolerance of baud rate variations. table 23-2. recommended maximum receiver baud rate error for no rmal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 23-3. recommended maximum receiver baud rate error for do uble speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 the recommendations of the maximum receiver baud ra te error were made under the assumption that the receiver and transmitter equall y divides the maximum total error. there are two possible sources for the receiver bau d rate error. the receiver?s system clock will always have some minor instability over the supply voltage range and the temperature range. when using the radio transceiver crystal oscillator (xosc) to generate the system clock, this is rarely a problem , but for the internal rc oscillator the system clock may differ more than 2% over the tempe rature range. the second source for the error is more controllable. the baud rate g enerator can not always do an exact 356 8266c-mcu wireless-08/11 ATMEGA128RFA1 division of the system frequency to get the baud ra te wanted. in this case an ubrr value that gives an acceptable low error can be use d if possible. 23.9 multi-processor communication mode setting the multi-processor communication mode (mpc m n ) bit in ucsr n a enables a filtering function of incoming frames received by t he usart receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames t hat has to be handled by the mcu, in a system with multiple mcus that communicate via the same serial bus. the transmitter is unaffected by the mpcm n setting, but has to be used differently when it is a part of a system utilizing the multi-processor co mmunication mode. if the receiver is set up to receive frames that co ntain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8 n ) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables seve ral slave mcus to receive data from a master mcu. this is done by first decoding a n address frame to find out which mcu has been addressed. if a particular slave mcu h as been addressed, it will receive the following data frames as normal, while the othe r slave mcus will ignore the received frames until another address frame is rece ived. 23.9.1 using mpcmn for an mcu to act as a master mcu, it can use a 9 b it character frame format (ucsz n 2:0 = 7). the 9 th bit (txb8 n ) must be set when an address frame (txb8 n = 1) or cleared when a data frame (txb = 0) is being tra nsmitted. the slave mcus must in this case be set to use a 9 bit character frame for mat. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor communicat ion mode (mpcm n in ucsr n a is set). 2. the master mcu sends an address frame, and all s laves receive and read this frame. in the slave mcus, the rxc n flag in ucsrna will be set as normal. 3. each slave mcu reads the udr n register and determines if it has been selected. i f so, it clears the mpcm n bit in ucsr n a, otherwise it waits for the next address byte and keeps the mpcm n setting. 4. the addressed mcu will receive all data frames u ntil a new address frame is received. the other slave mcus, which still have th e mpcm n bit set, will ignore the data frames. 5. when the last data frame is received by the addr essed mcu, the addressed mcu sets the mpcm n bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5 to 8 bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 charac ter frame formats. this makes full-duplex operation difficult since the transmitt er and receiver uses the same character size setting. if 5 to 8 bit character frames are us ed, the transmitter must be set to use two stop bit (usbs n = 1) since the first stop bit is used for indicati ng the frame type. 357 8266c-mcu wireless-08/11 ATMEGA128RFA1 do not use read-modify-write instructions (sbi and cbi) to set or clear the mpcm n bit. the mpcm n bit shares the same i/o location as the txc n flag and this might accidentally be cleared when using sbi or cbi instr uctions. 23.10 register description 23.10.1 udr0 ? usart0 i/o data register bit 7 6 5 4 3 2 1 0 na ($c6) udr07:00 udr0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the usart transmit data buffer register and usart r eceive data buffer registers share the same i/o address referred to as usart dat a register or udr0. the transmit data buffer register (txb) will be the des tination for data written to the udr0 register location. reading the udr0 register locati on will return the contents of the receive data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udre0 flag in t he ucsr0a register is set. data written to udr0 when the udre0 flag is not set, wil l be ignored by the usart transmitter. when data is written to the transmit b uffer and the transmitter is enabled, the transmitter will load the data into the transmi t shift register when the shift register is empty. then the data will be serially t ransmitted on the txd0 pin. the receive buffer consists of a two level fifo. the fi fo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read- modify-write instructions (sbi and cbi) on this loc ation. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. ? bit 7:0 ? udr07:00 - usart i/o data register 23.10.2 ucsr0a ? usart0 control and status register a bit 7 6 5 4 3 2 1 0 na ($c0) rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 ucsr0a read/write r rw r r r r rw rw initial value 0 0 1 0 0 0 0 0 ? bit 7 ? rxc0 - usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and co nsequently the rxc0 bit will become zero. the rxc0 flag can be used to generate a recei ve complete interrupt (see description of the rxcie0 bit). ? bit 6 ? txc0 - usart transmit complete this flag bit is set when the entire frame in the t ransmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udr0). the txc0 flag bit is automatically cleared when a trans mit complete interrupt is executed, or it can be cleared by writing a one to its bit lo cation. the txc0 flag can generate a transmit complete interrupt (see description of the txcie0 bit). 358 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 5 ? udre0 - usart data register empty the udre0 flag indicates if the transmit buffer (ud r0) is ready to receive new data. if udre0 is one, the buffer is empty, and therefore re ady to be written. the udre0 flag can generate a data register empty interrupt (see d escription of the udrie0 bit). udre0 is set after a reset to indicate that the tra nsmitter is ready. ? bit 4 ? fe0 - frame error this bit is set if the next character in the receiv e buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udr0) i s read. the fe0 bit is zero when the stop bit of received data is one. always set this b it to zero when writing to ucsr0a. ? bit 3 ? dor0 - data overrun this bit is set if a data overrun condition is dete cted. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register and a new start bit is detected. thi s bit is valid until the receive buffer (udr0) is read. always set this bit to zero when wr iting to ucsr0a. ? bit 2 ? upe0 - usart parity error this bit is set if the next character in the receiv e buffer had a parity error when received and the parity checking was enabled at that point ( upm01 = 1). this bit is valid until the receive buffer (udr0) is read. always set this bit to zero when writing to ucsr0a. ? bit 1 ? u2x0 - double the usart transmission speed this bit only has effect for the asynchronous opera tion. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the trans fer rate for asynchronous communication. ? bit 0 ? mpcm0 - multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcm0 bit is written to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the tr ansmitter is unaffected by the mpcm0 setting. for more detailed information see se ction "multi-processor communication mode". 23.10.3 ucsr0b ? usart0 control and status register b bit 7 6 5 4 3 2 1 0 na ($c1) rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 ucsr0b read/write rw rw rw rw rw rw r w initial value 0 0 1 0 0 0 0 0 ? bit 7 ? rxcie0 - rx complete interrupt enable writing this bit to one enables interrupt on the rx c0 flag. a usart receive complete interrupt will be generated only if the rxcie0 bit is written to one, the global interrupt flag in sreg is written to one and the rxc0 bit in ucsr0a is set. ? bit 6 ? txcie0 - tx complete interrupt enable writing this bit to one enables interrupt on the tx c0 flag. a usart transmit complete interrupt will be generated only if the txcie0 bit is written to one, the global interrupt flag in sreg is written to one and the txc0 bit in ucsr0a is set. ? bit 5 ? udrie0 - usart data register empty interrup t enable 359 8266c-mcu wireless-08/11 ATMEGA128RFA1 writing this bit to one enables interrupt on the ud re0 flag. a data register empty interrupt will be generated only if the udrie0 bit is written to one, the global interrupt flag in sreg is written to one and the udre0 bit in ucsr0a is set. ? bit 4 ? rxen0 - receiver enable writing this bit to one enables the usart receiver. the receiver will override normal port operation for the rxd0 pin when enabled. disab ling the receiver will flush the receive buffer invalidating the fe0, dor0 and upe0 flags. ? bit 3 ? txen0 - transmitter enable writing this bit to one enables the usart transmitt er. the transmitter will override normal port operation for the txd0 pin when enabled . the disabling of the transmitter (writing txen0 to zero) will not become effective u ntil ongoing and pending transmissions are completed, i.e., when the transmi t shift register and transmit buffer register do not contain data to be transmitted. whe n disabled, the transmitter will no longer override the txd0 port. ? bit 2 ? ucsz02 - character size the ucsz02 bits combined with the ucsz01:0 bit in u csr0c sets the number of data bits (character size) in the frame that the receive r and transmitter use. ? bit 1 ? rxb80 - receive data bit 8 rxb80 is the 9th data bit of the received character when operating with serial frames with nine data bits. the bit must be read before re ading the lower 8 bits from udr0. ? bit 0 ? txb80 - transmit data bit 8 txb80 is the 9th data bit in the character to be tr ansmitted when operating with serial frames with nine data bits. the bit must be written before writing the lower 8 bits to udr0. 23.10.4 ucsr0c ? usart0 control and status register c bit 7 6 5 4 3 2 1 0 na ($c2) umsel01 umsel00 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 ucsr0c read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 1 0 ? bit 7:6 ? umsel01:00 - usart mode select these bits select the mode of operation of the usar t0 as shown in the following table. see section "usart in spi mode" for a full descript ion of the master spi mode (mspim) operation. table 23-4 umsel0 register bits register bits value description 0x00 asynchronous usart 0x01 synchronous usart 0x02 reserved umsel01:00 0x03 master spi (mspim) ? bit 5:4 ? upm01:00 - parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter will automatically generate and send th e parity of the transmitted data bits within each frame. the receiver will generate a par ity value for the incoming data and 360 8266c-mcu wireless-08/11 ATMEGA128RFA1 compare it to the upm0 setting. if a mismatch is de tected, the upe0 flag in ucsr0a will be set. table 23-5 upm0 register bits register bits value description 0x00 disabled 0x01 reserved 0x02 enabled, even parity upm01:00 0x03 enabled, odd parity ? bit 3 ? usbs0 - stop bit select this bit selects the number of stop bits to be inse rted by the transmitter. the receiver ignores this setting. table 23-6 usbs0 register bits register bits value description 0x00 1-bit usbs0 0x01 2-bit ? bit 2:1 ? ucsz01:00 - character size the ucsz01:0 bits combined with the ucsz02 bit in u csr0b sets the number of data bits (character size) in the frame that the receive r and transmitter use. table 23-7 ucsz0 register bits register bits value description 0 5-bit 1 6-bit 2 7-bit 3 8-bit 4 reserved 5 reserved 6 reserved ucsz02:00 7 9-bit ? bit 0 ? ucpol0 - clock polarity this bit is used for synchronous mode only. write t his bit to zero when asynchronous mode is used. the ucpol0 bit sets the relationship between data output change and data input sample, and the synchronous clock (xck0) . table 23-8 ucpol0 register bits register bits value description 0 rising xckn edge (transmitted data changed), falling xckn edge (received data sampled) ucpol0 1 falling xckn edge (transmitted data changed), rising xckn edge (received data sampled) 361 8266c-mcu wireless-08/11 ATMEGA128RFA1 23.10.5 ubrr0h ? usart0 baud rate register high byt e bit 7 6 5 4 3 2 1 0 na ($c5) res3 res2 res1 res0 ubrr11 ubrr10 ubrr9 ubrr8 ubrr0h read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ubrr0 is a 12-bit register which contains the usart baud rate. the ubrr0h contains the four most significant bits, and the ub rr0l contains the eight least significant bits of the usart baud rate. ongoing tr ansmissions by the transmitter and receiver will be corrupted if the baud rate is chan ged. writing ubrr0l will trigger an immediate update of the baud rate prescaler. ? bit 7:4 ? res3:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 3:0 ? ubrr11:8 - usart baud rate register these bits represent bits [11:8] of the baud rate r egister. sample values for commonly used clock frequencies can be found in sec tion "examples of baud rate setting". 23.10.6 ubrr0l ? usart0 baud rate register low byte bit 7 6 5 4 3 2 1 0 na ($c4) ubrr7 ubrr6 ubrr5 ubrr4 ubrr3 ubrr2 ubrr1 ubrr0 ubr r0l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ubrr0 is a 12-bit register which contains the usart baud rate. the ubrr0h contains the four most significant bits, and the ub rr0l contains the eight least significant bits of the usart baud rate. ongoing tr ansmissions by the transmitter and receiver will be corrupted if the baud rate is chan ged. writing ubrr0l will trigger an immediate update of the baud rate prescaler. ? bit 7:0 ? ubrr7:0 - usart baud rate register these bits represent bits [7:0] of the baud rate re gister. sample values for commonly used clock frequencies can be found in section "exa mples of baud rate setting". 23.10.7 udr1 ? usart1 i/o data register bit 7 6 5 4 3 2 1 0 na ($ce) udr17:10 udr1 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the usart transmit data buffer register and usart r eceive data buffer registers share the same i/o address referred to as usart dat a register or udr1. the transmit data buffer register (txb) will be the des tination for data written to the udr1 register location. reading the udr1 register locati on will return the contents of the 362 8266c-mcu wireless-08/11 ATMEGA128RFA1 receive data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udre1 flag in t he ucsr1a register is set. data written to udr1 when the udre1 flag is not set, wil l be ignored by the usart transmitter. when data is written to the transmit b uffer and the transmitter is enabled, the transmitter will load the data into the transmi t shift register when the shift register is empty. then the data will be serially t ransmitted on the txd1 pin. the receive buffer consists of a two level fifo. the fi fo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read- modify-write instructions (sbi and cbi) on this loc ation. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. ? bit 7:0 ? udr17:10 - usart i/o data register 23.10.8 ucsr1a ? usart1 control and status register a bit 7 6 5 4 3 2 1 0 na ($c8) rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 ucsr1a read/write r rw r r r r rw rw initial value 0 0 1 0 0 0 0 0 ? bit 7 ? rxc1 - usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and co nsequently the rxc1 bit will become zero. the rxc1 flag can be used to generate a recei ve complete interrupt (see description of the rxcie1 bit). ? bit 6 ? txc1 - usart transmit complete this flag bit is set when the entire frame in the t ransmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udr1). the txc1 flag bit is automatically cleared when a trans mit complete interrupt is executed, or it can be cleared by writing a one to its bit lo cation. the txc1 flag can generate a transmit complete interrupt (see description of the txcie1 bit). ? bit 5 ? udre1 - usart data register empty the udre1 flag indicates if the transmit buffer (ud r1) is ready to receive new data. if udre1 is one, the buffer is empty, and therefore re ady to be written. the udre1 flag can generate a data register empty interrupt (see d escription of the udrie1 bit). udre1 is set after a reset to indicate that the tra nsmitter is ready. ? bit 4 ? fe1 - frame error this bit is set if the next character in the receiv e buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udr1) i s read. the fe1 bit is zero when the stop bit of received data is one. always set this b it to zero when writing to ucsr1a. ? bit 3 ? dor1 - data overrun this bit is set if a data overrun condition is dete cted. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register and a new start bit is detected. thi s bit is valid until the receive buffer (udr1) is read. always set this bit to zero when wr iting to ucsr1a. ? bit 2 ? upe1 - usart parity error 363 8266c-mcu wireless-08/11 ATMEGA128RFA1 this bit is set if the next character in the receiv e buffer had a parity error when received and the parity checking was enabled at that point ( upm11 = 1). this bit is valid until the receive buffer (udr1) is read. always set this bit to zero when writing to ucsr1a. ? bit 1 ? u2x1 - double the usart transmission speed this bit only has effect for the asynchronous opera tion. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the trans fer rate for asynchronous communication. ? bit 0 ? mpcm1 - multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcm1 bit is written to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the tr ansmitter is unaffected by the mpcm1 setting. for more detailed information see se ction "multi-processor communication mode". 23.10.9 ucsr1b ? usart1 control and status register b bit 7 6 5 4 3 2 1 0 na ($c9) rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 ucsr1b read/write rw rw rw rw rw rw r w initial value 0 0 1 0 0 0 0 0 ? bit 7 ? rxcie1 - rx complete interrupt enable writing this bit to one enables interrupt on the rx c1 flag. a usart receive complete interrupt will be generated only if the rxcie1 bit is written to one, the global interrupt flag in sreg is written to one and the rxc1 bit in ucsr1a is set. ? bit 6 ? txcie1 - tx complete interrupt enable writing this bit to one enables interrupt on the tx c1 flag. a usart transmit complete interrupt will be generated only if the txcie1 bit is written to one, the global interrupt flag in sreg is written to one and the txc1 bit in ucsr1a is set. ? bit 5 ? udrie1 - usart data register empty interrup t enable writing this bit to one enables interrupt on the ud re1 flag. a data register empty interrupt will be generated only if the udrie1 bit is written to one, the global interrupt flag in sreg is written to one and the udre1 bit in ucsr1a is set. ? bit 4 ? rxen1 - receiver enable writing this bit to one enables the usart receiver. the receiver will override normal port operation for the rxd1 pin when enabled. disab ling the receiver will flush the receive buffer invalidating the fe1, dor1 and upe1 flags. ? bit 3 ? txen1 - transmitter enable writing this bit to one enables the usart transmitt er. the transmitter will override normal port operation for the txd1 pin when enabled . the disabling of the transmitter (writing txen1 to zero) will not become effective u ntil ongoing and pending transmissions are completed, i.e., when the transmi t shift register and transmit buffer register do not contain data to be transmitted. whe n disabled, the transmitter will no longer override the txd1 port. ? bit 2 ? ucsz12 - character size 364 8266c-mcu wireless-08/11 ATMEGA128RFA1 the ucsz12 bits combined with the ucsz11:0 bit in u csr1c sets the number of data bits (character size) in the frame that the receive r and transmitter use. ? bit 1 ? rxb81 - receive data bit 8 rxb81 is the 9th data bit of the received character when operating with serial frames with nine data bits. the bit must be read before re ading the lower 8 bits from udr1. ? bit 0 ? txb81 - transmit data bit 8 txb81 is the 9th data bit in the character to be tr ansmitted when operating with serial frames with nine data bits. the bit must be written before writing the lower 8 bits to udr1. 23.10.10 ucsr1c ? usart1 control and status registe r c bit 7 6 5 4 3 2 1 0 na ($ca) umsel11 umsel10 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 ucsr1c read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 1 1 0 ? bit 7:6 ? umsel11:10 - usart mode select these bits select the mode of operation of the usar t1 as shown in the following table. see section "usart in spi mode" for a full descript ion of the master spi mode (mspim) operation. table 23-9 umsel1 register bits register bits value description 0x00 asynchronous usart 0x01 synchronous usart 0x02 reserved umsel11:10 0x03 master spi (mspim) ? bit 5:4 ? upm11:10 - parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter will automatically generate and send th e parity of the transmitted data bits within each frame. the receiver will generate a par ity value for the incoming data and compare it to the upm1 setting. if a mismatch is de tected, the upe1 flag in ucsr1a will be set. table 23-10 upm1 register bits register bits value description 0x00 disabled 0x01 reserved 0x02 enabled, even parity upm11:10 0x03 enabled, odd parity ? bit 3 ? usbs1 - stop bit select this bit selects the number of stop bits to be inse rted by the transmitter. the receiver ignores this setting. 365 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 23-11 usbs1 register bits register bits value description 0x00 1-bit usbs1 0x01 2-bit ? bit 2:1 ? ucsz11:10 - character size the ucsz11:0 bits combined with the ucsz12 bit in u csr1b sets the number of data bits (character size) in the frame that the receive r and transmitter use. table 23-12 ucsz1 register bits register bits value description 0 5-bit 1 6-bit 2 7-bit 3 8-bit 4 reserved 5 reserved 6 reserved ucsz12:10 7 9-bit ? bit 0 ? ucpol1 - clock polarity this bit is used for synchronous mode only. write t his bit to zero when asynchronous mode is used. the ucpol1 bit sets the relationship between data output change and data input sample, and the synchronous clock (xck1) . table 23-13 ucpol1 register bits register bits value description 0 rising xckn edge (transmitted data changed), falling xckn edge (received data sampled) ucpol1 1 falling xckn edge (transmitted data changed), rising xckn edge (received data sampled) 23.10.11 ubrr1h ? usart1 baud rate register high by te bit 7 6 5 4 3 2 1 0 na ($cd) res3 res2 res1 res0 ubrr11 ubrr10 ubrr9 ubrr8 ubrr1h read/write r r r r rw rw rw rw initial value 0 0 0 0 0 0 0 0 ubrr1 is a 12-bit register which contains the usart baud rate. the ubrr1h contains the four most significant bits, and the ub rr1l contains the eight least significant bits of the usart baud rate. ongoing tr ansmissions by the transmitter and receiver will be corrupted if the baud rate is chan ged. writing ubrr1l will trigger an immediate update of the baud rate prescaler. ? bit 7:4 ? res3:0 - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. 366 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 3:0 ? ubrr11:8 - usart baud rate register these bits represent bits [11:8] of the baud rate r egister. sample values for commonly used clock frequencies can be found in sec tion "examples of baud rate setting". 23.10.12 ubrr1l ? usart1 baud rate register low byt e bit 7 6 5 4 3 2 1 0 na ($cc) ubrr7 ubrr6 ubrr5 ubrr4 ubrr3 ubrr2 ubrr1 ubrr0 ubr r1l read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ubrr1 is a 12-bit register which contains the usart baud rate. the ubrr1h contains the four most significant bits, and the ub rr1l contains the eight least significant bits of the usart baud rate. ongoing tr ansmissions by the transmitter and receiver will be corrupted if the baud rate is chan ged. writing ubrr1l will trigger an immediate update of the baud rate prescaler. ? bit 7:0 ? ubrr7:0 - usart baud rate register these bits represent bits [7:0] of the baud rate re gister. sample values for commonly used clock frequencies can be found in section "exa mples of baud rate setting". 23.11 examples of baud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using th e ubrr settings in table 23-14 below to table 23-16 on page 368. ubrr values which yield an actual baud r ate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frame s (see "asynchronous operational range" on page 354 ). the error values are calculated using the follow ing equation: [ ] % 100 1 % ? ? ?? ? ? ?? ? ? = baudrate baudrate error match closest table 23-14. examples of ubrr n settings for commonly used oscillator frequencies f osc = 1.8432 mhz f osc = 2.0000 mhz f osc = 3.6864 mhz u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 baud rate (bps) ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0 .0% 4800 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0 % 9600 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0 % 14.4k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0 % 19.2k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0 % 28.8k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 38.4k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 367 8266c-mcu wireless-08/11 ATMEGA128RFA1 f osc = 1.8432 mhz f osc = 2.0000 mhz f osc = 3.6864 mhz u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 baud rate (bps) ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 57.6k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 76.8k 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 115.2k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 230.4k - - 0 0.0% - - - - 0 0.0% 1 0.0% 250k - - - - - - 0 0.0%% 0 -7.8% 1 -7.8% max. (1) 115.2 kbps 230.4 kbps 125 kbps 250 kbps 230.4 kbps 460.8 kbps notes: 1. ubrr = 0, error = 0.0% table 23-15. examples of ubrr n settings for commonly used oscillator frequencies (continued) f osc = 4.0000 mhz f osc = 7.3728 mhz f osc = 8.0000 mhz u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 baud rate (bps) ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 103 0.2% 207 0.2% 191 0.0% 383 0.0% 207 0.2% 4 16 -0.1% 4800 51 0.2% 103 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 9600 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0. 2% 14.4k 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 19.2k 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0. 2% 28.8k 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 16 2.1% 34 -0 .8% 38.4k 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0. 2% 57.6k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 76.8k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 115.2k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 230.4k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 250k 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 0.5m - - 0 0.0% 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1m - - - - - - 0 -7.8% - - 0 0.0% max. (1) 250 kbps 0.5 mbps 460.8 kbps 921.6 kbps 0.5 mbps 1 mbps notes: 1. ubrr = 0, error = 0.0% 368 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 23-16. examples of ubrr n settings for commonly used oscillator frequencies (continued) f osc = 11.0592 mhz f osc = 14.7456 mhz f osc = 16.0000 mhz u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 u2x n = 0 u2x n = 1 baud rate (bps) ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 287 0.0% 575 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 143 0.0% 287 0.0% 191 0.0% 383 0.0% 207 0.2% 4 16 -0.1% 9600 71 0.0% 143 0.0% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 47 0.0% 95 0.0% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 35 0.0% 71 0.0% 47 0.0% 95 0.0% 51 0.2% 103 0 .2% 28.8k 23 0.0% 47 0.0% 31 0.0% 63 0.0% 34 -0.8% 68 0 .6% 38.4k 17 0.0% 35 0.0% 23 0.0% 47 0.0% 25 0.2% 51 0. 2% 57.6k 11 0.0% 23 0.0% 15 0.0% 31 0.0% 16 2.1% 34 -0 .8% 76.8k 8 0.0% 17 0.0% 11 0.0% 23 0.0% 12 0.2% 25 0.2 % 115.2k 5 0.0% 11 0.0% 7 0.0% 15 0.0% 8 -3.5% 16 2.1 % 230.4k 2 0.0% 5 0.0% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 3 0.0% 7 0.0% 0.5m - - 2 -7.8% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 1m - - - - 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% max. (1) 691.2 kbps 1.3824 mbps 921.6 kbps 1.8432 mbps 1 mbp s 2 mbps notes: 1. ubrr = 0, error = 0.0% 369 8266c-mcu wireless-08/11 ATMEGA128RFA1 24 usart in spi mode the universal synchronous and asynchronous serial r eceiver and transmitter (usart) can be set to a master spi compliant mode o f operation. the master spi mode (mspim) has the following features: ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1 , 2, and 3) ? lsb first or msb first data transfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operation (f xck,max = f ck /2) ? flexible interrupt generation 24.1 overview setting both umseln1:0 bits to one enables the usar t in mspim logic. in this mode of operation the spi master control logic takes dir ect control over the usart resources. these resources include the transmitter and receiver shift register and buffers, and the baud rate generator. the parity ge nerator and checker, the data and clock recovery logic, and the rx and tx control log ic is disabled. the usart rx and tx control logic is replaced by a common spi transf er control logic. however, the pin control logic and interrupt generation logic is ide ntical in both modes of operation. the i/o register locations are the same in both mod es. however, some of the functionality of the control registers changes when using mspim. 24.2 usart mspim vs. spi the ATMEGA128RFA1 usart in mspim mode is fully comp atible with the ATMEGA128RFA1 spi regarding: ? master mode timing diagram. ? the ucpoln bit functionality is identical to the s pi cpol bit. ? the ucphan bit functionality is identical to the s pi cpha bit. ? the udordn bit functionality is identical to the s pi dord bit. however, since the usart in mspim mode reuses the u sart resources, the use of the usart in mspim mode is somewhat different compa red to the spi. in addition to differences of the control register bits, and that only master operation is supported by the usart in mspim mode, the following features dif fer between the two modules: ? the usart in mspim mode includes (double) bufferin g of the transmitter. the spi has no buffer. ? the usart in mspim mode receiver includes an addit ional buffer level. ? the spi wcol (write collision) bit is not included in usart in mspim mode. ? the spi double speed mode (spi2x) bit is not inclu ded. however, the same effect is achieved by setting ubrrn accordingly. ? interrupt timing is not compatible. ? pin control differs due to the master only operati on of the usart in mspim mode. a comparison of the usart in mspim mode and the spi pins is shown in table 24?3 on page 374. 370 8266c-mcu wireless-08/11 ATMEGA128RFA1 24.2.1 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal clo ck generation (i.e. master operation) is supported. the data direction registe r for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for t he usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous master mode. the baud rate or ubrrn set ting can therefore be calculated using the same equations, see table 24-1 below : table 24-1. equations for calculating baud rate register settin g operating mode equation for calculating baud rate (1) equation for calculating ubrr value synchronous master mode )1 (2 + = ubrrn f baud osc 1 2 ? = baud f ubrrn osc note: the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrhn and ubrrln registers, (0-4 095) 24.3 spi data modes and timing there are four combinations of xckn (sck) phase and polarity with respect to serial data, which are determined by control bits ucphan a nd ucpoln. the data transfer timing diagrams are shown in figure 24-1 below . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring s ufficient time for data signals to stabilize. the ucpoln and ucphan functionality is s ummarized in table 24-2 below . note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter . figure 24-1. ucphan and ucpoln data transfer timing diagrams xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 table 24-2. ucpoln and ucphan functionality ucpoln ucphan spi mode leading edge trailing ed ge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 371 8266c-mcu wireless-08/11 ATMEGA128RFA1 ucpoln ucphan spi mode leading edge trailing ed ge 1 1 3 setup (falling) sample (rising) 24.4 frame formats a serial frame for the mspim is defined to be one c haracter of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant d ata bit. then the next data bits, up to a total of eight, are succeeding, ending with the mos t or least significant bit accordingly. when a complete frame is transmitted, a new frame c an directly follow it, or the communication line can be set to an idle (high) sta te. the udordn bit in ucsrnc sets the frame format used by the usart in mspim mode. the receiver and transmitter use the same set ting. note that changing the setting of any of these bits will corrupt all ongoi ng communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udrn. a uart transmit complete interrupt will then signal that t he 16-bit value has been shifted out. 24.4.1 usart mspim initialization the usart in mspim mode has to be initialized befor e any communication can take place. the initialization process normally consists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to on e), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate independently. for interrupt driven usart operation , the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initialization of the xck n output the baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. setting ubrrn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a r eset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmi tter has completed all transfers, and the rxcn flag can be used to check that there a re no unread data in the receive buffer. note that the txcn flag must be cleared bef ore each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code exam ples show one assembly and one c function that are equal in functionality. the exa mples assume polling (no interrupts enabled). the baud rate is given as a function para meter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 372 8266c-mcu wireless-08/11 ATMEGA128RFA1 assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 375 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 5 ? udre0 - usart data register empty the udre0 flag indicates if the transmit buffer (ud r0) is ready to receive new data. if udre0 is one, the buffer is empty, and therefore re ady to be written. the udre0 flag can generate a data register empty interrupt (see d escription of the udrie0 bit). udre0 is set after a reset to indicate that the tra nsmitter is ready. 24.6.4 ucsr0b ? usart0 mspim control and status reg ister b bit 7 6 5 4 3 2 1 0 na ($c1) rxcie0 txcie0 udrie0 rxen0 txen0 ucsr0b read/write rw rw rw rw rw initial value 0 0 1 0 0 ? bit 7 ? rxcie0 - rx complete interrupt enable writing this bit to one enables interrupt on the rx c0 flag. a usart receive complete interrupt will be generated only if the rxcie0 bit is written to one, the global interrupt flag in sreg is written to one and the rxc0 bit in ucsr0a is set. ? bit 6 ? txcie0 - tx complete interrupt enable writing this bit to one enables interrupt on the tx c0 flag. a usart transmit complete interrupt will be generated only if the txcie0 bit is written to one, the global interrupt flag in sreg is written to one and the txc0 bit in ucsr0a is set. ? bit 5 ? udrie0 - usart data register empty interrup t enable writing this bit to one enables interrupt on the ud re0 flag. a data register empty interrupt will be generated only if the udrie0 bit is written to one, the global interrupt flag in sreg is written to one and the udre0 bit in ucsr0a is set. ? bit 4 ? rxen0 - receiver enable writing this bit to one enables the usart receiver in mspim mode. the receiver will override normal port operation for the rxd0 pin whe n enabled. disabling the receiver will flush the receive buffer. only enabling the re ceiver in mspi mode (i.e. setting rxen0=1 and txen0=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is suppor ted. ? bit 3 ? txen0 - transmitter enable writing this bit to one enables the usart transmitt er. the transmitter will override normal port operation for the txd0 pin when enabled . the disabling of the transmitter (writing txen0 to zero) will not become effective u ntil ongoing and pending transmissions are completed, i.e., when the transmi t shift register and transmit buffer register do not contain data to be transmitted. whe n disabled, the transmitter will no longer override the txd0 port. 24.6.5 ucsr0c ? usart0 mspim control and status reg ister c bit 7 6 5 4 3 2 1 0 na ($c2) udord0 ucpha0 ucpol0 ucsr0c read/write rw rw rw initial value 1 1 0 ? bit 2 ? udord0 - data order 376 8266c-mcu wireless-08/11 ATMEGA128RFA1 when set to one the lsb of the data word is transmi tted first. when set to zero the msb of the data word is transmitted first. refer to section "frame formats" for details. ? bit 1 ? ucpha0 - clock phase the ucpha0 bit setting determines if data is sample d on the leading (first) or tailing (last) edge of xck0. refer to the section "spi data modes and timing" for details. ? bit 0 ? ucpol0 - clock polarity the ucpol0 bit sets the polarity of the xck0 clock. the combination of the ucpol0 and ucpha0 bit settings determine the timing of the data transfer. refer to the section "spi data modes and timing" for details. 24.6.6 ucsr1a ? usart1 mspim control and status reg ister a bit 7 6 5 4 3 2 1 0 na ($c8) rxc1 txc1 udre1 ucsr1a read/write r rw r initial value 0 0 0 ? bit 7 ? rxc1 - usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and co nsequently the rxc1 bit will become zero. the rxc1 flag can be used to generate a recei ve complete interrupt (see description of the rxcie1 bit). ? bit 6 ? txc1 - usart transmit complete this flag bit is set when the entire frame in the t ransmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udr1). the txc1 flag bit is automatically cleared when a trans mit complete interrupt is executed, or it can be cleared by writing a one to its bit lo cation. the txc1 flag can generate a transmit complete interrupt (see description of the txcie1 bit). ? bit 5 ? udre1 - usart data register empty the udre1 flag indicates if the transmit buffer (ud r1) is ready to receive new data. if udre1 is one, the buffer is empty, and therefore re ady to be written. the udre1 flag can generate a data register empty interrupt (see d escription of the udrie1 bit). udre1 is set after a reset to indicate that the tra nsmitter is ready. 24.6.7 ucsr1b ? usart1 mspim control and status reg ister b bit 7 6 5 4 3 2 1 0 na ($c9) rxcie1 txcie1 udrie1 rxen1 txen1 ucsr1b read/write rw rw rw rw rw initial value 0 0 1 0 0 ? bit 7 ? rxcie1 - rx complete interrupt enable writing this bit to one enables interrupt on the rx c1 flag. a usart receive complete interrupt will be generated only if the rxcie1 bit is written to one, the global interrupt flag in sreg is written to one and the rxc1 bit in ucsr1a is set. 377 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 6 ? txcie1 - tx complete interrupt enable writing this bit to one enables interrupt on the tx c1 flag. a usart transmit complete interrupt will be generated only if the txcie1 bit is written to one, the global interrupt flag in sreg is written to one and the txc1 bit in ucsr1a is set. ? bit 5 ? udrie1 - usart data register empty interrup t enable writing this bit to one enables interrupt on the ud re1 flag. a data register empty interrupt will be generated only if the udrie1 bit is written to one, the global interrupt flag in sreg is written to one and the udre1 bit in ucsr1a is set. ? bit 4 ? rxen1 - receiver enable writing this bit to one enables the usart receiver in mspim mode. the receiver will override normal port operation for the rxd1 pin whe n enabled. disabling the receiver will flush the receive buffer. only enabling the re ceiver in mspi mode (i.e. setting rxen1=1 and txen1=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is suppor ted. ? bit 3 ? txen1 - transmitter enable writing this bit to one enables the usart transmitt er. the transmitter will override normal port operation for the txd1 pin when enabled . the disabling of the transmitter (writing txen1 to zero) will not become effective u ntil ongoing and pending transmissions are completed, i.e., when the transmi t shift register and transmit buffer register do not contain data to be transmitted. whe n disabled, the transmitter will no longer override the txd1 port. 24.6.8 ucsr1c ? usart1 mspim control and status reg ister c bit 7 6 5 4 3 2 1 0 na ($ca) udord1 ucpha1 ucpol1 ucsr1c read/write rw rw rw initial value 1 1 0 ? bit 2 ? udord1 - data order when set to one the lsb of the data word is transmi tted first. when set to zero the msb of the data word is transmitted first. refer to section "frame formats" for details. ? bit 1 ? ucpha1 - clock phase the ucpha1 bit setting determines if data is sample d on the leading (first) or tailing (last) edge of xck1. refer to the section "spi data modes and timing" for details. ? bit 0 ? ucpol1 - clock polarity the ucpol1 bit sets the polarity of the xck1 clock. the combination of the ucpol1 and ucpha1 bit settings determine the timing of the data transfer. refer to the section "spi data modes and timing" for details. 378 8266c-mcu wireless-08/11 ATMEGA128RFA1 25 2-wire serial interface 25.1 features ? simple yet powerful and flexible communication inte rface, only two bus lines needed ? both master and slave operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slav e addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus l ines ? fully programmable slave address with general call support ? address recognition causes wake-up when microcontro ller is in sleep mode 25.2 2-wire serial interface bus definition the 2-wire serial interface (twi) is ideally suited for typical microcontroller applications. the twi protocol allows the systems designer to int erconnect up to 128 different devices using only two bi-directional bus lines, on e for clock (scl) and one for data (sda). the only external hardware needed to impleme nt the bus is a single pull-up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus content ion are inherent in the twi protocol. figure 25-1. twi bus interconnection device 1 device 2 device 3 device n sda scl ........ r1 r2 devdd 25.2.1 twi terminology the following definitions are frequently encountere d in this section. table 25-1. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. 379 8266c-mcu wireless-08/11 ATMEGA128RFA1 the power reduction twi bit, prtwi bit in "prr0 ? power reduction register0" on page 169 must be written to zero to enable the 2-wire seria l interface. 25.2.2 electrical interconnection as depicted in figure 25-1 on page 378, both bus lines are connected to the posi tive supply voltage through pull-up resistors. the bus d rivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and function which is essential to the operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices trim-state their outputs, allowing the pull -up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave add ress space. a detailed specification of the electrical characteristics of the twi is giv en in "2-wire serial interface characteristics" on page 511 . two different sets of specifications are presente d there, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. 25.3 data transfer and frame format 25.3.1 transferring bits each data bit transferred on the twi bus is accompa nied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop condi tions. figure 25-2. data validity sda scl data stable data stable data change 25.3.2 start and stop conditions the master initiates and terminates a data transmis sion. the transmission is initiated when the master issues a start condition on the bus , and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued be tween a start and stop condition. this is referred to as a repeated start condition, and is used when the master wishes to initiate a new transfer without re linquishing control of the bus. after a repeated start, the bus is considered busy until th e next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signa led by changing the level of the sda line when the scl line is high. 380 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-3. start, repeated start and stop conditions sda scl start stop repeated start stop start 25.3.3 address packet format all address packets transmitted on the twi bus are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is to be performed, otherwise a write operation should be performed. when a slave recognizes that it is being addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the master?s requ est, the sda line should be left high in the ack clock cycle. the master can then tr ansmit a stop condition, or a repeated start condition to initiate a new transmis sion. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. s lave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should re spond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same message to several slaves in the system. when the g eneral call address followed by a write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack cycle. the followi ng data packets will then be received by all the slaves that acknowledged the general cal l. note that transmitting the general call address followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be rese rved for future purposes. figure 25-4. address packet format sda scl start 1 2 7 8 9 addr msb addr lsb r/w ack 25.3.4 data packet format all data packets transmitted on the twi bus are nin e bits long, consisting of one data byte and an acknowledge bit. during a data transfer , the master generates the clock and the start and stop conditions, while the receiv er is responsible for acknowledging the reception. an acknowledge (ack) i s signaled by the receiver 381 8266c-mcu wireless-08/11 ATMEGA128RFA1 pulling the sda line low during the ninth scl cycle . if the receiver leaves the sda line high, a nack is signaled. when the receiver has rec eived the last byte, or for some reason cannot receive any more bytes, it should inf orm the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 25-5. data packet format 1 2 7 8 9 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 25.3.5 combining address and data packets into a tr ansmission a transmission basically consists of a start condit ion, a sla+r/w, one or more data packets and a stop condition. an empty message, con sisting of a start followed by a stop condition, is illegal. note that the wired-a nding of the scl line can be used to implement handshaking between the master and the sl ave. the slave can extend the scl low period by pulling the scl line low. this is useful if the clock speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. the slave extending the scl low period will not affect the scl high period, which is determined by the mas ter. as a consequence, the slave can reduce the twi data transfer speed by prolongin g the scl duty cycle. figure 25-6 below shows a typical data transmission. note that sever al data bytes can be transmitted between the sla+r/w and the stop con dition, depending on the software protocol implemented by the application so ftware. figure 25-6. typical data transmission 1 2 7 8 9 data byte data msb data lsb ack sda scl start 1 2 7 8 9 addr msb addr lsb r/w ack sla+r/w stop 25.4 multi-master bus systems, arbitration and sync hronization the twi protocol allows bus systems with several ma sters. special concerns have been taken in order to ensure that transmissions wi ll proceed as normal, even if two or more masters initiate a transmission at the same ti me. two problems arise in multi- master systems: 382 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transm ission when they discover that they have lost the selection process. this selectio n process is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether i t is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i .e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencie s. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will facilitate the arbitration process. the wired-anding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-anded, yieldi ng a combined clock with a high period equal to the one from the master with the sh ortest high period. the low period of the combined clock is equal to the low period of th e master with the longest low period. note that all masters listen to the scl line, effec tively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 25-7. scl synchronization between multiple masters ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period arbitration is carried out by all masters continuou sly monitoring the sda line after outputting data. if the value read from the sda lin e does not match the value the master had output, it has lost the arbitration. not e that a master can only lose arbitration when it outputs a high sda value while another mast er outputs a low value. the losing master should immediately go to slave mode, checkin g if it is being addressed by the winning master. the sda line should be left high, b ut losing masters are allowed to generate a clock signal until the end of the curren t data or address packet. arbitration will continue until only one master remains, and th is may take many bits. if several masters are trying to address the same slave, arbit ration will continue into the data packet. note that arbitration is not allowed between: ? a repeated start condition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s responsibility to ensure that these illegal arbitration conditions never occur. this implies that in multi-master syst ems, all data transfers must use the same composition of sla+r/w and data packets. in ot her words: all transmissions 383 8266c-mcu wireless-08/11 ATMEGA128RFA1 must contain the same number of data packets, other wise the result of the arbitration is undefined. figure 25-8. arbitration between two masters sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 25.5 overview of the twi module the twi module is comprised of several sub-modules, as shown in figure 25-9 below . all registers drawn in a thick line are accessible through the avr data bus. figure 25-9. overview of the twi module twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 384 8266c-mcu wireless-08/11 ATMEGA128RFA1 25.5.1 scl and sda pins these pins interface the avr twi with the rest of t he mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes sh orter than 50 ns. note that the internal pull-ups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 25.5.2 bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is controlled by settings in the twi bit rate regis ter (twbr) and the prescaler bits in the twi status register (twsr). slave operation doe s not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ( ) twps twbr frequency clock cpu frequency scl 4 2 16 ? + = ? twbr = value of the twi bit rate register. ? twps = value of the prescaler bits in the twi stat us register. note that pull-up resistor values should be selecte d according to the scl frequency and the capacitive bus line load. see in "2-wire serial interface characteristics" on page 511 for value of pull-up resistor. 25.5.3 bus interface unit this unit contains the data and address shift regis ter (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data byt es received. in addition to the 8-bit twdr, the bus interface unit also contains a regist er containing the (n)ack bit to be transmitted or received. this (n)ack register is no t directly accessible by the application software. however, when receiving, it c an be set or cleared by manipulating the twi control register (twcr). when in transmitte r mode, the value of the received (n)ack bit can be determined by the value in the tw sr. the start/stop controller is responsible for genera tion and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hardware continuously monitors the transmission trying to de termine if arbitration is in process. if the twi has lost an arbitration, the control unit i s informed. correct action can then be taken and appropriate status codes generated. 25.5.4 address match unit the address match unit checks if received address b ytes match the seven-bit address in the twi address register (twar). if the twi gene ral call recognition enable (twgce) bit in the twar is written to one, all inco ming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. t he twi may or may not acknowledge its address, depending on settings in the twcr. the address match unit is able to 385 8266c-mcu wireless-08/11 ATMEGA128RFA1 compare addresses even if the avr mcu is in sleep m ode, enabling the mcu to wake up if addressed by a master. if another interrupt ( e.g., int0) occurs during twi power- down address match and wakes up the cpu, the twi ab orts operation and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down. 25.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when a n event requiring the attention of the application occurs on the twi bus, the twi inte rrupt flag (twint) is asserted. in the next clock cycle, the twi status register (twsr ) is updated with a status code identifying the event. the twsr only contains relev ant status information when the twi interrupt flag is asserted. at all other times, the twsr contains a special status code indicating that no relevant status information is available. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before allowing the twi transmission to conti nue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated sta rt condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave addr ess or general call. ? after the twi has received a data byte. ? after a stop or repeated start has been received w hile still addressed as a slave. ? when a bus error has occurred due to an illegal st art or stop condition. 25.6 using the twi the ATMEGA128RFA1 twi is byte-oriented and interru pt based. interrupts are issued after all bus events, like reception of a byte or t ransmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that th e twi interrupt enable (twie) bit in twcr together with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag s hould generate an interrupt request. if the twie bit is cleared, the applicatio n must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finish ed an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the current state of the twi bus. the ap plication software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 25-10 on page 386 is a simple example of how the applicatio n can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more d etailed explanation follows later in this section. a simple code example implementing the des ired behavior is also presented. 386 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-10. interfacing the application to the twi in a typical transmission start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 1. the first step in a twi transmission is to trans mit a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. wri ting a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint , the twi will initiate transmission of the start condition. 2. when the start condition has been transmitted, t he twint flag in twcr is set, and twsr is updated with a status code indicating t hat the start condition has successfully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. i f twsr indicates otherwise, the application software might take some special action , like calling an error routine. assuming that the status code is as expected, the a pplication must load sla+w into twdr. remember that twdr is used both for address a nd data. after twdr has been loaded with the desired sla+w, a specific valu e must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is impo rtant that the twint bit is set in the value written. writing a one to twint clears the fl ag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmissi on of the address packet. 4. when the address packet has been transmitted, th e twint flag in twcr is set, and twsr is updated with a status code indicating t hat the address packet has successfully been sent. the status code will also r eflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, an d that the value of the ack bit was as expected. if twsr indicates otherwise, the a pplication software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load a data packet i nto twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write i s described later on. however, it is important that the twint bit is set in the value written. writing a one to twint 387 8266c-mcu wireless-08/11 ATMEGA128RFA1 clears the flag. the twi will not start any operati on as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the t wint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflect whethe r a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and t hat the value of the ack bit was as expected. if twsr indicates otherwise, the appli cation software might take some special action, like calling an error routine. assu ming that the status code is as expected, the application must write a specific val ue to twcr, instructing the twi hardware to transmit a stop condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start an y operation as long as the twint bit in twcr is set. immediately after the applicati on has cleared twint, the twi will initiate transmission of the stop condition. n ote that twint is not set after a stop condition has been sent. even though this example is simple, it shows the pr inciples involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is cleared. ? when the twint flag is set, the user must update a ll twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending a pplication software tasks have been completed, twcr is written. when writing twcr, the twint bit should be set. writing a one to twint clears the flag. the tw i will then commence executing whatever operation was specified by the twcr settin g. in the following an assembly and c implementation o f the example is given. note that the code below assumes that several definitions hav e been made, for example by using include-files. table 25-2. code example assembly code example c example comments 1 ldi r16,(1< 390 8266c-mcu wireless-08/11 ATMEGA128RFA1 twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 0 x 1 0 x this scheme is repeated until the last byte has bee n sent and the transfer is ended by generating a stop condition or a repeated start con dition. a stop condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 1 x 1 0 x a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value x 1 0 x 1 0 x after a repeated start condition (state 0x10) the 2 -wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing contro l of the bus. figure 25-12. formats and states in the master transmitter mode s sla w a data a p $08 $18 $28 r sla w $10 a p $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s 391 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 25-3. status codes for master transmitter mode application software response to twcr status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware to/from twdr sta sto twint twea next action taken by twi hardware 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte o no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be rese stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus be-comes free 25.7.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (for slave see figure 25-13 on page 392). in order to enter a master mode, a start condition must be transmitted. the format o f the following address packet determines whether master transmitter or master rec eiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this sec tion assume that the prescaler bits are zero or are masked to zero. 392 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-13. data transfer in master receiver mode device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 devdd a start condition is sent by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x twen must be written to one to enable the 2-wire se rial interface, twsta must be written to one to transmit a start condition and tw int must be set to clear the twint flag. the twi will then test the 2-wire seria l bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 25-4 on page 393). in order to enter mr mode, sla+r must b e transmitted. this is done by writing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the t ransfer. this is accomplished by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 0 x 1 0 x when sla+r have been transmitted and an acknowledge ment bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48 . the appropriate action to be taken for each of these status codes is detailed in table 25-4 on page 393. received data can be read from the twdr register when the tw int flag is set high by hardware. this scheme is repeated until the last by te has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by genera ting a stop condition or a repeated start condition. a stop condition is generated by w riting the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 1 x 1 0 x a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x after a repeated start condition (state 0x10) the 2 -wire serial interface can access the same slave again, or a new slave without transm itting a stop condition. repeated 393 8266c-mcu wireless-08/11 ATMEGA128RFA1 start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over th e bus. table 25-4. status codes for master receiver mode application software response to twcr status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware to/from twdr sta std twint twea next action taken by twi hardware 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack o r not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or notack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 394 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-14. formats and states in the master receiver mode s sla r a data a $08 $40 $50 sla r $10 a p $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfullreception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a $58 a r s 25.7.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 25-15 below ). all the status codes mentioned in this section assume that the prescaler bits are zero or are mask ed to zero. figure 25-15. data transfer in slave receiver mode device 3 device n sda scl ........ r1 r2 devdd device 2 master transmitter device 1 slave receiver to initiate the slave receiver mode, twar and twcr must be initialized as follows: twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twg ce value device?s own slave address 395 8266c-mcu wireless-08/11 ATMEGA128RFA1 the upper 7 bits are the address to which the 2-wir e serial interface will respond when addressed by a master. if the lsb is set, the twi w ill respond to the general call address (0x00), otherwise it will ignore the genera l call address. twcr twint twea twsta twsto twwc twen ? twie value 0 1 0 0 0 1 0 x twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own s lave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi w aits until it is addressed by its own slave address (or the general call address if e nabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi w ill operate in sr mode, otherwise st mode is entered. after its own slave address and the wri te bit have been received, the twint flag is set and a valid status code can be read fro m twsr. the status code is used to determine the appropriate software action. the appr opriate action to be taken for each status code is detailed in table 25-5 below . the slave receiver mode may also be entered if arbitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is z ero, the twi does not acknowledge its own slave address. however, the 2-w ire serial bus is still monitored and address recognition may resume at any time by s etting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledg e its own slave address or the general call address by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be carried out as normal, with the avr clocks runni ng as normal. observe that if the avr is set up with a long start-up time, the scl li ne may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these s leep modes. table 25-5. status codes for slave receiver mode application software response to twcr status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware to/from twdr sta sto twint twea next action taken by twi hardware 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 396 8266c-mcu wireless-08/11 ATMEGA128RFA1 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re-ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 397 8266c-mcu wireless-08/11 ATMEGA128RFA1 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free figure 25-16. formats and states in the slave receiver mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a 25.7.4 slave transmitter mode in the slave transmitter mode, a number of data byt es are transmitted to a master receiver (see figure 25-17 on page 398). all the status codes mentioned in this section assume that the prescaler bits are zero or are mask ed to zero. 398 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-17. data transfer in slave transmitter mode device 3 device n sda scl ........ r1 r2 devdd device 2 master receiver device 1 slave transmitter to initiate the slave transmitter mode, twar and tw cr must be initialized as follows: twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twg ce value device?s own slave address the upper seven bits are the address to which the 2 -wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the genera l call address. twcr twint twea twsta twsto twwc twen ? twie value 0 1 0 0 0 1 0 x twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own s lave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi w aits until it is addressed by its own slave address (or the general call address if e nabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi wi ll operate in st mode, otherwise sr mode is entered. after its own slave address and the wri te bit have been received, the twint flag is set and a valid status code can be read fro m twsr. the status code is used to determine the appropriate software action. the appr opriate action to be taken for each status code is detailed in table 25-6 on page 399. the slave transmitter mode may also be entered if arbitration is lost while the tw i is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfe r, the twi will transmit the last byte of the transfer. state 0xc0 or state 0xc8 will be ente red, depending on whether the master receiver transmits a nack or ack after the f inal byte. the twi is switched to the not addressed slave mode, and will ignore the m aster if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitti ng ack), even though the slave has transmitted the last byte (twea zero and expect ing nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the 2-wire serial bus is still monitored and address re cognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledg e its own slave address or the general call address by using the 2-wire serial bus clock as a clock source. the part 399 8266c-mcu wireless-08/11 ATMEGA128RFA1 will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by wri ting it to one). further data transmission will be carried out as normal, with th e avr clocks running as normal. observe that if the avr is set up with a long start -up time, the scl line may be held low for a long time, blocking other data transmissi ons. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these s leep modes. table 25-6. status code for slave transmitter mode application software response to twcr status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware to/from twdr sta std twint twea next action taken by twi hardware 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 400 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 25-18. formats and states in the slave transmitter mode s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = 0) arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1s a 25.7.5 miscellaneous states there are two status codes that do not correspond t o a defined twi state, see table 25-7 below . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and w hen the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2-wire serial bus transfer. a bus error occurs when a start or stop condition o ccurs at an illegal position in the format frame. examples of such illegal positions ar e during the serial transfer of an address byte, a data byte, or an acknowledge bit. w hen a bus error occurs, twint is set. to recover from a bus error, the twsto flag mu st set and twint must be cleared by writing a logic one to it. this causes t he twi to enter the not addressed slave mode and to clear the twsto flag (no other bi ts in twcr are affected). the sda and scl lines are released, and no stop conditi on is transmitted. table 25-7. miscellaneous states application software response to twcr status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware to/from twdr sta sto twint twea next action taken by twi hardware 0xf8 no relevant state information available twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi-tion is sent on the bus. in all cases, the bus is released and twsto is cleared. 25.7.6 combining several twi modes in some cases, several twi modes must be combined i n order to complete the desired action. consider for example reading data from a se rial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location shou ld be read. 401 8266c-mcu wireless-08/11 ATMEGA128RFA1 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to s lave and vice versa. the master must instruct the slave what location it wants to r ead, requiring the use of the mt mode. subsequently, data must be read from the slave, imp lying the use of the mr mode. thus, the transfer direction must be changed. the m aster must keep control of the bus during all these steps, and the steps should be car ried out as an atomic operation. if this principle is violated in a multi-master system , another master can alter the data pointer in the eeprom between steps 2 and 3, and th e master will read the wrong data location. such a change in transfer direction is ac complished by transmitting a repeated start between the transmission of the addr ess byte and reception of the data. after a repeated start, the master keeps owne rship of the bus. the following figure shows the flow in this transfer. figure 25-19. combining several twi modes to access a serial eepr om master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p 25.8 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. the twi stan dard ensures that such situations are handled in such a way that one of the masters w ill be allowed to proceed with the transfer, and that no data will be lost in the proc ess. an example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. figure 25-20. an arbitration example device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 devdd several different scenarios may arise during arbitr ation, as described below: ? two or more masters are performing identical commu nication with the same slave. in this case, neither the slave nor any of the mast ers will know about the bus contention. ? two or more masters are accessing the same slave w ith different data or direction bit. in this case, arbitration will occur, either i n the read/write bit or in the data bits. the masters trying to output a one on sda whi le another master outputs a zero 402 8266c-mcu wireless-08/11 ATMEGA128RFA1 will lose the arbitration. losing masters will swit ch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. ? two or more masters are accessing different slaves . in this case, arbitration will occur in the sla bits. masters trying to output a o ne on sda while another master outputs a zero will lose the arbitration. masters l osing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depen ding on the value of the read/write bit. if they are not being addressed, th ey will switch to not addressed slave mode or wait until the bus is free and transm it a new start condition, depending on application software action. this is summarized in figure 25-21 below . possible status values are given in circles. figure 25-21. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction yes write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 25.9 register description 25.9.1 twbr ? twi bit rate register bit 7 6 5 4 3 2 1 0 na ($b8) twbr7:0 twbr read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the scl period is controlled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). s lave operation does not depend on bit rate or prescaler settings, but the cpu clock f requency in the slave must be at least 16 times higher than the scl frequency. ? bit 7:0 ? twbr7:0 - twi bit rate register value the twbr register selects the division factor for t he bit rate generator. the bit rate generator is a frequency divider which generates th e scl clock frequency in the master modes. see section "bit rate generator unit" for ca lculating bit rates. 403 8266c-mcu wireless-08/11 ATMEGA128RFA1 25.9.2 twcr ? twi control register bit 7 6 5 4 3 2 1 0 na ($bc) twint twea twsta twsto twwc twen res twie twcr read/write rw rw rw rw rw rw r rw initial value 0 0 0 0 0 0 0 0 the twcr is used to control the operation of the tw i. it is used to enable the twi, to initiate a master access by applying a start condit ion to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are put int o the twdr. it also indicates a write collision if data writing to twdr is attempted whil e the register is inaccessible. ? bit 7 ? twint - twi interrupt flag this bit is set by hardware when the twi has finish ed its current job and expects application software response. if the i-bit in sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while th e twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cle ared by hardware when executing the interrupt routine. also note that clearing this fla g starts the operation of the twi. so all accesses to the twi address register (twar), twi st atus register (twsr) and twi data register (twdr) must be complete before cleari ng this flag. ? bit 6 ? twea - twi enable acknowledge bit the twea bit controls the generation of the acknowl edge pulse. if the twea bit is written to one, the ack pulse is generated on the t wi bus if the following conditions are met: 1. the devices own slave address has been received; 2. a general call has been received, while the twgce bit in the twar is s et. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2 -wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta - twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hardware checks if the b us is available and generates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected and then generat es a new start condition to claim the bus master status. twsta must be cleared by sof tware when the start condition has been transmitted. ? bit 4 ? twsto - twi stop condition bit writing the twsto bit to one in master mode will ge nerate a stop condition on the 2- wire serial bus. when the stop condition is execute d on the bus, the twsto bit is cleared automatically. in slave mode, setting the t wsto bit can be used to recover from an error condition. this will not generate a s top condition, but the twi returns to a well-defined not-addressed slave mode and release s the scl and sda lines to a high impedance state. ? bit 3 ? twwc - twi write collision flag the twwc bit is set when attempting to write to the twi data register twdr when twint is low. this flag is cleared by writing the t wdr register when twint is high. ? bit 2 ? twen - twi enable bit the twen bit enables twi operation and activates th e twi interface. when twen is written to one, the twi takes control over the i/o ports connected to the scl and sda 404 8266c-mcu wireless-08/11 ATMEGA128RFA1 pins enabling the slew-rate limiters and spike filt ers. if this bit is written to zero, the twi is switched off and all twi transmissions are termi nated regardless of any ongoing operation. ? bit 1 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 0 ? twie - twi interrupt enable when this bit is written to one and the i-bit in sr eg is set, the twi interrupt request will be activated for as long as the twint flag is high. 25.9.3 twsr ? twi status register bit 7 6 5 4 3 2 1 0 na ($b9) tws7 tws6 tws5 tws4 tws3 res twps1 twps0 twsr read/write rw rw rw rw rw r rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:3 ? tws4:0 - twi status these 5 bits reflect the status of the twi logic an d the 2-wire serial bus. the different status codes for both transmitter and receiver mode are described in the following table. note that the value read from twsr contains both th e 5-bit status value and the 2-bit prescaler value. the application designer should ma sk the prescaler bits to zero when checking the status bits. this makes status checkin g independent of prescaler setting. this approach is used in this datasheet, unless oth erwise noted. table 25-8 tws register bits register bits value description 0x00 bus error due to illegal start or stop condition. 0x08 a start condition has been transmitted. 0x10 a repeated start condition has been transmitted. 0x18 sla+w has been transmitted; ack has been received. 0x20 sla+w has been transmitted; not ack has been received. 0x28 data byte has been transmitted; ack has been received. 0x30 data byte has been transmitted; not ack has been received. 0x38 arbitration lost in sla+w or data bytes (transmitter); arbitration lost in sla+r or not ack bit (receiver). 0x40 sla+r has been transmitted; ack has been received. 0x48 sla+r has been transmitted; not ack has been received. tws4:0 0x50 data byte has been received; ack has been 405 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description returned. 0x58 data byte has been received; not ack has been returned. 0x60 own sla+w has been received; ack has been returned. 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned. 0x70 general call address has been received; ack has been returned. 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned. 0x80 previously addressed with own sla+w; data has been received; ack has been returned. 0x88 previously addressed with own sla+w; data has been received; not ack has been returned. 0x90 previously addressed with general call; data has been received; ack has been returned. 0x98 previously addressed with general call; data has been received; not ack has been returned. 0xa0 a stop condition or repeated start condition has been received while still addressed as slave. 0xa8 own sla+r has been received; ack has been returned. 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned. 0xb8 data byte in twdr has been transmitted; ack has been received. 0xc0 data byte in twdr has been transmitted; no ack has been received. 0xc8 last data byte in twdr has been transmitted (twea = 0); ack has been received. 0xf8 no relevant state information available; twint = 0. ? bit 2 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 1:0 ? twps1:0 - twi prescaler bits these bits can be read and written and control the bit rate of the prescaler. table 25-9 twps register bits register bits value description twps1:0 0x00 1 406 8266c-mcu wireless-08/11 ATMEGA128RFA1 register bits value description 0x01 4 0x02 16 0x03 64 25.9.4 twdr ? twi data register bit 7 6 5 4 3 2 1 0 na ($bb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write rw rw rw rw rw rw rw rw initial value 1 1 1 1 1 1 1 1 in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is wri table while the twi is not in the process of shifting a byte. this occurs when the tw i interrupt flag (twint) is set by hardware. note that the data register cannot be ini tialized by the user before the first interrupt occurs. the data in twdr remains stable a s long as twint is set. while data is shifted out, data on the bus is simultaneously s hifted in. twdr always contains the last byte present on the bus, except after a wake u p from a sleep mode by the twi interrupt. in this case, the contents of twdr is un defined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is automatically controlled by the twi logic. the c pu cannot access the ack bit directly. ? bit 7:0 ? twd7:0 - twi data register byte 25.9.5 twar ? twi (slave) address register bit 7 6 5 4 3 2 1 0 na ($ba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the twar should be loaded with the 7-bit slave addr ess (in the seven most significant bits of twar) to which the twi will respond when pr ogrammed as a slave transmitter or receiver. this register is not needed in the mas ter modes. in multi-master systems twar must be set in masters which can be addressed as slaves by other masters. the lsb of twar is used to enable the recognition o f the general call address (0x00). there is an associated address comparator that look s for the slave address (or general call address if enabled) in the received serial add ress. if a match is found, an interrupt request is generated. ? bit 7:1 ? twa6:0 - twi (slave) address these bits contain the twi address operated as a sl ave device. ? bit 0 ? twgce - twi general call recognition enable bit if set, this bit enables the recognition of a gener al call given over the 2-wire serial bus. 407 8266c-mcu wireless-08/11 ATMEGA128RFA1 25.9.6 twamr ? twi (slave) address mask register bit 7 6 5 4 3 2 1 0 na ($bd) twam6 twam5 twam4 twam3 twam2 twam1 twam0 res twamr read/write rw rw rw rw rw rw rw r initial value 0 0 0 0 0 0 0 0 ? bit 7:1 ? twam6:0 - twi address mask the twamr can be loaded with a 7-bit slave address mask. each of the bits in twamr can mask (disable) the corresponding address bit in the twi address register (twar). if the mask bit is set to one then the addr ess match logic ignores the compare between the incoming address bit and the correspond ing bit in twar. ? bit 0 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. 408 8266c-mcu wireless-08/11 ATMEGA128RFA1 26 ac ? analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator out put, aco, is set. the comparator?s output can be set to trigger the timer/counter1 inp ut capture function. in addition, the comparator can trigger a separate interrupt, exclus ive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 26-1 below . the power reduction adc bit pradc in prr0 (see "prr0 ? power reduction register0" on page 169 ) must be disabled by writing a logical zero to be able to use the adc input multiplexer. figure 26-1. analog comparator block diagram note: 1. see table 26-1 below . 2. refer to figure 1-1 on page 2 and table 14-9 on page 199 for analog comparator pin placement. 26.1 analog comparator multiplexed input it is possible to select any of the adc7:0 pins as the negative input of the analog comparator. the adc multiplexer is used to select t his input and consequently the adc must be switched off to utilize this feature. i f the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is s witched off (aden in adcsra is zero), mux5 and mux2:0 in admux select the input pi n to replace the negative input to the analog comparator, as shown in table 26-1 below . if acme is cleared or aden is set, ain1 is applied to the negative input to th e analog comparator. table 26-1. analog comparator multiplexed input acme aden mux5 mux2:0 analog comparator negative in put 0 x x xxx ain1 1 1 x xxx ain1 1 0 0 000 adc0 1 0 0 001 adc1 1 0 0 010 adc2 1 0 0 011 adc3 1 0 0 100 adc4 409 8266c-mcu wireless-08/11 ATMEGA128RFA1 acme aden mux5 mux2:0 analog comparator negative in put 1 0 0 101 adc5 1 0 0 110 adc6 1 0 0 111 adc7 26.2 register description 26.2.1 acsr ? analog comparator control and status register bit 7 6 5 4 3 2 1 0 $30 ($50) acd acbg aco aci acie acic acis1 acis0 acsr read/write rw rw r rw rw rw rw rw initial value 0 0 na 0 0 0 0 0 ? bit 7 ? acd - analog comparator disable when this bit is written logic one, the power to th e analog comparator is switched off. this bit can be set at any time to turn off the ana log comparator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing t he acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg - analog comparator bandgap select when this bit is set, a fixed bandgap reference vol tage connects to the positive input of the analog comparator. when this bit is cleared, ai n0 is applied to the positive input of the analog comparator. when the bandgap reference i s used as the input of the analog comparator, it will take a certain time for the voltage to stabilize. if not stabilized, the first comparison may give a wrong v alue. see section "internal voltage reference" for details. ? bit 5 ? aco - analog compare output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1-2 clock cycles. ? bit 4 ? aci - analog comparator interrupt flag this bit is set by hardware when a comparator outpu t event triggers the interrupt mode defined by acis1 and acis0. the analog comparator i nterrupt routine is executed if the acie bit is set and the i-bit in sreg is set. a ci is cleared by hard-ware when executing the corresponding interrupt handling vect or. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie - analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog comparator interrupt is activated. when writ ten logic zero, the interrupt is disabled. ? bit 2 ? acic - analog comparator input capture enab le when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparat or output is in this case directly connected to the input capture front-end logic, mak ing the comparator utilize the noise canceler and edge select features of the timer/coun ter1 input capture interrupt. when written logic zero, no connection between the analo g comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mas k register (timsk1) must be set. 410 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bit 1:0 ? acis1:0 - analog comparator interrupt mod e select these bits determine which comparator events that t rigger the analog comparator interrupt. the different settings are shown in the following table. when changing the acis1/acis0 bits, the analog comparator interrupt m ust be disabled by clearing its interrupt enable bit in the acsr register. otherwis e an interrupt can occur when the bits are changed. table 26-2 acis register bits register bits value description 0x00 interrupt on toggle 0x01 reserved 0x02 interrupt on falling edge acis1:0 0x03 interrupt on rising edge 26.2.2 adcsrb ? adc control and status register b bit 7 6 5 4 3 2 1 0 na ($7b) acme adcsrb read/write rw initial value 0 ? bit 6 ? acme - analog comparator multiplexer enable when this bit is written logic one and the adc is s witched off (aden in adcsra is zero), the adc multiplexer defines the negative inp ut of the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see section "analog comparator multiplexed input". 26.2.3 didr1 ? digital input disable register 1 bit 7 6 5 4 3 2 1 0 na ($7f) ain1d ain0d didr1 read/write rw rw initial value 0 0 ? bit 1 ? ain1d - ain1 digital input disable when this bit is written logic one, the digital inp ut buffer on the ain1 pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1 pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce powe r consumption in the digital input buffer. ? bit 0 ? ain0d - ain0 digital input disable when this bit is written logic one, the digital inp ut buffer on the ain0 pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain0 pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce powe r consumption in the digital input buffer. 411 8266c-mcu wireless-08/11 ATMEGA128RFA1 27 adc ? analog to digital converter 27.1 features ? 10-bit resolution ? differential non-linearity is less than 0.5 lsb ? 2 lsb integral non-linearity ? 3 - 240 s conversion time ? up to 330 ksps (up to 570 ksps with 8-bit resolutio n) ? 8 multiplexed single ended input channels ? 11 differential input channels ? 2 differential input channels with an optional gain of 10x and 200x ? internal linear temperature sensor ? optional left adjustment for adc result readout ? 0 - v avdd adc input voltage range ? 0 - v evdd differential adc input voltage range ? selectable 1.5v, 1.6v or v avdd adc reference voltage ? free running or single conversion mode ? interrupt on adc conversion complete ? sleep mode noise canceller the ATMEGA128RFA1 features a 10-bit successive appr oximation adc. the adc is connected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs constructed from the pins of port f. the sin gle-ended voltage inputs refer to 0v (avss). the device also supports multiple differential volt age input combinations. two of the differential inputs (adc1 & adc0 and adc3 & adc2) a re equipped with a programmable gain stage, providing amplification st eps of 0 db (1x), 20 db (10x) or 46 db (200x) on the differential input voltage before the a/d conversion. the differential input channels are constructed of pairs out of the 8 single-ended inputs. they share a common negative terminal (adc0, adc1 or adc2), whil e most of the other adc inputs can be selected as the positive input terminal. if 1x or 10x gain is used, 8 bit resolution can be expected. if 200x gain is used, 6 bit resolu tion can be expected. the adc contains a sample and hold circuit which en sures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 27-1 on page 412. the analog components of the adc are supplied from the analog supply voltage avdd. avdd is generated from evdd by an internal voltage generator. the logic part of the adc is supplied from the digital supply voltage dvd d. dvdd is generated from devdd also by an internal voltage generator. internal reference voltages of nominally 1.5v, 1.6v or avdd (1.8v) are provided on- chip. the 1.6v reference is calibrated to 1 lsb d uring manufacturing. the reference voltage can be monitored at the aref pin. additiona l de-coupling capacitance at aref is not required. a high capacitive loading of aref will de-stabilize the internal reference voltage generation. an external reference voltage i n the range of 0 < v aref,ext v avdd may be used but must be supplied with a very low im pedance. the power reduction adc bit, pradc (see "prr0 ? power reduction register0" on page 169 ) must be disabled by writing a logical zero to ena ble the adc. 412 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-1. analog to digital converter block schematic 8-bit d atabu s ad c ctrl & status r egister b (adc sr b) ad c c trl & statu s reg ister c (adc sr c) adc multiplexer select (admu x) ad c c trl & status register a (ad csr a) trigger select adfr adsc adts [2:0] inte rrup t flags adif adie ad c on ver sion c omplete irq ad c data r eg ister (adc h/ad cl) 15 0 pr esc aler c on ver sion logic sta rt adps[2:0] adif aden adc[9:0] adsut[4:0] adtht[1:0] adlar m ux d ec oder mux[4:0] mux[5] refs[1:0] channel selection diff / gain select 10-bit dac sample & h old co mparator avd d aref internal reference (1.5v/1.6v) ad c[7:0] avss ba ndgap refere nce 1.2v tem pe ra ture s ens or adc[2:0] gain amplifier ad c multiplexer output drt vo lta ge sram 2 clamp acch 27.2 operation the adc converts an analog input voltage to a 10-bi t digital value through successive approximation. the minimum value represents 0v (con version result 0x000) and the maximum value in single ended mode represents the r eference voltage minus 1 lsb (conversion result 0x3ff). the reference voltage ca n be measured at the aref pin. the internal, generated reference voltage can have the values 1.5v, 1.6v or avdd where the 1.6v has the highest absolute accuracy. t he reference voltage is selected by writing to the refs n bits in the admux register. an external reference voltage can also be selected. such an external voltage must be supplied with a very low impedance r aref,ext (see "adc characteristics" on page 514 ). the load current i l,aref (see "adc characteristics" on page 514 ) seen by the external source is code dependent and changes in the course of the successive approximati on process (load current steps). the internal voltage reference (except avdd) must n ot be decoupled by an external capacitor. adding unnecessary external capacitance at the aref pin will cause instable operation of the internal reference voltage buffer and will not improve noise immunity. the analog input channel is selected by writing to the mux bits in admux and adcsrb. any of the adc input pins, as well as avss and a fixed bandgap voltage reference can be selected as single ended inputs to the adc. a choice of adc input 413 8266c-mcu wireless-08/11 ATMEGA128RFA1 pins can be selected as positive and negative input s to the differential amplifier. furthermore the temperature sensor and the drt voltages of sram2 can also be processed with the adc . if differential channels are selected, the amplifie d voltage difference between the selected input channel pair then becomes the input of the adc. the respective pin voltages for a differential measurement can be in t he range from 0v to evdd. in this way it is possible to handle differential input vol tages with a common mode value higher than avdd e.g. process a 50mv differential signal w ith a 2.5v common mode voltage. if single ended channels are used, the gain amplifi er is bypassed altogether. any adc input voltage (single-ended or amplified-differenti al) exceeding avdd will be internally clamped to avdd to avoid damaging the adc circuitry . note that the pin input current will not increase if the clamp circuit is active. the adc is enabled by setting aden bit in adcsra. v oltage reference and input channel selections will not go into effect until ad en is set. the adc does not consume power when aden is cleared. it is required to disab le the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presente d in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-b it precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same c onversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggere d when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 27.3 adc start-up after the adc is enabled by setting aden, it will g o through a start-up phase. the analog supply voltage avdd is turned on. it takes t ime t avreg (see "power management electrical characteristics" on page 510 ) s for avdd to stabilize. a stable avdd voltage is indicated by the avddok bit in adcsrb. a fter this the adc and, for differential input channels also the gain amplifier , is powered up. the duration of this phase depends on the adc clock period and the confi guration of the start-up and track-and?hold time bits, adsut and adtht in adcsrc . for details about the start- up timing refer to section "pre-scaling and conversion timing" on page 414. during the adc start-up phase a conversion start ca n already be requested by writing a logical one to the adc start conversion bit, adsc i n adcsra. in this case a conversion is started directly after the start-up p hase. during the start-up phase it is still possible to change the analog input channel until t he avddok bit changes to logic one or, if the avddok bit is one, until the adsc bit i s set. 27.4 starting a conversion a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected 414 8266c-mcu wireless-08/11 ATMEGA128RFA1 while a conversion is in progress, the adc will fin ish the current conversion before performing the channel change. alternatively, a conversion can be triggered automa tically by various sources. auto triggering is enabled by setting the adc auto trigg er enable bit, adate in adcsra. the trigger source is selected by setting the adc t rigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc pres caler is reset and a conversion is started. this provides a method of starting convers ions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger signal during conversion, the edge will be ignored. note that an interrupt flag will be set ev en if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrup t flag must be cleared in order to trigger a new conversion at the next interrupt even t. figure 27-2. adc auto trigger logic adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc .. . . edge detector adate using the adc interrupt flag as a trigger source ma kes the adc start a new conversion as soon as the ongoing conversion has fi nished. the adc then operates in free running mode, constantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive conversions in dependently of whether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversions c an be started by writing adsc in adcsra to one. adsc can also be used to determine i f a conversion is in progress. the adsc bit will be read as one during a conversio n, independently of how the conversion was started. 27.5 pre-scaling and conversion timing 27.5.1 prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 4 mhz. if a lower resolution tha n 10 bits is needed, the input clock frequency to the adc can be as high as 8 mhz to get a higher sample rate. for differential input channels the adc clock speed is restricted to a maximum of 2 mhz. 415 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-3. adc prescaler 7-bit adc prescaler adc clock source ck adps0adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start the adc module contains a prescaler, which generate s an acceptable adc clock frequency from any cpu frequency above 100 khz. the pre-scaling is set by the adps bits in adcsra. the prescaler starts counting from the moment when the adc is enabled. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. 27.5.2 start-up timing the adc is enabled by setting the aden bit in adcsr a. first the analog voltage regulator is powered up which takes t avreg (see "power management electrical characteristics" on page 510 ). a stable avdd is indicated by the avddok bit in adcsrb. after avdd has stabilized, the adc is started. the adc start-up time has a length of t adsu and can be adjusted by the start-up time bits adsut 4:0 in adcsrc. if differential input channels are used, then an addit ional initialization period t ainit is required by the gain amplifier. this period is conf igured by the track-and-hold time bits, adtht1:0 in adcsrc. adsut4:0 and adtht1:0 are fixed numbers of adc clock cycles and can be setup for different adc clo ck speeds. the minimum required adc start-up time is 20 s. no te that for the maximum adc speed of 8 mhz the start-up time can not be set hig her than 16 s in adsut4:0. under this condition the user has either to ensure that a conversion is not started earlier than 20 s after the adc is enabled or the first convers ion result should be discarded. for a summary of start-up times and sequences see table 27-1 below , table 27-2 below , figure 27-4 on page 416 and figure 27-5 on page 416. table 27-1. start-up time, single ended channels parameter duration in adc clock cycles adc start-up time t adsu 4(adsut+1), minimum 20 s table 27-2. start-up time, differential channels parameter duration in adc clock cycles adc start-up time t adsu 4(adsut+1), minimum 20 s gain amplifier initialization time t ainit 2(adtht+2) 416 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-4. adc timing diagram, start-up for single ended chann els a d c c lo c k a d e n a d s c a v d d o k a d if a d c h a d c l a d c s t a rt -u p t a v p u t a d s u m u x a n d r e f s u p d a te 1 1 t a d c _ c l k c o n v e rs io n a v d d p o w e r -u p s ig n a n d m s b o f r e s u lt l s b o f r e s u lt s a m p le & h o ld c o n v e rs io n c o m p le te figure 27-5. adc timing diagram, start-up for differential chann els a d c c lo c k a d e n a d s c a v d d o k a d if a d c h a d c l a d c s ta rt - u p t a v p u t a d s u m u x a n d r e f s u p d a te 1 1 t a d c _ c l k c o n v e r s io n a v d d p o w e r -u p s ig n a n d m s b l s b o f r e s u lt s a m p le & h o ld c o n v e r s io n c o m p le te a m p lifie r in it t a in it 27.5.3 conversion timing the delay from requesting a conversion start by set ting the adsc bit in adcsra to the moment where the sample-and-hold takes place is fix ed. the same fixed delay also applies for auto triggered conversions. in this cas e three additional cpu clock cycles are used for the trigger event synchronization logi c. the delay depends on the prescaler configuration adps and if single-ended or differential channels are used. a summary is given in table 27-3 below . all conversions take 11 adc clock cycles. when a conversion is complete, the result is writte n to the adc data registers, and adif is set. in single conversion mode, adsc is cle ared simultaneously. the software may then set adsc again, and a new conversion will be initiated at the earliest after the following tracking phase. the tracking phase is req uired after each conversion. its duration can be adjusted according to the adc clock speed by the adtht bits in adcsrc and is different for single-ended and differ ential channels. for details see table 27-4 on page 417. in free running mode, a new conversion will be star ted immediately after the tracking phase of the previous conversion while adsc remains high. the calculation of the resulting sample rate is given in table 27-5 on page 417. for timing diagrams of single and auto triggered an d free running conversions see figure 27-6 on page 417 to figure 27-8 on page 418. table 27-3. conversion start delay channel adps delay from conversion start request to sample & hold t scsmp 0, 1 2 cpu clock cycles single-ended 2 4 cpu clock cycles 417 8266c-mcu wireless-08/11 ATMEGA128RFA1 channel adps delay from conversion start request to sample & hold t scsmp 3 0 cpu clock cycles 4?7 0 cpu clock cycles differential 0?7 2 adc clock cycles table 27-4. tracking time channel tracking phase duration t trck in adc clock cycles single-ended adtht+1, minimum 500 ns differential 2adtht+3 table 27-5. sample rate in free running mode channel sample rate in adc clock cycles single-ended adtht+12 differential 2adtht+14 figure 27-6. adc timing diagram, single conversion a d c c lo c k a d e n a d s c a d if a d c h a d c l m u x a n d r e f s u p d a te 1 1 t a d c _ c l k t t r c k t ra c k in g c o n v e rsio n t s c s m p s ig n a n d m s b o f r e s u lt l s b o f r e s u lt m u x a n d r e f s u p d a te c o n v e rsio n c o m p le te t s c s m p c o n v e rs io n p re s ca le r r e se t a n d s a m p le & h o ld p re s c a le r r e se t a n d s a m p le & h o ld figure 27-7. adc timing diagram, auto triggered conversion a d c c lo ck a d e n t rig g e r s o u rce a d if a d c h a d c l m u x a n d r e f s u p d a te 1 1 t a d c _ c l k t t r c k t ra c kin g c o n ve rs io n t s c s m p s ig n a n d m s b o f r e s u lt l s b o f r e su lt m u x a n d r e f s u p d a te c o n v e rsio n c o m p le te t s c s m p c o n v e rs io n p re s ca le r r e s e t a n d s a m p le & h o ld a d a t e p re s ca le r r e se t a n d s a m p le & h o ld 418 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-8. adc timing diagram, free running conversion a d c c lo c k a d t s [2 :0 ] a d s c a d if a d c h a d c l 1 1 t a d c _ c l k t t r c k t ra c k in g c o n v e rs io n s ig n a n d m s b o f r e s u lt l s b o f r e s u lt m u x a n d r e f s u p d a te c o n v e rs io n c o m p le te s a m p le & h o ld c o n v e rs io n 0 1 1 t a d c _c l k 27.6 changing channel or reference selection the mux n and refs n bits in the admux and adcsrb register are single b uffered through a temporary register to which the cpu has r andom access. this ensures that the channels and reference selection only takes pla ce at a safe point during the conversion. the channel and reference selection is continuously updated either during the avdd power-up phase or until a conversion is st arted by setting adsc. after this the channel and reference selection is locked to en sure a sufficient initialization and sampling time for the adc. continuous updating of t he channel selection resumes after the conversion has completed (adif in adcsra is set ). if auto triggering is used, the exact time of the t riggering event can be undetermined. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settin gs. if both adate and aden in the adscra register are w ritten to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during a conversion 3. after a conversion, before the interrupt flag us ed as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next a/d conversion. after the channel or reference voltage selection is updated a settling time is required for the adc and the gain amplifier or the reference vol tage to stabilize. when changing the channel selection while the adc is enabled the required settling phase is automatically inserted by the adc interface, see se ction "adc input channels" on page 419. for consideration on changing the reference vo ltage selection please refer to section "adc voltage reference" on page 420. 27.6.1 accessing the admux register the channel selection bits mux4:0 and mux5 are loca ted in two different register, the admux and the adcsrb register. to ensure that chang es go only into effect after both register have been changed they are internally buffered (see figure 27-9 on page 419 and figure 27-10 on page 420). the mux5 bit has to written first follo wed by a write access to the mux4:0 bits which triggers the update of the internal buffer. if only the mux4:0 bits need to be modified then a write ac cess to the mux4:0 bits is sufficient. 419 8266c-mcu wireless-08/11 ATMEGA128RFA1 27.6.2 adc input channels the adc input channels can be changed while the adc is running under the condition that the previous channel was a single-ended one. c hanging between differential channels however requires that the adc is disabled and enabled again to make the adc go through the initial start-up phase. if changing from single-ended to single-ended or fr om single-ended to differential input channels a settling phase is automatically inserted by the adc interface logic after the input channel is modified. the settling phase is re quired by the adc and the gain amplifier to stabilize. if a conversions start is r equested during this settling phase, by setting adsc or by a trigger event in auto triggere d mode then the conversion is started only after the settling phase has completed . in case the mux n bits are altered during an ongoing conversion, the adc input channel is changed after the conversion has completed. mux n changes occurring during the tracking phase, which follows a conversion, will st op the tracking phase and the adc settling phase will be entered. in free running mode mux n can also be modified. in this case the adc input c hannel is changed after the conversion end or from the sub sequent tracking phase. as a consequence the time from one conversion to the nex t is extended by the duration of the adc settling phase. the adc settling time t aset depends on the previous and the new channel and on the configuration of the adsut and adtht bits as shown in table 27-6 below . additionally a synchronization delay t chdly from 2 cpu to 2 adc clock cycles is required betwe en changing the adc input channel selection and the be ginning of the settling phase. for details see the timing diagrams figure 27-9 below and figure 27-10 on page 420. table 27-6. settling time after channel changes channel transition settling time t aset in adc clock cycles single-ended to single-ended adtht+2 differential to single-ended adtht+2 differential to differential single-ended to differential requires the adc to be disabled and enabled again. figure 27-9. adc timing diagram, changing mux n after a conversion a d c c lo c k a d if a d c h a d c l t a s e t a d c s e ttlin g c o n v e rs io n s ig n a n d m s b o f r e s u lt l s b o f r e s u lt c o n v e rs io n c o m p le te m u x 5 :0 m u x 5 :0 in te rn a l o ld c h a n n e l n e w c h a n n e l n e w c h a n n e l o ld c h a n n e l a d c in p u t c h a n n e l is c h a n g e d t c h d l y n e w c o n v e rs io n c a n b e s ta rte d fro m h e re 420 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-10. adc timing diagram, changing mux n during a conversion a d c c lo ck a d if a d c h a d c l 1 1 t a d c _ c l k t a s e t a d c s e ttlin g c o n ve rsio n s ig n a n d m s b o f r e su lt l s b o f r e su lt c o n ve rsio n c o m p le te m u x 5 :0 m u x 5 :0 in te rn a l o ld c h a n n e l n e w c h a n n e l n e w c h a n n e l o ld c h a n n e l a d c in p u t c h a n n e l is ch a n g e d t c h d l y n e w c o n ve rsio n ca n b e sta rte d fro m h e re 27.6.3 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result 0x3ff. v ref can be selected by the refs n bits in the admux register as either avdd (1.8v), i nternal 1.5v or 1.6v reference or an external voltage at the aref pin. avdd is connected to the adc through a passive swit ch. the internal 1.5v and 1.6v references are generated from a bandgap reference ( vbg) through an amplifier. in either case, the external aref pin is directly conn ected to the adc and the reference voltage can be measured at the aref pin with a high impedance voltmeter. when using the internal 1.5v or 1.6v references no exter nal de-coupling capacitor must be connected to aref. high capacitive loading will de- stabilize the internal voltage amplifier. the 1.6v reference voltage is calibrated to an absolute accuracy of 1 lsb during the manufacturing process. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the applicat ion, as they will be shorted to the external voltage. an external reference voltage mus t be supplied with a very low impedance r aref,ext (see "adc characteristics" on page 514 ). the load current i l,aref (see "adc characteristics" on page 514 ) seen by the external source is code dependent and changes (current steps) in the course of the successive approximation process. if no external voltage is applied to the a ref pin, the user may switch between avdd, 1.5v and 1.6v as reference selection. changes of the reference selection bits refs n will only take effect until the first conversion start is requested by setting adsc in ad csra. after this the adc has to be disabled and enabled again for new reference select ions. for internal references a stable voltage is indicated by the refok bit in adc srb. 27.7 adc noise canceller the adc features a noise canceller that enables con version during sleep mode to reduce noise induced from the cpu core and other i/ o peripherals. the noise canceller can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not bus y converting. single conversion mode must be selected and the adc conversion comple te interrupt must be enabled. 2. enter adc noise reduction mode (or idle mode). t he adc will start a conversion once the cpu has been halted. 421 8266c-mcu wireless-08/11 ATMEGA128RFA1 3. if no other interrupts occur before the a/d conv ersion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the a/ d conversion is complete, that interrupt will be executed, and an adc conversion c omplete interrupt request will be generated when the a/d conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the us er is advised to write zero to aden before entering such sleep modes to avoid exce ssive power consumption. 27.7.1 analog input circuitry the analog input circuitry for single ended channel s is illustrated in figure 27-11 below . an analog source applied to adc n is subjected to the pin capacitance and input leakage of that pin, regardless of whether that cha nnel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals having outp ut impedance z out of approximately 3 k or less. if such a source is used, the sampling ti me will be negligible. if a source with higher impedance is us ed, the correct sampling time will depend on how much time is needed to charge the s/h capacitor, which can vary widely. the user is recommended to only use low imp edance sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. the required tracking time (input sampling switch c losed) t dtrck to settle to within 1 lsb can be estimated to ns k z t out dtrck 097 .0 ) 2000 / ( ? + = for z out > 3k (worst case: maximum input step). a minimum tracki ng time of 500ns is guaranteed by the conversion logic. based on the ad c clock frequency the bits adtht[1:0] of register adcsrc allow the adjustment of the tracking time to the user?s requirements. tracking time requirements should also be considere d for the differential mode. the input signal is sampled by the gain amplifier. the value of the input capacitance c s/h depends on the selected gain (~7pf for 200x gain, < 1pf otherwise). the tracking is equal to 50% of the clock period of ck adc2 . hence in differential mode a slower clock frequency is required for input sources with high i mpedance. figure 27-11. analog input circuitry a d c n i il i ih c s /h = 1 4 p f v a v d d /2 2 k signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from u npredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. 422 8266c-mcu wireless-08/11 ATMEGA128RFA1 27.7.2 analog noise canceling techniques digital circuitry inside and outside the device gen erates emi which might affect the accuracy of analog measurements. if conversion accu racy is critical, the noise level can be reduced by applying the following techniques: 1. keep analog signal paths as short as possible. m ake sure analog tracks run over the ground plane, and keep them well away from high-spe ed switching digital tracks. 2. use the adc noise canceller function to reduce i nduced noise from the cpu. 3. if any adc port pins are used as digital outputs , it is essential that these do not switch while a conversion is in progress. 27.7.3 offset compensation schemes the differential amplifier has a built-in offset ca ncellation circuitry that nulls the offset of differential measurements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same chan nel for both differential inputs. this offset residue can then be subtracted in software f rom the measurement results. the offset on any channel can be reduced below one lsb using this kind of software based offset correction. 27.7.4 differential amplifier limitations the programmable gain, differential amplifier (pga) converts a differential input voltage to a single-ended output voltage that is further pr ocessed with the 10 bit adc. the performance of the pga is determined by the physica l properties of its operational amplifier: ? the noise of pga adds to the random error of the a dc conversation result. however the pga noise enables the application of ov ersampling techniques to recover or even increase the adc resolution. ? the gain of the pga falls if the output voltage of the operational amplifier approaches the supply rails (avss) resulting in an increased non-linearity. hence for reasonable inl and dnl performance the input vo ltage range must be limited. 27.7.5 adc accuracy definitions an n-bit single-ended adc converts a voltage linear ly between 0v and v ref in 2 n steps (lsb?s). the lowest code is read as 0, and the high est code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x0 00 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. 423 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-12. offset error output code v ref input voltage ideal adcactual adc offset error ? gain error: after adjusting for offset, the gain e rror is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the id eal transition (at 1.5 lsb below maximum). ideal value: 0 lsb. figure 27-13. gain error output code v ref input voltage ideal adcactual adc gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. 424 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 27-14. integral non-linearity (inl) output code v ref input voltage ideal adcactual adc inl ? differential non-linearity (dnl): the maximum devi ation of the actual code width (the interval between two adjacent transitions) fro m the ideal code width (1 lsb). ideal value: 0 lsb. figure 27-15. differential non-linearity (dnl) output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) wi ll code to the same value. it is always 0.5 lsb. ? absolute accuracy: the maximum deviation of an act ual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 27.8 adc conversion result after the conversion is complete (adif is high), th e conversion result can be found in the adc result registers (adcl, adch). 425 8266c-mcu wireless-08/11 ATMEGA128RFA1 for single ended conversion, the result is ref in v v adc 1024 ? = where v in is the voltage on the selected input pin and v ref the selected voltage reference (see "table 27-10" on page 428 and "table 27-11" on page 429 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is ( ) ref neg pos v gain v v adc 512 ? ? ? = where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference. the result is pres ented in two?s complement form, from 0x200 (-512d) through 0x1ff ( +511d). note that if the user wants to perform a quick polarity check of the resu lt, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the r esult is negative, and if this bit is zero, the result is positive. figure 27-16 below shows the decoding of the differential input range. table 27-7 on page 426 shows the resulting output codes if the d ifferential input channel pair (adcn - adcm) is selected with a gain of gain and a reference voltage of v ref . figure 27-16. differential measurement range 0 output code 0x1ff 0x000 v ref /gain differential input voltage (volts) 0x3ff 0x200 - v ref /gain 426 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 27-7. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref / gain 0x1ff 511 v adcm + 0.999 v ref / gain 0x1ff 511 v adcm + 0.998 v ref / gain 0x1fe 510 ? ? ? v adcm + 0.001 v ref / gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref / gain 0x3ff -1 ? ? ? v adcm - 0.999 v ref / gain 0x201 -511 v adcm - v ref / gain 0x200 -512 example: admux = 0xed (adc3 - adc2, 10x gain, 1.6v reference , left adjusted result) the voltage on adc3 is 300 mv; the voltage on adc2 is 425 mv. adcr = 512 * 10 * (300 - 425) / 1600 = -400 = 0x270 . adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. 27.9 internal temperature measurement the on-chip temperature can be measured using a spe cial setup of the a/d converter inputs. the integrated temperature sensor provides a linear, medium-accurate voltage proportional to the absolute temperature (in kelvin ). this voltage is first amplified with the programmable gain amplifier and then processed with the a/d converter. a low frequency of the conversion clock must be selected due to the nature of the input signal. the absolute accuracy of the temperature measuremen t is limited by manufacturing tolerances, noise from supply and ground voltages a nd the exactness of the reference voltage. one time calibration at room temperature c an easily compensate this distribution. the resolution of the temperature reading can be im proved (<1k) by averaging (using float numbers) or decimation (based on integer numb ers) of multiple a/d conversion results. in this way the impact of noise is reduced (see measurement results "temperature sensor" on page 539 and "differential amplifier limitations" on page 422). the following table summarizes the preferred setup of the temperature measurement: table 27-8. recommended adc setup for temperature measurement parameter register recommended setup adc channel admux, adcsrb select the temperature sensor, mux4:0 = 01001; mux5 = 1; adc clock adcsra select a clock frequency of 500 kh z or lower; v ref admux select the internal 1.6v reference voltage; start-up time adcsrc standard requirement of 20 s is sufficient; tracking time adcsrc setting adtht = 0 is sufficien t; 427 8266c-mcu wireless-08/11 ATMEGA128RFA1 the a/d conversion result adc temp will always be a positive number. the ideal result can be calculated when using the internal 1.6v refe rence voltage according to the following equation: c adc temp ? + = / 885 .0 4. 241 similar the celsius-temperature can be extracted from the a/d conversion result wi th this formula: 8. 272 13.1 / ? ? = temp adc c note that the above equations are only valid in the allowed operating temperature range. the translation of the a/d measurement resul t to a celsius-temperature value can be easily achieved with a look-up table in soft ware. the temperature sensor is connected to a differential input channel with a ga in of 10. the offset error of the channel can be corrected to the first order by usin g an appropriate channel (e.g. mux4:0=01000, mux5=0, see table 27-11 on page 429 ). the in that manner measured error of the differential signal processin g is then subtracted from the temperature sensor adc reading. note that changing between the temperature sensor c hannel and the channel for the offset error correction can lead to a large differe nce of the analog input voltage. therefore it is recommended to disable the adc, sel ect the new channel and then enable the adc again, or discard the first conversi on result from the new input channel. 27.10 sram drt voltage measurement the decrease of the supply voltage of sram block 2 for the leakage current reduction can also be measured using a special setup of the a /d converter inputs. the details of the sram leakage current reduction are described in section "sram with data retention" on page 164 . the supply voltage of a disabled sram block can b e reduced to save leakage power while maintaining data retent ion. this feature applies to all four sram blocks however only the voltage of sram block 2 can be verified using the a/d converter. the default factory setting for the data retention (drt) voltage normally guarantees the best leakage performances. other values are neverth eless possible and can be selected by the application software. the true valu e of the supply voltage reduction is depending on the manufacturing process and environm ental conditions like temperature. the a/d converter allows determining t he value of the drt voltage of sram block 2. the same voltage setting results for all practical purposes in the same supply voltage for all other sram blocks. care must be taken when verifying the drt voltage o f sram block 2 with the a/d converter because it will be put into sleep mode an d hence it is not available for the application program. addressing the disabled sram w ill return invalid data (all data read zero). the voltage measurement is split into t wo parts. one setting allows measuring the voltage drop from dvdd. the other set ting allows verifying the voltage shift from dvss. both measurements are differential and use the programmable gain amplifier. a low frequency of the conversion clock must be selected due to the high- impedance nature of the input signal. accurate and stable voltage readings may just be available after a long waiting time of up to 100 ms . this limitation is the consequence of the small leakage currents that discharge the inter nal de-coupling capacitances before the supply voltage settles to the drt value. the fo llowing table summarizes the preferred setup of the drt voltage measurement: 428 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 27-9. recommended adc setup for drt voltage measurements parameter register recommended setup sram drt on drtram2 set bits dispc and endrt to 1; adc channel admux, adcsrb select mux4:0 = 10100 to measure v drtbbp ; select mux4:0 = 11101 to measure v drtbbn ; mux5 = 1; adc clock adcsra select a clock frequency of 500khz or lower; v ref admux select the internal 1.6v reference voltage; start-up time adcsrc standard requirement of 20s i s sufficient; tracking time adcsrc setting adtht = 0 is sufficien t; the a/d conversion result will always be a positive number for both v drtbbp and v drtbbn . the sram supply voltage is easily calculated acco rding to the following equation (see chapter "sram with data retention" on page 164 ): ) ( , , drtbbn drtbbp dd drt sram dd v v v v + ? = the conversion result is coded as described in "adc conversion result" on page 424 with a gain of 0.5. it is not possible to read both v drtbbp and v drtbbn at the same time. however the time required for the a/d conversion is short compared to the time constant of a drt voltage change. 27.11 register description 27.11.1 admux ? adc multiplexer selection register bit 7 6 5 4 3 2 1 0 na ($7c) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc , as shown in the following table. changes of these bits will only take effect until t he first conversion start is requested by setting adsc. after this the adc has to be disabled and enabled again for new reference selections. the internal voltage referenc e options may not be used if an external reference voltage is being applied to the aref pin. table 27-10. reference voltage selections for adc refs1 refs0 reference voltage selection 0 0 aref, internal v ref turned off 0 1 avdd (1.8v) 1 0 internal 1.5v voltage reference (no external ca pacitor at aref pin) 1 1 internal 1.6v voltage reference (no external ca pacitor at aref pin) ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the a/d c onversion result in the adc data register. write one to adlar to left adjust the res ult. otherwise, the result is right adjusted. changing the adlar bit will affect the ad c data register immediately, regardless of any ongoing conversions. for a comple te description of this bit, see "adcl and adch ? the adc data register" on page 433. 429 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? bits 4:0 ? mux4:0: analog channel and gain selectio n bits the value of these bits selects which combination o f analog inputs is connected to the adc. see table 27-11 below for details. if these bits are changed during a con version, the change will not go in effect until this convers ion is complete (adif in adcsra is set). note that the mux5 bit is located in the adcs rb register. a write access to the mux4:0 bits triggers the update of the internally b uffered mux5 bit, see "accessing the admux register" on page 418 . 27.11.2 adcsrb ? adc control and status register b bit 7 6 5 4 3 2 1 0 na ($7b) avddok acme refok acch mux5 adts2 adts1 adts0 adcsrb read/write r r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ? bit 7 ? avddok: avdd supply voltage ok the analog functions of the adc are powered from th e avdd domain. avdd is supplied from an internal voltage regulator. settin g the aden bit in register adcsra will power-up the avdd domain if not already reques ted by another functional group of the device. the bit allows the user to monitor (pol l) the status of the avdd domain. a status of 1 indicates that avdd has been powered-up . ? bit 6 ? acme: analog comparator multiplexer enable this bit is used for the analog comparator only. se e "adcsrb ? adc control and status register b" on page 410 for details. ? bit 5 ? refok: reference voltage ok the status of the internal generated reference volt age can be monitored through this bit. setting the aden bit in register adcsra will e nable the reference voltage for the adc according to the refs n bits in the admux register. the reference voltage will be available after a start-up delay. a refok value of 1 indicates that the internal generated reference voltage is approaching final le vels. ? bit 4 ? acch: analog channel change refer to "errata" on page 547 first. the user can force a reset of the analog bl ocks by setting this bit to 1 without requesting a differen t channel. the analog blocks of the adc will be reset to handle possible new voltage ranges . such a reset phase is especially important for the gain amplifier. it could be tempo rarily disabled by a large step of its input common voltage leading to erroneous a/d conve rsion results. acch will read as one until the reset phase of the analog blocks can be entered. ? bit 3 ? mux5: analog channel and gain selection bit this bit is used together with mux4:0 in admux to s elect the analog input signals connected to the adc. see the following table for d etails. if this bit is changed during a conversion, the change will not go in effect until this conversion is complete. note that the mux5 bit is internally buffered and a write acc ess to the mux4:0 bits is required to trigger the update of the mux5 bit, see "accessing the admux register" on page 418 . table 27-11. input channel selections mux5:0 single ended input positive differential input negative differential input gain 000000 adc0 000001 adc1 000010 adc2 n/a 430 8266c-mcu wireless-08/11 ATMEGA128RFA1 mux5:0 single ended input positive differential input negative differential input gain 000011 adc3 000100 adc4 000101 adc5 000110 adc6 000111 adc7 001000 adc0 adc0 10x 001001 adc1 adc0 10x 001010 adc0 adc0 200x 001011 adc1 adc0 200x 001100 adc2 adc2 10x 001101 adc3 adc2 10x 001110 adc2 adc2 200x 001111 n/a adc3 adc2 200x 010000 adc0 adc1 1x 010001 adc1 adc1 1x 010010 adc2 adc1 1x 010011 adc3 adc1 1x 010100 adc4 adc1 1x 010101 adc5 adc1 1x 010110 adc6 adc1 1x 010111 n/a adc7 adc1 1x 011000 adc0 adc2 1x 011001 adc1 adc2 1x 011010 adc2 adc2 1x 011011 adc3 adc2 1x 011100 adc4 adc2 1x 011101 n/a adc5 adc2 1x 011110 1.2v (v bg ) 011111 0v (avss) n/a 100000 reserved 100001 reserved 100010 reserved 100011 reserved 100100 reserved 100101 reserved 100110 reserved 100111 reserved n/a 101000 reserved 101001 temperature sensor 101010 reserved 101011 n/a reserved 431 8266c-mcu wireless-08/11 ATMEGA128RFA1 mux5:0 single ended input positive differential input negative differential input gain 101100 reserved 101101 reserved 101110 reserved 101111 reserved 110000 reserved 110001 reserved 110010 reserved 110011 reserved 110100 sram back-bias voltage v drtbbp 110101 reserved 110110 reserved 110111 n/a reserved 111000 reserved 111001 reserved 111010 reserved 111011 reserved 111100 reserved 111101 n/a sram back-bias voltage v drtbbn 111110 reserved 111111 reserved n/a ? bits 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an a/d conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the risin g edge of the selected interrupt flag. note that switching from a trigger source that is c leared, to a trigger source that is set, will generate a positive edge on the trigger signal . if aden in adcsra is set, this will start a conversion. switching to free running mode (adts2:0=0) will not cause a trigger event, even if the adc interrupt flag is se t. table 27-12. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event 432 8266c-mcu wireless-08/11 ATMEGA128RFA1 27.11.3 adcsra ? adc control and status register a bit 7 6 5 4 3 2 1 0 na ($7a) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ? bit 7 ? aden: adc enable writing this bit to one enables the adc. the avdd s upply voltage will also be enabled if not already available. by writing it to zero, th e adc is turned off. turning the adc off while a conversion is in progress will terminate th is conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the fi rst conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will include a start-up time to initialize the analog blocks of the adc. the start-up time is defined by the adsut bits of register adcsrc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto triggering of the adc is enabled. the adc will start a conversion on a positive edge of the select ed trigger signal. the trigger source is selected by setting the adc trigger select bits, ad ts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an a/d conversion is completed and the data register are updated. the adc conversion complete interrupt is executed i f the adie bit and the i-bit in sreg are set. adif is cleared by hardware when exec uting the corresponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi inst ructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sr eg is set, the adc conversion complete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between th e cpu frequency and the input clock to the adc. table 27-13. adc prescaler selections adps2 adps1 adps0 division factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 433 8266c-mcu wireless-08/11 ATMEGA128RFA1 27.11.4 adcsrc ? adc control and status register c bit 7 6 5 4 3 2 1 0 na ($77) adtht1 adtht0 res0 adsut4 adsut3 adsut2 adsut1 adsut0 adcsrc read/write rw rw rw rw rw rw rw rw initial value 0 1 0 1 0 1 0 0 this register defines the track-and-hold time for s ampling the analog input voltage of the adc and it defines the start-up time for the an alog blocks based on a number of adc clock cycles. the adc clock is generated from t he system clock with the adc prescaler. the bits adps2:0 of register adcsra set the prescaler ratio. correct start- up and track-and-hold times are important for preci se conversion results. ? bits 7:6 ? adtht1:0: adc track-and-hold time these bits define the number of adc clock cycles fo r the sampling time of the analog input voltage. for a complete description of this b it, see "pre-scaling and conversion timing" on page 414. ? bit 5 ? res0: reserved ? bits 4:0 ? adsut4:0: adc start-up time these bits define the number of adc clock cycles fo r the start-up time of the analog blocks. for a complete description of this bit, see "pre-scaling and conversion timing" on page 414 . 27.11.5 adcl and adch ? the adc data register 27.11.5.1 adlar = 0 bit 15 14 13 12 11 10 9 8 na ($79) ? ? ? ? ? ? adc9 adc8 adch na ($78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 7 6 5 4 3 2 1 0 read/write r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27.11.5.2 adlar = 1 bit 15 14 13 12 11 10 9 8 na ($79) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch na ($78) adc1 adc0 ? ? ? ? ? ? adcl 7 6 5 4 3 2 1 0 read/write r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 when an a/d conversion is complete, the result is f ound in these two registers. if differential channels are used, the result is prese nted in two?s complement form. when adcl is read, the adc data register is not upd ated until adch is read. consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign 434 8266c-mcu wireless-08/11 ATMEGA128RFA1 bit for differential input channels) is required, i t is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the mux n bits in admux affect the way the result is read from the registers. if adlar is set, the resul t is left adjusted. if adlar is cleared (default), the result is right adjusted. ? adc9:0: a/d conversion result these bits represent the result from the conversion as detailed in "adc conversion result" on page 424 . 27.11.6 didr0 ? digital input disable register 0 bit 7 6 5 4 3 2 1 0 na ($7e) adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d did r0 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 ? bits 7:0 ? adc7d:adc0d: digital input disable when this bit is written logic one, the digital inp ut buffer on the corresponding adc pin is disabled. the corresponding pin register bit wil l always read as zero when this bit is set. when an analog signal is applied to the adc7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 27.11.7 didr2 ? digital input disable register 2 bit 7 6 5 4 3 2 1 0 na ($7d) adc15d adc14d adc13d adc12d adc11d adc10d adc9d adc8d didr2 read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 reserved for future use. ? bit 7:0 ? adc15d:adc8d - reserved bits this bit is reserved for future use. for ensuring c ompatibility with future devices, this bit must be written to zero. 27.11.8 bgcr ? reference voltage calibration regist er bit 7 6 5 4 na ($67) res bgcal_fine3 bgcal_fine2 bgcal_fine1 bgcr read/write r rw rw rw initial value 0 0 0 0 bit 3 2 1 0 na ($67) bgcal_fine0 bgcal2 bgcal1 bgcal0 bgcr read/write rw rw rw rw initial value 0 0 0 0 this register contains the calibration values of th e reference voltage of the adc. the values are loaded from the fuse memory after power- up. they can be corrected by the 435 8266c-mcu wireless-08/11 ATMEGA128RFA1 application software e.g. to compensate for tempera ture changes. the internal 1.6v reference voltage is calibrated and has therefore t he highest accuracy compared to the 1.5v or avdd reference. ? bit 7 ? res - reserved bit this bit is reserved for future use. a read access always will return zero. a write access does not modify the content. ? bit 6:3 ? bgcal_fine3:0 - fine calibration bits these bits allow the calibration of the aref voltag e with a resolution of 2mv. table 27-14 bgcal_fine register bits register bits value description 0 center value 1 voltage step up 8 voltage step down 7 setting for highest voltage bgcal_fine3:0 15 setting for lowest voltage ? bit 2:0 ? bgcal2:0 - coarse calibration bits these bits allow the calibration of the aref voltag e with a resolution of 10mv. table 27-15 bgcal register bits register bits value description 4 center value 3 voltage step up 5 voltage step down 0 setting for highest voltage bgcal2:0 7 setting for lowest voltage 436 8266c-mcu wireless-08/11 ATMEGA128RFA1 28 jtag interface and on-chip debug system 28.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the ieee st d. 1149.1 (jtag) standard ? debugger access to: o all internal peripheral units o internal and external ram o the internal register file?program counter o eeprom and flash memories ? extensive on-chip debug support for break condition s, including o avr break instruction o break on change of program memory flow o single step break o program memory breakpoints on single address or add ress range o data memory breakpoints on single address or addres s range ? programming of flash, eeprom, fuses, and lock bits through the jtag interface ? on-chip debugging supported by avr studio ? 28.2 overview the avr ieee std. 1149.1 compliant jtag interface c an be used for ? testing pcbs by using the jtag boundary-scan capab ility ? programming the non-volatile memories, fuses and l ock bits ? on-chip debugging a brief description is given in the following secti ons. detailed descriptions for programming via the jtag interface, and using the b oundary-scan chain can be found in the sections "programming via the jtag interface" on page 483 and "programming via the jtag interface" on page 483 , respectively. the on-chip debug support is considered being private jtag instructions, and dis tributed within atmel and to selected third party vendors only. figure 28-1 on page 437 shows a block diagram of the jtag interfa ce and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift reg ister) between the tdi ? input and tdo ? output. the instruction register holds jtag i nstructions controlling the behavior of a data register. the id-register, bypass register, and the boundary- scan chain are the data registers used for board-level testing. the jtag pr ogramming interface (actually consisting of several physical and virtual data reg isters) is used for serial programming via the jtag interface. the internal scan-chain and breakpoint scan-chain are used for on-chip debugging only. 437 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 28-1. block diagram tap controller tditdo tck tms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pcinstruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0i/o port n boundary scan chain analog inputs control & clock lines device boundary 28.3 tap - test access port the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. t hese pins are: ? tms: test mode select. this pin is used for naviga ting through the tap-controller state machine. ? tck: test clock. jtag operation is synchronous to tck. ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo: test data out. serial output data from instru ction register or data register. the ieee std. 1149.1 also specifies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is un-programmed, these four t ap pins are normal port pins, and the tap controller is in reset. when programmed the input tap signals are internally pulled high and the jtag is enabled for boundary-scan and programming. the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jt ag interface pins, the reset pin is monitored by the debugger to be able to detect exte rnal reset sources. the debugger can also pull the reset pin low to reset the whole system, assuming only open collectors on the reset line are used in the applic ation. 438 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 28-2. tap controller state diagram test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 28.4 tap controller the tap controller is a 16-state finite state machi ne that controls the operation of the boundary-scan circuitry, jtag programming circuitry , or on-chip debug system. the state transitions depicted in figure 28-2 above depend on the signal present on tms (shown adjacent to each state transition) at the ti me of the rising edge at tck. the initial state after a power-on reset is test-logic- reset. as a definition in this document, the lsb is shifte d in and out first for all shift registers. assuming run-test/idle is the present state, a typi cal scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. wh ile in this state, shift the four bits of the jtag instructions into the jtag instruction reg ister from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of t he instruction is shifted in when this state is left by setting tms high. while the i nstruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on t he tdo pin. the jtag instruction 439 8266c-mcu wireless-08/11 ATMEGA128RFA1 selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. ? apply the tms sequence 1, 1, 0 to re-enter the run -test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at th e rising edges of tck to enter the shift data register ? shift-dr state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in or der to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by s etting tms high. while the data register is shifted in from the tdi pin, the parall el inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run -test/idle state. if the selected data register has a latched parallel-output, the la tching takes place in the update- dr state. the exit-dr, pause-dr, and exit2-dr state s are only used for navigating the state machine. as shown in the state diagram, the run-test/idle st ate need not be entered between selecting jtag instruction and using data registers , and some jtag instructions may select certain functions to be performed in the run -test/idle, making it unsuitable as an idle state. note that independent of the initial state of the t ap controller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specification, ref er to the literature listed in "bibliography" on page 441. 28.5 using the boundary-scan chain a complete description of the boundary-scan capabil ities are given in the section "ieee 1149.1 (jtag) boundary-scan" on page 442 . 28.6 using the on-chip debug system the on-chip debug system must be disabled for the b est rf performance of the radio transceiver. as shown in figure 28-1, the hardware support for on-chip debugging consists mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? breakpoint unit. ? communication interface between the cpu and jtag s ystem. all read or modify/write operations needed for impl ementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is pa rt of the communication interface between the cpu and the jtag system. the breakpoint unit implements break on change of program flow , single step break , two program memory breakpoints and two combined bre akpoints. together, the four breakpoints can be configured as either: ? 4 single program memory breakpoints; ? 3 single program memory breakpoint + 1 single data memory breakpoint; ? 2 single program memory breakpoints + 2 single dat a memory breakpoints; 440 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? 2 single program memory breakpoints + 1 program me mory breakpoint with mask (?range breakpoint?). ? 2 single program memory breakpoints + 1 data memor y breakpoint with mask (?range breakpoint?). a debugger, like the avr studio, may however use on e or more of these resources for its internal purpose, leaving less flexibility to t he end-user. a list of the on-chip debug specific jtag instructi ons is given in "on-chip debug specific jtag instructions" below . the jtagen fuse must be programmed to enable the jt ag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to work. as a security feature , the on-chip debug system is disabled when either of the lb1 or lb2 lock-bits ar e set. otherwise, the on-chip debug system would have provided a back-door into a secur ed device. the avr studio enables the user to fully control ex ecution of programs on an avr device with on-chip debug capability, avr in-circui t emulator, or the built-in avr instruction set simulator. avr studio supports sour ce level execution of assembly programs assembled with atmel corporation?s avr ass embler and c programs compiled with third party vendors? compilers. for a full description of the avr studio, please refer to the avr studio user guide. only hig hlights are presented in this document. all necessary execution commands are available in a vr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functi ons, step out of functions, place the cursor on a statement and execute until the stateme nt is reached, stop the execution, and reset the execution target. in addition, the us er can have an unlimited number of code breakpoints (using the break instruction) and up to two data memory breakpoints, alternatively combined as a mask (rang e) breakpoint. 28.7 on-chip debug specific jtag instructions the on-chip debug support is considered being priva te jtag instructions, and distributed within atmel and to selected third part y vendors only. instruction operation codes are listed for reference. 28.7.1 private0; 0x8 private jtag instruction for accessing on-chip debu g system; 28.7.2 private1; 0x9 private jtag instruction for accessing on-chip debu g system; 28.7.3 private2; 0xa private jtag instruction for accessing on-chip debu g system; 28.7.4 private3; 0xb private jtag instruction for accessing on-chip debu g system; 28.8 using the jtag programming capabilities programming of the ATMEGA128RFA1 via jtag is perfor med via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins tha t need to be controlled and observed to perform jtag programming (in addition t o power pins). the jtagen fuse must be programmed and the jtd bit in the mcucr reg ister must be cleared to enable the jtag test access port. 441 8266c-mcu wireless-08/11 ATMEGA128RFA1 the jtag programming capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in parallel pro gramming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be progra mmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interfa ce and programming specific jtag instructions are given in the section "programming via the jtag interface" on page 483 . 28.9 bibliography for more information about general boundary-scan, t he following literature can be consulted: ? ieee: ieee std. 1149.1-1990. ieee standard test ac cess port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testab le logic circuits, addison- wesley, 1992. 28.10 on-chip debug related register in i/o memory 28.10.1 ocdr ? on-chip debug register bit 7 6 5 4 3 2 1 0 $31 ($51) ocdr7:0 ocdr read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the ocdr register provides a communication channel from the running program in the microcontroller to the debugger. the cpu can tr ansfer a byte to the debugger by writing to this location. at the same time, an inte rnal flag; i/o debug register dirty idrd is set to indicate to the debugger that the r egister has been written. when the cpu reads the ocdr register the 7 lsb will be from the ocdr register, while the msb is the idrd bit. the debugger clears the idrd b it when it has read the information. in some avr devices, this register is shared with a standard i/o location. in this case, the ocdr register can only be accesse d if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. ? bit 7:0 ? ocdr7:0 - on-chip debug register data table 28-16 ocdr register bits register bits value description ocdr7:0 0 refer to the debugger documentation for further information on how to use this register. 442 8266c-mcu wireless-08/11 ATMEGA128RFA1 29 ieee 1149.1 (jtag) boundary-scan 29.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag st andard ? full scan of all port functions as well as analog c ircuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset th e ATMEGA128RFA1 29.2 system overview the boundary-scan chain has the capability of drivi ng and observing the logic levels on the digital i/o pins, as well as the boundary betwe en digital and analog logic for analog circuitry having off-chip connections. at system le vel, all ics having jtag capabilities are connected serially by the tdi/tdo signals to fo rm a long shift register. an external controller sets up the devices to drive values at t heir output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan provide s a mechanism for testing interconnections and integrity of components on pri nted circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag instruc tions idcode, bypass, sample/preload, and extest, as well as the avr spec ific public jtag instruction avr_reset can be used for testing the printed circu it board. initial scanning of the data register path will show the id-code of the dev ice, since idcode is the default jtag instruction. it may be desirable to have the a vr device in reset during test mode. if not reset, inputs to the device may be determine d by the scan operations, and the internal software may be in an undetermined state w hen exiting the test mode. entering reset, the outputs of any port pin will instantly e nter the high impedance state, making the highz instruction redundant. if needed, the byp ass instruction can be issued to make the shortest possible scan chain through the d evice. the device can be set in the reset state either by pulling the external reset pi n low, or issuing the avr_reset instruction with appropriate setting of the reset d ata register. the extest instruction is used for sampling externa l pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-regis ter. therefore, the sample/preload should also be used for setting init ial values to the scan ring, to avoid damaging the board when issuing the extest in struction for the first time. sample/preload can also be used for taking a snapsh ot of the external pins during normal operation of the part. the jtagen fuse must be programmed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port . when using the jtag interface for boundary-scan, us ing a jtag tck clock frequency higher than the internal chip frequency is possible . the chip clock is not required to run. 29.3 data registers the data registers relevant for boundary-scan opera tions are: ? bypass register ? device identification register 443 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? reset register ? boundary-scan chain 29.3.1 bypass register the bypass register consists of a single shift regi ster stage. when the bypass register is selected as path between tdi and tdo, t he register is reset to 0 when leaving the capture-dr controller state. the bypass register can be used to shorten the scan chain on a system when the other devices a re to be tested. 29.3.2 device identification register figure 29-1. the format of the device identification register msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1 bit 29.3.2.1 version version is a 4-bit number identifying the revision of the component. the jtag version number follows the revision of the device. revision a is 0x0, revision b is 0x1 and so on. 29.3.2.2 part number the part number is a 16-bit code identifying the co mponent. the jtag part number for ATMEGA128RFA1 is listed in table 31-6 on page 468 . 29.3.2.3 manufacturer id the manufacturer id is a 11-bit code identifying th e manufacturer. the jtag manufacturer id for atmel is listed in table 31-6 on page 468 . 29.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri- states port pins when reset, the reset register can also replace the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to p ulling the external reset low. the part is reset as long as there is a high value pres ent in the reset register. depending on the fuse settings for the clock options, the par t will remain reset for a reset time-out period (see "clock sources" on page 149 ) after releasing the reset register. the output from this data register is not latched, so t he reset will take place immediately, as shown in figure 29-2 on page 444. 444 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 29-2. reset register d q from tdi clockdr avr_reset to tdo from other internal and external reset sources internal reset 29.3.4 boundary-scan chain the boundary-scan chain has the capability of drivi ng and observing the logic levels on the digital i/o pins, as well as the boundary betwe en digital and analog logic for analog circuitry having off-chip connections. see "boundary-scan chain" on page 445 for a complete description. 29.4 boundary-scan specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. listed below are the jtag instructions useful for boundary-scan oper ation. note that the optional highz instruction is not implemented, but all outputs wit h tri-state capability can be set in high- impedance state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shift ed in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. 29.4.1 extest; 0x0 mandatory jtag instruction for selecting the bounda ry-scan chain as data register for testing circuitry external to the avr package. for port-pins, pull-up disable, output control, output data, and input data are all access ible in the scan chain. for analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. the contents of the lat ched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the internal scan chain is shifted by th e tck input. ? update-dr: data from the scan chain is applied to output pins. 29.4.2 idcode; 0x1 optional jtag instruction selecting the 32 bit id-r egister as data register. the id- register consists of a version number, a device num ber and the manufacturer code chosen by jedec. this is the default instruction af ter power-up. 445 8266c-mcu wireless-08/11 ATMEGA128RFA1 the active states are: ? capture-dr: data in the idcode register is sampled into the boundary-scan chain. ? shift-dr: the idcode scan chain is shifted by the tck input. 29.4.3 sample_preload; 0x2 mandatory jtag instruction for pre-loading the outp ut latches and taking a snap-shot of the input/output pins without affecting the system operation. however, the output latches are not connected to the pins. the boundary -scan chain is selected as data register. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the boundary-scan chain is shifted by th e tck input. ? update-dr: data from the boundary-scan chain is ap plied to the output latches. however, the output latches are not connected to th e pins. 29.4.4 avr_reset; 0xc the avr specific public jtag instruction for forcin g the avr device into the reset mode or releasing the jtag reset source. the tap co ntroller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 29.4.5 bypass; 0xf mandatory jtag instruction selecting the bypass reg ister for data register. the active states are: ? capture-dr: loads a logic ?0? into the bypass regi ster. ? shift-dr: the bypass register cell between tdi and tdo is shifted. 29.5 boundary-scan chain the boundary-scan chain has the capability of drivi ng and observing the logic levels on the digital i/o pins, as well as the boundary betwe en digital and analog logic for analog circuitry having off-chip connection. 29.5.1 scanning the digital port pins figure 29-3 on page 446 shows the boundary-scan cell for a bi-dir ectional port pin. the pull-up function is disabled during boundary-scan w hen the jtag ic contains extest or sample_preload. the cell consists of a bi-direct ional pin cell that combines the three signals output control - ocxn, output data - odxn, and input data - idxn, into only a two-stage shift register. the port and pin i ndexes are not used in the following description. the boundary-scan logic is not included in the figu res in the datasheet. figure 29-4 on page 447 shows a simple digital port pin as describ ed in the section "i/o-ports" on page 188 . the boundary-scan details from figure 29-3 on page 446 replaces the dashed box in figure 29-4 on page 447. 446 8266c-mcu wireless-08/11 ATMEGA128RFA1 when no alternate port function is present, the inp ut data - id - corresponds to the pinxn register value (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the da ta direction - dd register, and the pull-up enable - puexn ? corresponds to logic e xpression: portxn ddxn pud ? ? digital alternate port functions are connected outs ide the dotted box figure 29-4 on page 447 to make the scan chain read the actual pin value. for analog function, there is a direct connection from the external pin to the an alog circuit. there is no scan chain on the interface between the digital and the analog ci rcuitry, but some digital control signal to analog circuitry are turned off to avoid driving contention on the pads. when jtag ir contains extest or sample_preload the clock is not sent out on the port pins even if the ckout fuse is programmed. even though the clock is output when the jtag ir contains sample_preload, the clock is not sampled by the boundary scan. figure 29-3. boundary-scan cell for bi-directional port pin with pull-up function 447 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 29-4. general port pin schematic diagram clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx dl qq reset reset q q d q q d clr portxn q q d clr ddxn pinxn dat a bus sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output da ta to pin pxn idxn: input da ta from pin pxn 29.5.2 scanning the rstn, clki and tst pin an observe-only cell as shown in figure 29-5 below is inserted for the active low reset signal rstn, for the active high programming and te st mode enable signal tst and for the clock input clki. figure 29-5. observe-only cell 01 d q from previous cell clockdr shiftdr to next cell from system pin to system logic ff1 448 8266c-mcu wireless-08/11 ATMEGA128RFA1 29.5.3 scanning the rston pin for the low-active reset output pin rston a boundar y-scan cell as shown in figure 29-6 below is inserted. figure 29-6. boundary-scan cell for output pins without pull-up function 29.6 boundary-scan related register in i/o memory for detailed register description see chapter "mcucr ? mcu control register" on page 217 and "mcusr ? mcu status register" on page 185 . 29.6.1 mcucr ? mcu control register bit 7 6 5 4 3 2 1 0 $35 ($55) jtd mcucr read/write rw initial value 0 the mcu control register contains control bits for general microcontroller unit functions. ? bit 7 ? jtd - jtag interface disable when this bit is zero, the jtag interface is enable d if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in order to avoid unintentional disabling or enabling of the jtag int erface, a timed sequence must be followed when changing this bit: the application so ftware must write this bit to the desired value twice within four cycles to change it s value. note that this bit must not be altered when using the on-chip debug system. 29.6.2 mcusr ? mcu status register bit 7 6 5 4 3 2 1 0 $34 ($54) jtrf mcusr read/write rw initial value 0 449 8266c-mcu wireless-08/11 ATMEGA128RFA1 the mcu status register provides information on whi ch reset source caused an mcu reset. ? bit 4 ? jtrf - jtag reset flag this bit is set if a reset is being caused by a log ic one in the jtag reset register selected by the jtag instruction avr_reset. this bi t is reset by a power-on reset, or by writing a logic zero to the flag. 29.7 boundary-scan description language files boundary-scan description language (bsdl) files des cribe boundary-scan capable devices in a standard format used by automated test -generation software. the order and function of bits in the boundary-scan data regi ster are included in this description. bsdl files are available for ATMEGA128RFA1. 29.8 ATMEGA128RFA1 boundary-scan order table 29-1 on page 450 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follo ws the pin-out order. in figure 29-3 on page 446 , pxn. data corresponds to ff0, pxn. control corres ponds to ff1, pxn. bit 4, 5, 6 and 7 of port f is not in the scan chain, sinc e these pins constitute the tap pins when the jtag is enabled. 450 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 29-1. ATMEGA128RFA1 boundary-scan order bit number signal name module bit number signal name module 0 pf1.control 36 clki.data clock input (input only) 1 pf1.data 37 pd7.control 2 pf0.control 38 pd7.data 3 pf0.data port f 39 pd6.control 4 pe7.control 40 pd6.data 5 pe7.data 41 pd5.control 6 pe6.control 42 pd5.data 7 pe6.data 43 pd4.control 8 pe5.control 44 pd4.data 9 pe5.data 45 pd3.control 10 pe4.control 46 pd3.data 11 pe4.data 47 pd2.control 12 pe3.control 48 pd2.data 13 pe3.data 49 pd1.control 14 pe2.control 50 pd1.data 15 pe2.data 51 pd0.control 16 pe1.control 52 pd0.data port d 17 pe1.data 53 pg5.control 18 pe0.control 54 pg5.data 19 pe0.data port e 55 pg4.control 20 pb7.control 56 pg4.data 21 pb7.data 57 pg3.control 22 pb6.control 58 pg3.data 23 pb6.data 59 pg2.control 24 pb5.control 60 pg2.data 25 pb5.data 61 pg1.control 26 pb4.control 62 pg1.data 27 pb4.data 63 pg0.control 28 pb3.control 64 pg0.data port g 29 pb3.data 65 rston.data reset logic output (output only without pull-up) 30 pb2.control 66 rstt.data reset logic (observe only) 31 pb2.data 67 tst.data test and programming mode enable (observe only) 32 pb1.control 68 pf3.control 33 pb1.data 69 pf3.data 34 pb0.control 70 pf2.control 35 pb0.data port b 71 pf2.data port f 451 8266c-mcu wireless-08/11 ATMEGA128RFA1 30 boot loader support ? read-while-write self-prog ramming the boot loader support provides a real read-while- write self-programming mechanism for downloading and uploading program cod e by the mcu itself. this feature allows flexible application software update s controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write that (program) code into the flash memory, or read the code from the program memory. the program code within the boot loader section has the capability t o write into the entire flash, including the boot loader memory. the boot loader can thus ev en modify itself (including erasing) from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the bo ot loader has two separate sets of boot lock bits which can be set independently. t his gives the user a unique flexibility to select different levels of protection. 30.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexib le protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consistin g of several bytes (see "table 31-7" on page 468 ) used during programming. the page organization do es not affect normal operation. 30.2 application and boot loader flash sections the flash memory is organized in two main sections: the application section and the boot loader section (see figure 30-2 on page 453). the size of the different sections is configured by the bootsz fuses as shown in table 30-7 on page 462 and figure 30-2 on page 453. these two sections can have different le vel of protection since they have different sets of lock bits. 30.2.1 application section the application section is the region of the flash that is used for storing the application code. the protection level for the application sect ion can be selected by the application boot lock bits (boot lock bits 0, blb0), see table 31-2 on page 465 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 30.2.2 bls ? boot loader section while the application section is used for storing t he application code, the boot loader software must be located in the bls. the spm instru ction can only initiate programming when executed from the bls. the spm ins truction can access the entire flash, including the bls itself. the protection lev el for the boot loader section can be selected by the boot loader lock bits (boot lock bi ts 1, blb1), see table 31-2 on page 465 . 452 8266c-mcu wireless-08/11 ATMEGA128RFA1 30.3 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader software update is dependent on the address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sec tions, the read-while-write (rww) section and the no read-while-write (nrww) section. the limit between the rww- and nrww sections is given in table 30-1 on page 453 and figure 30-1 below . the main differences between the two sections are: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section during a boot loader software operation. th e syntax ?read-while-write section? refers to the section that is being progra mmed (erased or written) and not to the section that actually is being read during a bo ot loader software update. figure 30-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 30.3.1 rww ? read-while-write section if a boot loader software update is programming a p age inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an ongoing programming, the softwar e must ensure that the rww section never is being read. if the user software i s trying to read code that is located inside the rww section (i.e., by load program memor y, call, or jump instructions or an interrupt) during programming, the software might e nd up in an unknown state. to avoid this, the interrupts should either be disabled or m oved to the boot loader section. the boot loader section is always located in the nrww s ection. the rww section busy bit (rwwsb) in the store program memory control and status register (spmcsr) will be read as logical one as long as the rww section i s blocked for reading. after a 453 8266c-mcu wireless-08/11 ATMEGA128RFA1 programming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see "spmcsr ? store program memory control register" on page 462 for details on how to clear rwwsb. 30.3.2 nrww ? no read-while-write section the code located in the nrww section can be read wh en the boot loader software is updating a page in the rww section. when the boot l oader code updates the nrww section, the cpu is halted during the entire page e rase or page write operation. table 30-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no figure 30-2. memory sections 0x0000flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rwwstart nrww application flash section boot loader flash section boot loader flash section end rwwstart nrww end rwwstart nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end applicationstart boot loader end applicationstart boot loader end applicationstart boot loader note: 1. the parameters in the figure above are giv en in table 30-7 on page 462 . 454 8266c-mcu wireless-08/11 ATMEGA128RFA1 30.4 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibi lity to select different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 31-2 on page 465 for further details. the boot lock bits can be set in software and in serial or parallel programming mode , but they can be cleared by a chip erase command only. the general write lock (lo ck bit mode 2) does not control the programming of the flash memory by spm instruct ion. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by (e)lpm/spm, if it is attempted. 30.4.1 entering the boot loader program entering the boot loader takes place by a jump or c all from the application program. this may be initiated by a trigger such as a comman d received via usart, or spi interface. alternatively, the boot reset fuse can b e programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applicat ion code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fus e is programmed, the reset vector will always point to the boot loader reset a nd the fuse can only be changed through the serial or parallel programming interfac e. table 30-2. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 30-7 on page 462 ) note: 1. ?1? means unprogrammed, ?0? means programm ed 30.5 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer consists of the z- registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. not e that the rampz register is only implemented when the program space is larger than 6 4k bytes. 23 22 21 20 19 18 17 16 bit 15 14 13 12 11 10 9 8 rampz rampz1 rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7 z6 z5 z4 z3 z2 z1 z0 7 6 5 4 3 2 1 0 455 8266c-mcu wireless-08/11 ATMEGA128RFA1 since the flash is organized in pages (see "table 31-7" on page 468 ), the program counter can be treated as having two different sect ions. one section, consisting of the least significant bits, is addressing the words wit hin a page, while the most significant bits are addressing the pages. this is shown in figure 30-3 below . note that the page erase and page write operations are addressed indep endently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a programming operation is initiated, the address is latched and the z-pointer can be used fo r other operations. the (e)lpm instruction uses the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also bit z0 of th e z-pointer is used. figure 30-3. addressing the flash during spm program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word page pcword[pagemsb:0]: 0001 02 pageend page pcword pcpage pcmsb pagemsb program counter note: 1. the different variables used in figure 30-3 above are listed in table 30-6 on page 461 . 30.6 self-programming the flash the program memory is updated in a page by page fas hion. before programming a page with the data stored in the temporary page buf fer, the page must be erased. the temporary page buffer is filled one word at a time using spm. the buffer must be filled before the page write command. required sequence for self-programming the flash: ? perform a page erase, ? fill temporary page buffer, ? perform a page write; if only a part of the page needs to be changed, the rest of the page must be stored before the erase, and then be rewritten. the tempor ary page buffer can be accessed in a random sequence. it is essential that the page ad dress used in both the page erase 456 8266c-mcu wireless-08/11 ATMEGA128RFA1 and page write operation is addressing the same pag e. for an assembly code example see "simple assembly code example for a boot loader" on page 459. 30.6.1 performing page erase by spm to execute page erase, set up the address in the z- pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles aft er writing spmcsr. the data in r1 and r0 is ignored. the page address must be writ ten to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section ca n be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 30.6.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within f our clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will be auto -erased after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm pa ge load operation, all data loaded is still buffered. 30.6.3 performing a page write to execute page write, set up the address in the z- pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles aft er writing spmcsr. the data in r1 and r0 is ignored. the page address must be writ ten to pcpage. other bits in the z-pointer must be written to zero during this opera tion. ? page write to the rww section: the nrww section ca n be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 30.6.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls sectio n to avoid that an interrupt is accessing the rww section when it is blocked for re ading. how to move the interrupts is described in "interrupts" on page 212 . 30.6.5 consideration while updating bls special care must be taken if the user allows the b oot loader section to be updated by leaving boot lock bit11 un-programmed. an accidenta l write to the boot loader itself can corrupt the entire boot loader, and further sof tware updates might be impossible. if it is not necessary to change the boot loader softw are itself, it is recommended to program the boot lock bit11 to protect the boot loa der software from any internal software changes. 457 8266c-mcu wireless-08/11 ATMEGA128RFA1 30.6.6 prevent reading the rww section during self- programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itsel f must prevent that this section is addressed during the self programming operation. th e rwwsb in the spmcsr will be set as long as the rww section is busy. during self -programming the interrupt vector table should be moved to the bls as described in "interrupts" on page 212 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwws b by writing the rwwsre. see "simple assembly code example for a boot loader" on page 459 for an example. 30.6.7 setting the boot loader lock bits by spm to set the boot loader lock bits and general lock b its, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within f our clock cycles after writing spmcsr. bit 7 6 5 4 3 2 1 0 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 see table 31-2 on page 465 for how the different settings of the boot loader bits affect the flash access. if bits 5:0 in r0 are cleared (zero), the correspon ding lock bit will be programmed if an spm instruction is executed within four cycles afte r blbset and spmen are set in spmcsr. the z-pointer is don?t care during this ope ration, but for future compatibility it is recommended to load the z-pointer with 0x0001 (s ame as used for reading the lock bits). for future compatibility it is also recommen ded to set bits 7 and 6 in r0 to ?1? when writing the lock bits. when programming the lo ck bits the entire flash can be read during the operation. 30.6.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the signature row, fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommende d that the user checks the status bit (eepe) in the eecr register and verifies that t he bit is cleared before writing to the spmcsr register. 30.6.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset a nd spmen bits in spmcsr. when an (e)lpm instruction is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits wil l auto-clear upon completion of reading the lock bits or if no (e)lpm instruction i s executed within three cpu cycles or no spm instruction is executed within four cpu cycl es. when blbset and spmen are cleared, (e)lpm will work as described in the instr uction set manual. bit 7 6 5 4 3 2 1 0 rd - - blb12 blb11 blb02 blb01 lb2 lb1 the algorithm for reading the fuse low byte is simi lar to the one described above for reading the lock bits. to read the fuse low byte, l oad the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an (e )lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown on 458 8266c-mcu wireless-08/11 ATMEGA128RFA1 the next page. refer to (see "table 31-5" on page 467 ) for a detailed description and mapping of the fuse low byte. bit 7 6 5 4 3 2 1 0 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 similarly, load 0x0003 in the z-pointer for reading the fuse high byte. when an (e)lpm instruction is executed within three cycles after t he blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) w ill be loaded in the destination register as shown below. refer to "table 31-4" on page 466 for detailed description and mapping of the fuse high byte. bit 7 6 5 4 3 2 1 0 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 load 0x0002 in the z-pointer for reading the extend ed fuse byte. when an (e)lpm instruction is executed within three cycles after t he blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte (ef b) will be loaded in the destination register as shown below. refer to table 31-3 on page 466 for detailed description and mapping of the extended fuse byte. bit 7 6 5 4 3 2 1 0 rd - - - - - efb2 efb1 efb0 fuse and lock bits that are programmed will be read as zero. fuse and lock bits that are un-programmed will be read as one. 30.6.10 reading the signature row from software to read the signature row from software, load the z -pointer with the signature byte address given in table 30-3 below and set the sigrd and spmen bits in spmcsr. when a lpm instruction is executed within three cpu cycles after the sigrd and spmen bits are set in spmcsr, the signature byte va lue will be loaded in the destination register. the sigrd and spmen bits will auto-clear upon completion of reading the signature row or if no lpm instruction is executed within three cpu cycles. when sigrd and spmen are cleared, lpm will work as described in the instruction set manual. the signature row cannot be read during an eeprom write/erase operation. table 30-3. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 0x0001 note: 2. all other addresses are reserved for futur e use. 30.6.11 preventing flash corruption during periods of v devdd <1.8v, the flash program can be corrupted because t he supply voltage is too low for the cpu and the flash to ope rate properly. these issues are the same as for board level systems using flash, and th e same design solutions should be applied. a flash program corruption can be caused by two sit uations when the voltage is too low. first, a regular write sequence to the flash r equires a minimum voltage to operate 459 8266c-mcu wireless-08/11 ATMEGA128RFA1 correctly. secondly, the cpu itself can execute ins tructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updat es. 2. keep the avr reset active (low) during periods o f insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if n ot, an external low v devdd reset protection circuit can be used. if a reset occurs w hile a write operation is in progress, the write operation will be completed under the con dition that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode durin g periods of low v devdd . this will prevent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash f rom unintentional writes. 30.6.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 30-4 below shows the typical programming time for flash accesses fro m the cpu. table 30-4. spm programming time symbol min programming time max programming time flash write (page write, and write lock bits by spm) 3.7 ms 4.5 ms flash write (page erase) 7.3 ms 8.9 ms 30.6.13 simple assembly code example for a boot loa der assembly code example ( 1 ) ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section ; can be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the ; boot loader section or that the interrupts are disabled. .equ pagesizeb=pagesize*2 ;pagesizeb is page in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 462 8266c-mcu wireless-08/11 ATMEGA128RFA1 variable value corresponding z-value (2) description (1) zpagemsb z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used; the zpagemsb equals pagemsb + 1. pcpage pc[15:7] z16 (3) :z8 program counter page address: page select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) notes: 1. z0: should be zero for all spm commands, byte select for the (e)lpm instruction. 2. see "addressing the flash during self-programming" on page 454 for details about the use of z-pointer during self-programming. 3. the z-register is only 16 bits wide. bit 16 is l ocated in the rampz register in the i/o map. table 30-7. boot size configuration with 128 kbyte of flash mem ory ( 1 ) bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 512 words 4 0x0000 ? 0xfdff 0xfe00 ? 0xffff 0xfdff 0xfe00 1 0 1024 words 8 0x0000 ? 0xfbff 0xfc00 ? 0xffff 0xfbff 0xfc00 0 1 2048 words 16 0x0000 ? 0xf7ff 0xf800 ? 0xffff 0xf7ff 0xf800 0 0 4096 words 32 0x0000 ? 0xefff 0xf000 ? 0xffff 0xefff 0xf000 note: 1. the different bootsz fuse configurations a re shown in figure 30-2 on page 453 . 30.7 register description 30.7.1 spmcsr ? store program memory control regist er bit 7 6 5 4 3 2 1 0 $37 ($57) spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/write rw r rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 the store program memory control register contains the control bits needed to control the boot loader operations. note: only one spm inst ruction should be active at any time. ? bit 7 ? spmie - spm interrupt enable 463 8266c-mcu wireless-08/11 ATMEGA128RFA1 when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm re ady interrupt will be executed as long as the spmen bit in the spmcr register is clea red. ? bit 6 ? rwwsb - read while write section busy when a self-programming (page erase or page write) operation to the rww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operatio n is completed. alternatively the rwwsb bit will automatically be cleared if a page l oad operation is initiated. ? bit 5 ? sigrd - signature row read if this bit is written to one at the same time as s pmen, the next lpm instruction within three clock cycles will read a byte from the signat ure row into the destination register. a spm instruction within four cycles after sigrd and spmen are set, will have no effect. this operation is reserved for future use and shoul d not be used. ? bit 4 ? rwwsre - read while write section read enab le when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by ha rdware). to re-enable the rww section, the user software must wait until the prog ramming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles r e-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is written while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. ? bit 3 ? blbset - boot lock bit set if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z pointer are ignored. the blbse t bit will automatically be cleared upon completion of the lock bit set, or if no spm i nstruction is executed within four clock cycles. a lpm instruction within three cycles after blbset and spmen are set in the spmcr register, will read either the lock-bits or t he fuse bits (depending on z0 in the z pointer) into the destination register. ? bit 2 ? pgwrt - page write if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles executes page write, with the dat a stored in the temporary buffer. the page address is taken from the high part of the z p ointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon complet ion of a page write, or if no spm instruction is executed within four clock cycles. t he cpu is halted during the entire page write operation if the nrww section is address ed. ? bit 1 ? pgers - page erase if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles executes page erase. the page add ress is taken from the high part of the z pointer. the data in r1 and r0 are ignored. t he pgers bit will auto-clear upon completion of a page erase, or if no spm instructio n is executed within four clock cycles. the cpu is halted during the entire page wr ite operation if the nrww section is addressed. ? bit 0 ? spmen - store program memory enable this bit enables the spm instruction for the next f our clock cycles. if written to one together with either rwwsre, blb-set, pgwrt or pger s, the following spm instruction will have a special meaning, see descri ption above. if only spmen is written, 464 8266c-mcu wireless-08/11 ATMEGA128RFA1 the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z pointer. the lsb of the z pointe r is ignored. the spmen bit will auto-clear upon completion of an spm instruction, o r if no spm instruction is executed within four clock cycles. during page erase and pag e write, the spmen bit remain high until the operation is completed. writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. 30.7.2 nemcr ? flash extended-mode control-register bit 7 6 5 4 3 2 1 0 na ($75) resx7 eneam aeam1 aeam0 resx3 resx2 resx1 resx0 nem cr read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 1 0 1 0 the flash extended-mode control-register handles th e extended address-mode of the extra rows. ? bit 7 ? resx7 - reserved ? bit 6 ? eneam - enable extended address mode for ex tra rows when active high, the extended address mode of the extra rows is enabled. the address is decoded from bits aeam1:0 of this regist er. ? bit 5:4 ? aeam1:0 - address for extended address mo de of extra rows these bits are only used when bit eneam of this reg ister is set high. then aeam1:0 are used to decode the addresses of the extra rows. a value of 0 decodes the default factory row that is also accessible when the extend ed address mode is deactivated. table 30-8 aeam register bits register bits value description 0 factory row 1 user row 1 2 user row 2 aeam1:0 3 user row 3 ? bit 3:0 ? resx3:0 - reserved 465 8266c-mcu wireless-08/11 ATMEGA128RFA1 31 memory programming 31.1 program and data memory lock bits the ATMEGA128RFA1 provides six lock bits which can be left un-programmed (?1?) or can be programmed (?0?) to obtain the additional fe atures listed in table 31-2 below . the lock bits can only be erased to ?1? with the ch ip erase command. table 31-1. lock bit byte (1) lock bit byte bit no description default value ? 7 ? 1 (un-programmed) ? 6 ? 1 (un-programmed) blb12 5 boot lock bit 1 (un-programmed) blb11 4 boot lock bit 1 (un-programmed) blb02 3 boot lock bit 1 (un-programmed) blb01 2 boot lock bit 1 (un-programmed) lb2 1 lock bit 1 (un-programmed) lb1 0 lock bit 1 (un-programmed) note: 1. ?1? means un-programmed, ?0? means program med. table 31-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 2 1 0 further programming of the flash and eeprom is disabled in parallel, jtag and serial programming mode. the fuse bits are locked in parallel, jtag an d serial programming mode. (1) 3 0 0 further programming and verification of the flash a nd eeprom is disabled in parallel, jtag and serial programming mode. the boot lock bits and fuse bits are locked in parallel, jtag and serial programming mode. (1) blb0 mode bl02 bl01 1 1 1 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the applicatio n section. 3 0 0 spm is not allowed to write to the application sect ion, and (e)lpm executing from the boot loader section is not allowed to read from the application section . if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing fr om the application section. 4 0 1 (e)lpm executing from the boot loader section is no t allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing fr om the application section. 466 8266c-mcu wireless-08/11 ATMEGA128RFA1 memory lock bits protection type blb1 mode bl12 bl11 1 1 1 no restrictions for spm or (e)lpm accessing the boo t loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 (e)lpm executing from the application section is no t allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing fr om the boot loader section. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means un-programmed, ?0? means programmed. 31.2 fuse bits the ATMEGA128RFA1 has three fuse bytes. table 31-3 below ? table 31-5 on page 467 describe briefly the functionality of all the f uses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. table 31-3. extended fuse byte fuse low byte bit no description default value ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 reserved 3 do not modify 1 (un-programmed) bodlevel2 (1) 2 brown-out detector trigger level 1 (un-programme d) bodlevel1 (1) 1 brown-out detector trigger level 1 (un-programme d) bodlevel0 (1) 0 brown-out detector trigger level 0 (programmed) notes: 1. see table 35-23 on page 510 for bodlevel fuse decoding. table 31-4. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable on-chip debugging (ocd) 1 (un-programmed, ocd disabled) jtagen 6 enable jtag interface 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading (spi) 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (un-programmed) 467 8266c-mcu wireless-08/11 ATMEGA128RFA1 fuse high byte bit no description default value eesave 3 eeprom memory is preserved through the chip erase 1 (un-programmed, eeprom not preserved) bootsz1 2 select boot size (see table 30-7 on page 462 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 30-7 on page 462 for details) 0 (programmed) (2) bootrst 0 select reset vector 1 (un-programmed) notes: 1. the spien fuse is not accessible in seria l programming mode. 2. the default value of bootsz1:0 results in maximu m boot size. see table 30-7 on page 462 for details. 3. see "wdtcsr ? watchdog timer control register" on page 185 for details. 4. never ship a product with the ocden fuse program med regardless of the setting of lock bits and jtagen fuse. a programmed ocden fu se enables some parts of the clock system to be running in all slee p modes. this may increase the power consumption. table 31-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (un-programmed) sut1 5 select start-up time 1 (un-programmed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (un-programmed) (2) cksel0 0 select clock source 0 (programmed) (2) notes: 1. the default value of sut1:0 results in ma ximum start-up time for the default clock source. see "system control and reset" on page 178 for details. 2. the default setting of cksel3:0 results in inter nal rc oscillator @ 8 mhz. see "table 11-1" on page 149 for details. 3. the ckout fuse allows the system clock to be out put on porte7. see "clock output buffer" on page 153 for details. 4. see "system clock prescaler" on page 153 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program th e fuse bits before programming the lock bits. 31.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the pa rt leaves programming mode. this does not apply to the eesave fuse which will take e ffect once it is programmed. the fuses are also latched on power-up in normal mode. 468 8266c-mcu wireless-08/11 ATMEGA128RFA1 31.3 signature bytes all atmel microcontrollers have a three-byte signat ure code which identifies the device. this code can be read in both serial and parallel m ode, also when the device is locked. the three bytes reside in a separate address space. for the ATMEGA128RFA1 the signature bytes are given in table 31-6 below . accessing the signature bytes from software is described in section "reading the signature row from software" on page 458 . table 31-6. device and jtag id signature byte number jtag part 0 1 2 part number manufacturer id ATMEGA128RFA1 0x1e 0xa7 0x01 0xa701 0x1f 31.4 calibration byte the ATMEGA128RFA1 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in t he signature address space. during reset, this byte is automatically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. 31.5 page size table 31-7. number of words in a page and number of pages in t he flash flash size page size pcword no. of pages pcpage pcmsb 64k words (128k bytes) 128 words pc[6:0] 512 pc[15: 7] 15 table 31-8. number of bytes in a page and number of pages in t he eeprom eeprom size page size pcword no. of pages pcpage eeamsb 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11 31.6 parallel programming parameters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the ATMEGA128RFA1. 31.6.1 signal names in this section, some pins of the ATMEGA128RFA1 are referenced by signal names describing their functionality during parallel prog ramming; see figure 31-1 on page 469 and table 31-9 on page 469. pins not described in this table are ref erenced by their default pin names. the xa1/xa0 pins determine the action executed when the clki pin is given a positive pulse. the bit coding is shown in table 31-12 on page 470. when pulsing wr ___ or oe __ or, the command loaded determines the action execu ted. the different commands are shown in table 31-13 on page 470. 469 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 31-1. parallel programming (1) note: 1. unused pins should be left floating. table 31-9. pin name mapping signal name in programming mode pin name i/o function rdy/bsy ___ pd1 o 0: device is busy programming, 1: device is ready for new command. oe __ pd2 i output enable (active low). wr ___ pd3 i write pulse (active low). bs1 pd4 i byte select 1. xa0 pd5 i xtal action bit 0. xa1 pd6 i xtal action bit 1. pagel pd7 i program memory and eeprom data page load. bs2 pe2 i byte select 2. data pb7-0 i/o bi-directional data bus (output when oe is low). table 31-10. bs2 and bs1 encoding bs2 bs1 flash / eeprom address flash data loading / reading fuse programming reading fuse and lock bits 0 0 low byte low byte low byte fuse low byte 0 1 high byte high byte high byte lock bits 1 0 extended high byte reserved extended byte extended fuse byte 1 1 reserved reserved reserved fuse high byte 470 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 31-11. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 31-12. xa1 and xa0 encoding xa1 xa0 action when clki is pulsed 0 0 load flash or eeprom address (high or low address b yte determined by bs2 and bs1). 0 1 load data (high or low data byte for flash determin ed by bs1). 1 0 load command. 1 1 no action, idle. table 31-13. command byte bit encoding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 31.7 parallel programming pulses of clki and in the following command sequenc es are assumed to be at least 250 ns wide unless otherwise noted. 31.7.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 3.3v between devdd and dvss. 2. set rstn to 0 and tst to 0. 3. set the prog_enable pins listed in table 31-11 above to ?0000? and wait at least 100ns. 4. set tst to 1. tst can be set high any time befor e but not after the rising edge of rstn (t tstrnh ). 5. set rstn to 1. any activity on prog_enable pins within 100 ns after rstn is set to 1 will cause the device to fail entering programming mode. 6. wait at least 50 s before sending a command. 471 8266c-mcu wireless-08/11 ATMEGA128RFA1 31.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be cons idered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the cont ents of the entire eeprom (unless the eesave fuse is programmed) and flash after a ch ip erase. ? address high byte needs only be loaded before prog ramming or reading a new 256 word window in flash or 256 byte eeprom. this consi deration also applies to signature bytes reading. 31.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory ha s been completely erased. the fuse bits are not changed. a chip erase must be per formed before the flash and/or eeprom are reprogrammed. note: 1. the eeprom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loadi ng. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give clki a positive pulse. this loads the comma nd. 5. give wr ___ a negative pulse. this starts the chip erase. rdy/ bsy ___ goes low. 6. wait until rdy/bsy ___ goes high before loading a new command. 31.7.4 programming the flash the flash is organized in pages; see table 31-7 on page 468. when programming the flash, the program data is latched into a page buff er. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loadi ng. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give clki a positive pulse. this loads the comma nd. b. load address low byte (address bits 7:0) 1. set xa1, xa0 to ?00?. this enables address loadi ng. 2. set bs2, bs1 to ?00?. this selects the address l ow byte. 3. set data = address low byte (0x00 - 0xff). 4. give clki a positive pulse. this loads the addre ss low byte. 472 8266c-mcu wireless-08/11 ATMEGA128RFA1 c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give clki a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give clki a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the da ta bytes. (see figure 31-3 on page 473 for signal waveforms). f. repeat b through e until the entire buffer is fi lled or until all data within the page is loaded. while the lower bits in the address are mapped to w ords within the page, the higher bits address the pages within the flash. this is illustr ated in figure 31-5 on page 473. note that if less than eight bits are required to addres s words in the page (page size < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte (address bits15:8) 1. set xa1, xa0 to ?00?. this enables address load ing. 2. set bs2, bs1 to ?01?. this selects the address h igh byte. 3. set data = address high byte (0x00 - 0xff). 4. give clki a positive pulse. this loads the addre ss high byte. h. load address extended high byte (address bits 23 :16) 1. set xa1, xa0 to ?00?. this enables address load ing. 2. set bs2, bs1 to ?10?. this selects the address h igh byte. 3. set data = address extended high byte (0x00 - 0x ff). 4. give clki a positive pulse. this loads the addre ss extended high byte. i. program page 1. set bs2, bs1 to ?00? 2. give wr ___ a negative pulse. this starts programming of the e ntire page of data. rdy/bsy ___ goes low. 3. wait until rdy/bsy ___ goes high (see figure 31-3 on page 473 for signal waveforms). j. repeat b through i until the entire flash is pro grammed or until all data has been programmed. 473 8266c-mcu wireless-08/11 ATMEGA128RFA1 k. end page programming 1. set xa1, xa0 to ?10?. this enables command loadi ng. 2. set data to ?0000 0000?. this is the command for no operation. 3. give clki a positive pulse. this loads the comma nd, and the internal write signals are reset. figure 31-5. addressing the flash which is organized in pages (1) program memory word address within a page page address within the flash instruction word page pcword[pagemsb:0]: 0001 02 pageend page pcword pcpage pcmsb pagemsb program counter note: 1. pcpage and pcword are listed in table 31-7 on page 468. figure 31-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to t he programming description above. 31.7.5 programming the eeprom the eeprom is organized in pages; see table 31-8 on page 468. when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programmi ng algorithm for the eeprom data memory is as follows (refer to "programming the flash" on page 471 for details on command, address and data loading): 474 8266c-mcu wireless-08/11 ATMEGA128RFA1 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is fi lled. l: program eeprom page 1. set bs2, bs1 to ?00?. 2. give wr ___ a negative pulse. this starts programming of the e eprom page. rdy/bsy ___ goes low. 3. wait until to rdy/bsy ___ goes high before programming the next page (see figure 31- 7 below for signal waveforms). figure 31-7. programming the eeprom waveforms data xa1 xa0 bs1 bs2 clki wr rdy/bsy rstn oe pagel 0x11 addr.low data xx addr.low data xx addr.high a g b c e b c e l k 31.7.6 reading the flash the algorithm for reading the flash memory is as fo llows (refer to "programming the flash" on page 471 for details on command and address loadin g): 1. a: load command ?0000 0010?. 2. h: load address extended high byte (0x00 - 0xff) . 3. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe __ to ?0?, and bs1 to ?0?. the flash word low byte ca n now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe __ to ?1?. 31.7.7 reading the eeprom the algorithm for reading the eeprom memory is as f ollows (refer to "programming the flash" on page 471 for details on command and address loadin g): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe __ to ?0?, and bs1 to ?0?. the eeprom data byte can n ow be read at data. 475 8266c-mcu wireless-08/11 ATMEGA128RFA1 5. set oe __ to ?1?. 31.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr ___ a negative pulse and wait for rdy/bsy ___ to go high. 31.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?01?. this selects high data byt e. 4. give wr ___ a negative pulse and wait for rdy/bsy ___ to go high. 5. set bs2, bs1 to ?00?. this selects low data byte . 31.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bit s is as follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?10?. this selects extended data byte. 4. give wr ___ a negative pulse and wait for rdy/bsy ___ to go high. 5. set bs2, bs1 to ?00?. this selects low data byte . figure 31-8. programming the fuses waveforms 31.7.11 programming the lock bits the algorithm for programming the lock bits is as f ollows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0010 0000?. 476 8266c-mcu wireless-08/11 ATMEGA128RFA1 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is active (lb1 and lb2 are programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr ___ a negative pulse and wait for rdy/bsy ___ to go high. the lock bits can only be cleared by executing chip erase. 31.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0000 0100?. 2. set oe __ to ?0?, and bs2, bs1 to ?00?. the status of the fu se low bits can now be read at data (?0? means programmed). 3. set oe __ to ?0?, and bs2, bs1 to ?11?. the status of the fu se high bits can now be read at data (?0? means programmed). 4. set oe __ to ?0?, and bs2, bs1 to ?10?. the status of the ex tended fuse bits can now be read at data (?0? means programmed). 5. set oe __ to ?0?, and bs2, bs1 to ?01?. the status of the lo ck bits can now be read at data (?0? means programmed). 6. set oe __ to ?1?. figure 31-9. mapping between bs1, bs2 and the fuse and lock bit s during read lock bits 01 bs2 fuse high byte 01 bs1 data fuse low byte 01 bs2 extended fuse byte 31.7.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe __ to ?0? and bs to ?0?. the selected signature byte can now be read at data. 4. set oe __ to ?1?. 31.7.14 reading the calibration byte the algorithm for reading the calibration byte is a s follows (refer to "programming the flash" on page 471 for details on command and data loading): 1. a: load command ?0000 1000?. 477 8266c-mcu wireless-08/11 ATMEGA128RFA1 2. b: load address low byte, 0x00. 3. set oe __ to ?0? and bs1 to ?1?. the calibration byte can no w be read at data. 4. set oe __ to ?1?. 31.7.15 parallel programming characteristics figure 31-10. parallel programming timing including some general timing requirements data & control (data, xa0/1, bs1, bs2) clki t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl figure 31-11. parallel programming loading sequence with timing requirements (1) clki pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) note: 1. the timing requirements shown in figure 31-10 above (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. 478 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 31-12. parallel programming reading sequence (within the same page) with timing requirements (1) clki oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz note: 1. the timing requirements shown in figure 31-10 on page 477 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. table 31-14. parallel programming characteristics, v devdd = 3.3v 10% symbol parameter min typ max units t tstrnh delay tst high before rstn high 0 ns t dvxh data and control valid before clki high 67 ns t xlxh clki low to clki high 200 ns t xhxl clki pulse width high 150 ns t xldx data and control hold after clki low 67 ns t xlwl clki low to wr ___ low 0 ns t xlph clki low to pagel high 0 ns t plxh pagel low to clki high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr ___ low 67 ns t plwl pagel low to wr ___ low 67 ns t bvwl bs2/1 valid to wr ___ low 67 ns t wlwh wr ___ pulse width low 150 ns t wlrl wr ___ low to rdy/bsy ___ low 0 1 s t wlrh wr ___ low to rdy/bsy ___ high (1) 3.7 4.5 ms t wlrh_ce wr ___ low to rdy/bsy ___ high for chip erase (2) 12 14.5 ms t xlol clki low to oe __ low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe __ low to data valid 250 ns t ohdz oe __ high to data tri-stated 250 ns 479 8266c-mcu wireless-08/11 ATMEGA128RFA1 notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 31.8 serial downloading both the flash and eeprom memory arrays can be prog rammed using a serial programming bus while rstn is pulled to dvss. the s erial programming interface consists of pins sck, pdi (input) and pdo (output). after rstn is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 31-15 below , the pin mapping for serial programming is listed. 31.8.1 serial programming pin mapping table 31-15. pin mapping serial programming symbol pins i/o description pdi pb2 i serial data in pdo pb3 o serial data out sck pb1 i serial clock figure 31-13. serial programming and verify (1)(2) notes: 1. if the device is clocked by the internal oscillator, it is not required to connect a clock source to the clki pin. 2. v devdd -0.3v < v evdd < v devdd +0.3v, both v evdd and v devdd must stay in valid supply voltage limits. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operatio n turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be pre sent. the minimum low and high periods for the serial clock (sck) input are define d as follows: 480 8266c-mcu wireless-08/11 ATMEGA128RFA1 low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz; high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz; 31.8.2 serial programming algorithm when writing serial data to the ATMEGA128RFA1, data is clocked on the rising edge of sck. when reading data from the ATMEGA128RFA1, data is c locked on the falling edge of sck. see figure 31-15 on page 482 for timing details. to program and verify the ATMEGA128RFA1 in the seri al programming mode, the following sequence is recommended (see four byte in struction formats in table 31-17 on page 481): 1. power-up sequence: apply power between devdd and dvss while rstn and sck are set to ?0?. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, rstn must b e given a positive pulse of at least two cpu clock cycles duration after sck has b een set to ?0?. 2. wait for at least 20 ms and enable serial progra mming by sending the programming enable serial instruction to pin pdi. 3. the serial programming instructions will not wor k if the communication is out of synchronization. when in sync. the second byte (0x5 3), will echo back when issuing the third byte of the programming enable instructio n. whether the echo is correct or not, all four bytes of the instruction must be tran smitted. if the 0x53 did not echo back, give rstn a positive pulse and issue a new pr ogramming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is ap plied for a given address. the program memory page is stored by loading the write program memory page instruction with the address lines 15:8. before iss uing this command, make sure the instruction load address extended high byte has bee n used to define the msb of the address. the address extended high byte with th e address lines 23:16 is stored until the command is re-issued, i.e., the command n eeds only be issued for the first page, and when crossing the 64k word boundary. if p olling (rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page (see table 31-16 on page 481). accessing the serial programming interf ace before the flash write operation completes can result in incorrect program ming. 5. the eeprom array is programmed one byte at a tim e by supplying the address and data together with the appropriate write instructio n. an eeprom memory location is first automatically erased before new data is writt en. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 31-16 on page 481). in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output pd o. when reading the flash memory, use the instruction load address extended h igh byte to define the upper address byte, which is not included in the read pro gram memory instruction. the address extended high byte with the address lines 2 3:16 is stored until the command is re-issued, i.e., the command needs only be issue d for the first page, and when crossing the 64k word boundary. 7. at the end of the programming session, rstn can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1? . turn devdd power off. 481 8266c-mcu wireless-08/11 ATMEGA128RFA1 table 31-16. minimum wait delay before writing the next fuse/fl ash/eeprom location symbol minimum wait delay t wd_fuse 4.5 ms t wd_flash 4.5 ms t wd_eeprom 13 ms t wd_chiperase 14.5 ms 31.8.3 serial programming instruction set table 31-17 below and figure 31-14 on page 482 describe the instruction set. table 31-17. serial programming instruction set (5)(6) instruction format (2) instruction/operation byte1 byte2 byte3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instruction load address extended high byte (1) $4d $00 extended addr. $00 load program memory page, high byte $48 $00 addr. l sb high data byte in load program memory page, low byte $40 $00 addr. ls b low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instruction read program memory, high byte $28 addr. msb addr. lsb high data byte out read program memory, low byte $20 addr. msb addr. l sb low data byte out read eeprom memory $a0 0000 aaaa aaaa aaaa data byt e out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (3)(4) write program memory page $4c addr. msb addr. lsb $ 00 write eeprom memory $c0 0000 aaaa aaaa aaaa data by te in write eeprom memory page (page access) $c2 0000 aaa a aaaa 00 $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in notes: 1. not all instructions are applicable for a ll parts. 2. a = address. 3. bits are programmed ?0?, un-programmed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be un-programmed (?1?). 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 482 8266c-mcu wireless-08/11 ATMEGA128RFA1 instruction format (2) 6. see http://www.atmel.com/avr for application not es regarding programming and programmers. if the lsb in rdy/bsy data byte out is ?1?, a programming operation i s still pending. wait until this bit returns ?0? before the next ins truction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buffer, program the eeprom page; see figure 31-14 below . figure 31-14. serial programming instruction example byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory pag e 0 pag e 1 pag e 2 pag e n-1 pag e buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb pag e offset pag e number adr msb adr msb adr msb adr msb adr msb adr lsb adr lsb adr lsb adr lsb adr lsb 31.8.4 serial programming characteristics for characteristics of the serial programming modul e see "spi timing characteristics" on page 512 . figure 31-15. serial programming waveforms msbmsb lsblsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output 483 8266c-mcu wireless-08/11 ATMEGA128RFA1 31.9 programming via the jtag interface programming through the jtag interface requires con trol of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtagen fu se must be programmed. the device is default shipped with the fuse programmed. in addition, the jtd bit in mcucr must be cleared. alternatively, if the jtd bit is s et, the external reset can be forced low. then, the jtd bit will be cleared after two chip cl ocks, and the jtag pins are available for programming. this provides a means of using the jtag pins as normal port pins in running mode while still allowing in-system program ming via the jtag interface. note that this technique can not be used when using the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be dedicated for this purpose. during programming the clock frequency of the tck i nput must be less than the maximum frequency of the chip. the system clock pre scaler can not be used to divide the tck clock input into a sufficiently low frequen cy. as a definition in this datasheet, the lsb is shift ed in and out first of all shift registers. 31.9.1 programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. the jtag instructions useful for programming are listed belo w. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap-controller is us ed to generate internal clocks. it can also be used as an idle state between jtag sequence s. the state machine sequence for changing the instruction word is shown in figure 31-16 on page 484. 484 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 31-16. state machine sequence for changing the instruction word test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 31.9.2 avr_reset (0xc) the avr specific public jtag instruction is used fo r setting the avr device in the reset mode or taking the device out from the reset mode. the tap-controller is not reset by this instruction. the one bit reset regist er is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 31.9.3 prog_enable (0x4) the avr specific public jtag instruction enables pr ogramming via the jtag port. the 16-bit programming enable register is selected as d ata register. the active states are the following: ? shift-dr: the programming enable signature is shif ted into the data register. 485 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? update-dr: the programming enable signature is com pared to the correct value, and programming mode is entered if the signature is valid. 31.9.4 prog_commands (0x5) the avr specific public jtag instruction is used fo r entering programming commands via the jtag port. the 15-bit programming command r egister is selected as data register. the active states are the following: ? capture-dr: the result of the previous command is loaded into the data register. ? shift-dr: the data register is shifted by the tck input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to t he flash inputs. ? run-test/idle: one clock cycle is generated, execu ting the applied command. 31.9.5 prog_pageload (0x6) the avr specific public jtag instruction directly l oads the flash data page via the jtag port. an 8-bit flash data byte register is sel ected as the data register. this is physically the 8 lsb?s of the programming command r egister. the active states are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte regi ster is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr state, starting with the low byte for the first update-dr encounter ed after entering the prog_pageload command. the program counter is pre-i ncremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counte r increment into the next page. 31.9.6 prog_pageread (0x7) the avr specific public jtag instruction directly c aptures the flash content via the jtag port. an 8-bit flash data byte register is sel ected as the data register. this is physically the 8 lsb?s of the programming command r egister. the active states are the following: ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates bet ween reading the low and the high byte for each new capture-dr state, starting w ith the low byte for the first capture-dr encountered after entering the prog_page read command. the program counter is post-incremented after reading e ach high byte, including the first read byte. this ensures that the first data is capt ured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. ? shift-dr: the flash data byte register is shifted by the tck input. 31.9.7 data registers the data registers are selected by the jtag instruc tion registers described in section "programming specific jtag instructions" on page 483. the data registers relevant for programming operations are: ? reset register 486 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? programming enable register ? programming command register ? flash data byte register 31.9.8 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering pr ogramming mode. a high value in the reset register corresponds to p ulling the external reset low. the part is reset as long as there is a high value pres ent in the reset register. depending on the fuse settings for the clock options, the par t will remain reset for a reset time- out period (refer to "clock sources" on page 149 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in "figure 29-2" on page 444 . 31.9.9 programming enable register the programming enable register is a 16-bit registe r. the content of this register is compared to the programming enable signature, binar y code 1010_0011_0111_0000. when the content of the register is equal to the pr ogramming enable signature, programming via the jtag port is enabled. the regis ter is reset to 0 on power-on reset, and should always be reset when leaving prog ramming mode. figure 31-17. programming enable register tdi tdo d a t a = d q clockdr & prog_enable programming enable 0xa370 31.9.10 programming command register the programming command register is a 15-bit regist er. this register is used to serially shift in programming commands, and to seri ally shift out the result of the previous command, if any. the jtag programming inst ruction set is shown in table 31-18 on page 487. the state sequence when shifting in the programming commands is illustrated in figure 31-19 on page 490. 487 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 31-18. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits table 31-18. jtag programming instruction (set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care) instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 x xxxx o x_xxxxxxxx (2) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxx xxxx 2b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 2c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 2d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2e. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2f. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2g. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. poll for page write complete 0110111_00000000 x xxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxx xxx 3b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 3c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 3d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 488 8266c-mcu wireless-08/11 ATMEGA128RFA1 instruction tdi sequence tdo sequence notes 3e. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxx xxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. poll for page write complete 0110011_00000000 x xxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxx xxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxx xxx 6b. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3)(6) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse write complete 0110111_00000000 x xxxx o x_xxxxxxxx (2) 6e. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3)(7) 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse write complete 0110111_00000000 x xxxx o x_xxxxxxxx (2) 6h. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3)(8) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse write complete 0110011_00000000 x xxxx o x_xxxxxxxx (2) 7a. enter lock bit write 0100011_00100000 xxxxxxx_x xxxxxxx 7b. load data byte 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4)(9) 489 8266c-mcu wireless-08/11 ATMEGA128RFA1 instruction tdi sequence tdo sequence notes 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit write complete 0110011_000000 00 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxx xx_xxxxxxxx 8b. read extended fuse byte 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo (6)(5) 8c. read fuse high byte 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo (7)(5) 8d. read fuse low byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo (8)(5) 8e. read lock bits 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (9)(5) 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxx xxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 x xxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx notes: 1. this command sequence is not required if the seven msb?s are correctly set by the previous c ommand sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fus e, ?1? to un-program the fuse. 4. set bits to ?0? to program the corresponding loc k bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = un-programmed. 6. the bit mapping for fuses extended byte is liste d in table 31-3 on page 466. 7. the bit mapping for fuses high byte is listed in table 31-4 on page 466. 8. the bit mapping for fuses low byte is listed in table 31-5 on page 467. 9. the bit mapping for lock bits byte is listed in table 31-1 on page 465. 10. address bits exceeding pcmsb and eeamsb ( table 31-7 on page 468 and table 31-8 on page 468) are don?t care. 11. all tdi and tdo sequences are represented by bi nary digits. 490 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 31-19. state machine sequence for changing/reading the da ta word test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 31.9.11 flash data byte register the flash data byte register provides an efficient way to load the entire flash page buffer before executing page write, or to read out/ verify the content of the flash. a state machine sets up the control signals to the fl ash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of t he 8-bit scan chain and an 8-bit temporary register. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initi ates a write sequence that within 11 tck cycles loads the content of the temporary regis ter into the flash page buffer. the avr automatically alternates between writing the lo w and the high byte for each new update-dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program cou nter is pre-incremented before writing the low byte, except for the first w ritten byte. this ensures that the first data is written to the address set up by prog_comma nds, and loading the last location in the page buffer does not make the progr am counter increment into the next page. 491 8266c-mcu wireless-08/11 ATMEGA128RFA1 during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered a fter entering the prog_pageread command. the program counter is post- incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into t he next page. figure 31-20. flash data byte register tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine the state machine controlling the flash data byte r egister is clocked by tck. during normal operation in which eight bits are shifted fo r each flash byte, the clock cycles needed to navigate through the tap-controller autom atically feeds the state machine for the flash data byte register with sufficient nu mber of clock pulses to complete its operation transparently for the user. however, if t oo few bits are shifted between each update-dr state during page load, the tap-controlle r should stay in the run-test/idle state for some tck cycles to ensure that there are at least 11 tck cycles between each update-dr state. 31.9.12 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 31-18 on page 487. 31.9.13 entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0 011_0111_0000 in the programming enable register. 31.9.14 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0 000_0000_0000 in the programming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. 492 8266c-mcu wireless-08/11 ATMEGA128RFA1 31.9.15 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1 a. 3. poll for chip erase complete using programming i nstruction 1b, or wait for t wlrh_ce (refer to table 31-14 on page 478). 31.9.16 programming the flash before programming the flash a chip erase must be p erformed, see section "performing chip erase" above . 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load extended high byte of address using program ming instruction 2b. 4. load high byte of address using programming inst ruction 2c. 5. load low byte of address using programming instr uction 2d. 6. load data using programming instructions 2e, 2f and 2g. 7. repeat steps 5 and 6 for all instruction words i n the page. 8. write the page using programming instruction 2h. 9. poll for flash write complete using programming instruction 2i, or wait for t wlrh (refer to table 31-14 on page 478). 10. repeat steps 4 to 9 until all data have been pr ogrammed. a more efficient data transfer can be achieved usin g the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instruct ions 2b, 2c and 2d. pcword (refer to table 31-7 on page 468) is used to address within one page and m ust be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruct ion words in the page byte-by-byte, starting with the lsb of the first instruction in t he page and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte register into the flash page location and to auto-increment the program counter before each new word. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2h. 8. poll for flash write complete using programming instruction 2i, or wait for t wlrh (refer to table 31-14 on page 478). 9. repeat steps 3 to 8 until all data have been pro grammed. 31.9.17 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b, 3c and 3d. 4. read data using programming instruction 3e. 5. repeat steps 3 and 4 until all data have been re ad. 493 8266c-mcu wireless-08/11 ATMEGA128RFA1 a more efficient data transfer can be achieved usin g the prog_pageread instruction: 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instruct ions 3b, 3c and 3d. pcword (refer to table 31-7 on page 468) is used to address within one page and m ust be written as 0. 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first instruct ion in the page (flash) and ending with the msb of the last instruction in the page (f lash). the capture-dr state both captures the data from the flash, and also auto-inc rements the program counter after each word is read. note that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been rea d. 31.9.18 programming the eeprom the eeprom must be erased before being programmed. a chip erase always erases both flash and eeprom memories, see "performing chip erase" on page 492. 1. enter jtag instruction prog_commands. 2. enable eeprom write using programming instructio n 4a. 3. load high byte of address using programming inst ruction 4b. 4. load low byte of address using programming instr uction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the p age. 7. write the data using programming instruction 4f. 8. poll for eeprom write complete using programming instruction 4g, or wait for t wlrh (refer to table 31-14 on page 478). 9. repeat steps 3 to 8 until all data have been pro grammed. note that the prog_pageload instruction can not be used when programming the eeprom. 31.9.19 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b a nd 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been re ad. note that the prog_pageread instruction can not be used when reading the eeprom. 31.9.20 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6a. 494 8266c-mcu wireless-08/11 ATMEGA128RFA1 3. load data high byte using programming instructio ns 6b. a bit value of ?0? will program the corresponding fuse; a ?1? will un-progr am the fuse. 4. write fuse high byte using programming instructi on 6c. 5. poll for fuse write complete using programming i nstruction 6d, or wait for t wlrh (refer to table 31-14 on page 478). 6. load data low byte using programming instruction s 6e. a ?0? will program the fuse, a ?1? will un-program the fuse. 7. write fuse low byte using programming instructio n 6f. 8. poll for fuse write complete using programming i nstruction 6g, or wait for t wlrh (refer to table 31-14 on page 478). 31.9.21 programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write using programming instruct ion 7a. 3. load data using programming instructions 7b. a b it value of ?0? will program the corresponding lock bit, a ?1? will leave the lock b it unchanged. 4. write lock bits using programming instruction 7c . 5. poll for lock bit write complete using programmi ng instruction 7d, or wait for t wlrh (refer to table 31-14 on page 478). 31.9.22 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming inst ruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instru ction 8b. to only read fuse low byte, use programming instruc tion 8c. to only read lock bits, use programming instruction 8d. 31.9.23 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming ins truction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming inst ruction 9c. 5. repeat steps 3 and 4 with address 0x01 and addre ss 0x02 to read the second and third signature bytes, respectively. 31.9.24 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming i nstruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming inst ruction 10c. 495 8266c-mcu wireless-08/11 ATMEGA128RFA1 32 application circuits 32.1 basic application schematic a basic application schematic of the ATMEGA128RFA1 with a single-ended rf connector is shown in figure 32-1 below and the associated bill of material in table 32- 1 on page 496. the 50 single-ended rf input is transformed to the 100 differential rf port impedance using balun b1. the capacitors c1 and c2 provide ac coupling of the rf input to the rf port, capacitor c4 improves matching. figure 32-1. basic application schematic 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 56 57 58 59 60 61 62 63 aref avss avss rfp rfn avss tst dvss dvdd dvdd xtal2 devdd dvss avdd evdd avss xtal1 41 42 43 44 45 46 47 48 pb0 dvss pe0 pb7 cb3 cb4 rstn v dd xtal cx1 cx2 cb1 v dd cb2 c1 c2 b1 rf c4 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 rston xtal 32khz cx3 cx4 clki devdd dvss devdd pe7 dvss devdd pf0 pf7 pg0 pg5 pd0 pd7 pins tst & clki must be connected the power supply bypass capacitors (cb2, cb4) are c onnected to the external analog supply pin (evdd, pin 59) and external digital supp ly pin (devdd, pin 23). pins 34, 44 and 54 supply the digital port pins. floating pins can cause excessive power dissipation (e.g. during power on). they should be connected to an appropriate source. gpio shall not be connected to ground or power supply directly. the digital input pins tst and clki must be connect ed. if pin tst will never be used it can be connected to avss while an unused pin clki c ould be connected to dvss (see chapter "unused pins" on page 6 ). ATMEGA128RFA1 496 8266c-mcu wireless-08/11 ATMEGA128RFA1 capacitors cb1 and cb3 are bypass capacitors for th e integrated analog and digital voltage regulators to ensure stable operation and t o improve noise immunity. capacitors should be placed as close as possible to the pins and should have a low- resistance and low-inductance connection to ground to achieve the best performance. the crystal (xtal), the two load capacitors (cx1, c x2), and the internal circuitry connected to pins xtal1 and xtal2 form the 16mhz cr ystal oscillator for the 2.4ghz transceiver. to achieve the best accuracy and stabi lity of the reference frequency, large parasitic capacitances must be avoided. crystal lin es should be routed as short as possible and not in proximity of digital i/o signal s. this is especially required for the high data rate modes. the 32.768 khz crystal connected to the internal lo w power (sub 1 a) crystal oscillator provides a stable time reference for all low power modes including 32 bit ieee 802.15.4 symbol counter ( "mac symbol counter" on page 134 ) and real time clock application using the asynchronous timer t/c2 ( "8-bit timer/counter2 with pwm and asynchronous operation" on page 310 ). total shunt capacitance including cx3, cx4 should not exceed 15pf across both pins. the very l ow supply current of the oscillator requires careful layout of the pcb and any leakage path must be avoided. crosstalk and radiation from switching digital sign als to the crystal pins or the rf pins can degrade the system performance. the programming of minimum drive strength settings for the digital output signal is recommend ed (see "dpds0 ? port driver strength register 0" on page 175 ). table 32-1. bill of materials (bom) designator description value manufacturer part numb er comment b1 smd balun smd balun / filter 2.4 ghz wuerth johanson technology 748421245 2450fb15l0001 filter included cb1 cb3 ldo vreg bypass capacitor 1 f (100nf minimum) cb2 cb4 power supply bypass capacitor 1 f (100nf minimum) avx murata 0603yd105kat2a grm188r61c105ka12d x5r (0603) 10% 16v cx1, cx2 16mhz crystal load capacitor 12 pf avx murata 06035a120ja grp1886c1h120ja01 cog (0603) 5% 50v cx3, cx4 32.768khz crystal load capacitor 12 ? 25 pf c0g 5% c1, c2 rf coupling capacitor 22 pf epcos epcos avx b37930 b37920 06035a220jat2a (0402 or 0603) 50v c4 (optional) rf matching 0.47 pf johnstech xtal crystal cx-4025 16 mhz sx-4025 16 mhz acal taitjen siward xwbbpl-f-1 a207-011 xtal 32khz crystal rs=100 kohm 32.2 extended feature set application schematic the ATMEGA128RFA1 supports additional features like : ? security module (aes) ? high data rate mode up to 2mbits/s ? antenna diversity using alternate pin function dig 1/2 at port g and f 497 8266c-mcu wireless-08/11 ATMEGA128RFA1 ? rx/tx indicator using alternate pin function dig3/ 4 at port g and f an extended feature set application schematic illus trating the use of the ATMEGA128RFA1 extended feature set, is shown in figure 32-2 below . figure 32-2. extended feature application schematic 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 56 57 58 59 60 61 62 63 aref avss avss rfp rfn avss tst dvss dvdd dvdd xtal2 devdd dvss avdd evdd avss xtal1 41 42 43 44 45 46 47 48 pb0 dvss pe0 pb7 cb3 cb4 rstn v dd xtal cx1 cx2 cb1 v dd cb2 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 rston xtal 32khz cx3 cx4 clki devdd dvss devdd pe7 dvss devdd pf0 pf7 pg0 pg5 pd0 pd7 balun rf- switch ant0 ant1 rf- switch b1 sw1 sw2 pa lna n1 n2 pins tst & clki must be connected although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinati ons. ATMEGA128RFA1 498 8266c-mcu wireless-08/11 ATMEGA128RFA1 33 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0x1ff) trxfbend trxfbend7 trxfbend6 trxfbend5 trxf bend4 trxfbend3 trxfbend2 trxfbend1 trxfbend0 133 ... (0x180) trxfbst trxfbst7 trxfbst6 trxfbst5 trxfbst4 trxfbst3 trxfbst2 trxfbst1 trxfbst0 133 (0x17f) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x17e) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x17d) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x17c) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x17b) tst_rx_length rx_length7 rx_length6 rx_leng th5 rx_length4 rx_length3 rx_length2 rx_length1 rx_ length0 133 (0x17a) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x179) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x178) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x177) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x176) tst_ctrl_digi res7 res6 res5 res4 tst_ctrl_ dig3 tst_ctrl_dig2 tst_ctrl_dig1 tst_ctrl_dig0 132 (0x175) reserved res7 res6 res5 res4 res3 res2 res1 res0 ... (0x173) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x172) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x171) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x170) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x16f) csma_be max_be3 max_be2 max_be1 max_be0 min _be3 min_be2 min_be1 min_be0 131 (0x16e) csma_seed_1 aack_fvn_mode1 aack_fvn_mode0 aack_set_pd aack_dis_ack aack_i_am_coord csma_seed_12 csma_seed_11 csma_seed_10 130 (0x16d) csma_seed_0 csma_seed_07 csma_seed_06 csma_seed_05 csma_seed_04 csma_seed_03 csma_seed_02 csma_seed_01 csma_seed_00 130 (0x16c) xah_ctrl_0 max_frame_retries3 max_frame_retries2 max_frame_retries1 max_frame_retries0 max_csma_retries2 max_csma_retries1 max_csma_retries0 slotted_operation 128 (0x16b) ieee_addr_7 ieee_addr_77 ieee_addr_76 ieee_ addr_75 ieee_addr_74 ieee_addr_73 ieee_addr_72 ieee _addr_71 ieee_addr_70 128 (0x16a) ieee_addr_6 ieee_addr_67 ieee_addr_66 ieee_ addr_65 ieee_addr_64 ieee_addr_63 ieee_addr_62 ieee _addr_61 ieee_addr_60 128 (0x169) ieee_addr_5 ieee_addr_57 ieee_addr_56 ieee_ addr_55 ieee_addr_54 ieee_addr_53 ieee_addr_52 ieee _addr_51 ieee_addr_50 127 (0x168) ieee_addr_4 ieee_addr_47 ieee_addr_46 ieee_ addr_45 ieee_addr_44 ieee_addr_43 ieee_addr_42 ieee _addr_41 ieee_addr_40 127 (0x167) ieee_addr_3 ieee_addr_37 ieee_addr_36 ieee_ addr_35 ieee_addr_34 ieee_addr_33 ieee_addr_32 ieee _addr_31 ieee_addr_30 127 (0x166) ieee_addr_2 ieee_addr_27 ieee_addr_26 ieee_ addr_25 ieee_addr_24 ieee_addr_23 ieee_addr_22 ieee _addr_21 ieee_addr_20 126 (0x165) ieee_addr_1 ieee_addr_17 ieee_addr_16 ieee_ addr_15 ieee_addr_14 ieee_addr_13 ieee_addr_12 ieee _addr_11 ieee_addr_10 126 (0x164) ieee_addr_0 ieee_addr_07 ieee_addr_06 ieee_ addr_05 ieee_addr_04 ieee_addr_03 ieee_addr_02 ieee _addr_01 ieee_addr_00 126 (0x163) pan_id_1 pan_id_17 pan_id_16 pan_id_15 pan_ id_14 pan_id_13 pan_id_12 pan_id_11 pan_id_10 126 (0x162) pan_id_0 pan_id_07 pan_id_06 pan_id_05 pan_ id_04 pan_id_03 pan_id_02 pan_id_01 pan_id_00 125 (0x161) short_addr_1 short_addr_17 short_addr_16 short_addr_15 short_addr_14 short_addr_13 short_addr_12 short_addr_11 short_addr_10 125 (0x160) short_addr_0 short_addr_07 short_addr_06 short_addr_05 short_addr_04 short_addr_03 short_addr_02 short_addr_01 short_addr_00 125 (0x15f) man_id_1 man_id_17 man_id_16 man_id_15 man_ id_14 man_id_13 man_id_12 man_id_11 man_id_10 124 (0x15e) man_id_0 man_id_07 man_id_06 man_id_05 man_ id_04 man_id_03 man_id_02 man_id_01 man_id_00 124 (0x15d) version_num version_num7 version_num6 version_num5 version_num4 version_num3 version_num2 version_num1 version_num0 124 (0x15c) part_num part_num7 part_num6 part_num5 part _num4 part_num3 part_num2 part_num1 part_num0 123 (0x15b) pll_dcu pll_dcu_start res6 res5 res4 res3 res2 res1 res0 123 (0x15a) pll_cf pll_cf_start res6 res5 res4 res3 res 2 res1 res0 122 (0x159) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x158) ftn_ctrl ftn_start res6 res5 res4 res3 res2 res1 res0 122 (0x157) xah_ctrl_1 res1 res0 aack_fltr_res_ft aack_ upld_res_ft res aack_ack_time aack_prom_mode res 121 ... reserved (0x155) rx_syn rx_pdt_dis res2 res1 res0 rx_pdt_lev el3 rx_pdt_level2 rx_pdt_level1 rx_pdt_level0 120 ... reserved (0x152) xosc_ctrl xtal_mode3 xtal_mode2 xtal_mode1 xtal_mode0 xtal_trim3 xtal_trim2 xtal_trim1 xtal_tr im0 119 (0x151) batmon bat_low bat_low_en batmon_ok batmon_ hr batmon_vth3 batmon_vth2 batmon_vth1 batmon_vth0 118 (0x150) vreg_ctrl avreg_ext avdd_ok res5 res4 res3 d vdd_ok res1 res0 116 (0x14f) irq_status awake tx_end ami cca_ed_done rx_ end rx_start pll_unlock pll_lock 116 (0x14e) irq_mask awake_en tx_end_en ami_en cca_ed_d one_en rx_end_en rx_start_en pll_unlock_en pll_lock_en 115 (0x14d) ant_div ant_sel res2 res1 res0 ant_div_en a nt_ext_sw_en ant_ctrl1 ant_ctrl0 114 (0x14c) trx_ctrl_2 rx_safe_mode res4 res3 res2 res1 res0 oqpsk_data_rate1 oqpsk_data_rate0 113 (0x14b) sfd_value sfd_value7 sfd_value6 sfd_value5 sfd_value4 sfd_value3 sfd_value2 sfd_value1 sfd_val ue0 113 (0x14a) rx_ctrl res7 res6 res5 res4 pdt_thres3 pdt_ thres2 pdt_thres1 pdt_thres0 112 (0x149) cca_thres cca_cs_thres3 cca_cs_thres2 cca_cs_thres1 cca_cs_thres0 cca_ed_thres3 cca_ed_thres2 cca_ed_thres1 cca_ed_thres0 111 (0x148) phy_cc_cca cca_request cca_mode1 cca_mode0 c hannel4 channel3 channel2 channel1 channel0 110 (0x147) phy_ed_level ed_level7 ed_level6 ed_level5 e d_level4 ed_level3 ed_level2 ed_level1 ed_level0 110 (0x146) phy_rssi rx_crc_valid rnd_value1 rnd_value0 rssi4 rssi3 rssi2 rssi1 rssi0 109 (0x145) phy_tx_pwr pa_buf_lt1 pa_buf_lt0 pa_lt1 pa_ lt0 tx_pwr3 tx_pwr2 tx_pwr1 tx_pwr0 107 499 8266c-mcu wireless-08/11 ATMEGA128RFA1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0x144) trx_ctrl_1 pa_ext_en irq_2_ext_en tx_auto_c rc_on res4 res3 res2 res1 res0 107 (0x143) trx_ctrl_0 res7 res6 res5 res4 res3 res2 re s1 res0 106 (0x142) trx_state trac_status2 trac_status1 trac_status0 trx_cmd4 trx_cmd3 trx_cmd2 trx_cmd1 trx_cmd0 105 (0x141) trx_status cca_done cca_status tst_status t rx_status4 trx_status3 trx_status2 trx_status1 trx_ status0 104 ... reserved (0x13f) aes_key aes_key7 aes_key6 aes_key5 aes_key4 aes_ key3 aes_key2 aes_key1 aes_key0 103 (0x13e) aes_state aes_state7 aes_state6 aes_state5 aes_state4 aes_state3 aes_state2 aes_state1 aes_sta te0 103 (0x13d) aes_status aes_er res5 res4 res3 res2 res1 res0 aes_done 102 (0x13c) aes_ctrl aes_request res aes_mode res aes_d ir aes_im res1 res0 101 (0x13b) reserved res7 res6 res5 res4 res3 res2 res1 res0 ... reserved (0x139) trxpr res3 res2 res1 res0 res3 res2 slptr t rxrst 171 ... reserved (0x137) dpds1 res5 res4 res3 res2 res1 res0 pgdrv1 pgdrv0 176 (0x136) dpds0 pfdrv1 pfdrv0 pedrv1 pedrv0 pddrv1 pd drv0 pbdrv1 pbdrv0 175 (0x135) drtram0 res1 res0 drtswok endrt res3 res2 r es1 res0 171 (0x134) drtram1 res1 res0 drtswok endrt res3 res2 r es1 res0 172 (0x133) drtram2 res7 res drtswok endrt res3 res2 re s1 res0 172 (0x132) drtram3 res1 res0 drtswok endrt res3 res2 r es1 res0 173 (0x131) lldrh res2 res1 res0 lldrh4 lldrh3 lldrh2 l ldrh1 lldrh0 174 (0x130) lldrl res3 res2 res1 res0 lldrl3 lldrl2 lld rl1 lldrl0 175 (0x12f) llcr res1 res0 lldone llcomp llcal lltco ll short llencal 173 ... reserved (0x12d) ocr5ch ocr5ch7 ocr5ch6 ocr5ch5 ocr5ch4 ocr5 ch3 ocr5ch2 ocr5ch1 ocr5ch0 301 (0x12c) ocr5cl ocr5cl7 ocr5cl6 ocr5cl5 ocr5cl4 ocr5 cl3 ocr5cl2 ocr5cl1 ocr5cl0 302 (0x12b) ocr5bh ocr5bh7 ocr5bh6 ocr5bh5 ocr5bh4 ocr5 bh3 ocr5bh2 ocr5bh1 ocr5bh0 300 (0x12a) ocr5bl ocr5bl7 ocr5bl6 ocr5bl5 ocr5bl4 ocr5 bl3 ocr5bl2 ocr5bl1 ocr5bl0 301 (0x129) ocr5ah ocr5ah7 ocr5ah6 ocr5ah5 ocr5ah4 ocr5 ah3 ocr5ah2 ocr5ah1 ocr5ah0 300 (0x128) ocr5al ocr5al7 ocr5al6 ocr5al5 ocr5al4 ocr5 al3 ocr5al2 ocr5al1 ocr5al0 300 (0x127) icr5h icr5h7 icr5h6 icr5h5 icr5h4 icr5h3 ic r5h2 icr5h1 icr5h0 302 (0x126) icr5l icr5l7 icr5l6 icr5l5 icr5l4 icr5l3 ic r5l2 icr5l1 icr5l0 302 (0x125) tcnt5h tcnt5h7 tcnt5h6 tcnt5h5 tcnt5h4 tcnt 5h3 tcnt5h2 tcnt5h1 tcnt5h0 299 (0x124) tcnt5l tcnt5l7 tcnt5l6 tcnt5l5 tcnt5l4 tcnt 5l3 tcnt5l2 tcnt5l1 tcnt5l0 299 ... reserved (0x122) tccr5c foc5a foc5b foc5c res4 res3 res2 res 1 res0 298 (0x121) tccr5b icnc5 ices5 res wgm53 wgm52 cs52 cs5 1 cs50 297 (0x120) tccr5a com5a1 com5a0 com5b1 com5b0 com5c1 c om5c0 wgm51 wgm50 295 ... reserved (0xf8) scocr1hh scocr1hh7 scocr1hh6 scocr1hh5 scocr 1hh4 scocr1hh3 scocr1hh2 scocr1hh1 scocr1hh0 141 (0xf7) scocr1hl scocr1hl7 scocr1hl6 scocr1hl5 scocr 1hl4 scocr1hl3 scocr1hl2 scocr1hl1 scocr1hl0 142 (0xf6) scocr1lh scocr1lh7 scocr1lh6 scocr1lh5 scocr 1lh4 scocr1lh3 scocr1lh2 scocr1lh1 scocr1lh0 142 (0xf5) scocr1ll scocr1ll7 scocr1ll6 scocr1ll5 scocr 1ll4 scocr1ll3 scocr1ll2 scocr1ll1 scocr1ll0 142 (0xf4) scocr2hh scocr2hh7 scocr2hh6 scocr2hh5 scocr 2hh4 scocr2hh3 scocr2hh2 scocr2hh1 scocr2hh0 142 (0xf3) scocr2hl scocr2hl7 scocr2hl6 scocr2hl5 scocr 2hl4 scocr2hl3 scocr2hl2 scocr2hl1 scocr2hl0 143 (0xf2) scocr2lh scocr2lh7 scocr2lh6 scocr2lh5 scocr 2lh4 scocr2lh3 scocr2lh2 scocr2lh1 scocr2lh0 143 (0xf1) scocr2ll scocr2ll7 scocr2ll6 scocr2ll5 scocr 2ll4 scocr2ll3 scocr2ll2 scocr2ll1 scocr2ll0 143 (0xf0) scocr3hh scocr3hh7 scocr3hh6 scocr3hh5 scocr 3hh4 scocr3hh3 scocr3hh2 scocr3hh1 scocr3hh0 143 (0xef) scocr3hl scocr3hl7 scocr3hl6 scocr3hl5 scocr 3hl4 scocr3hl3 scocr3hl2 scocr3hl1 scocr3hl0 144 (0xee) scocr3lh scocr3lh7 scocr3lh6 scocr3lh5 scocr 3lh4 scocr3lh3 scocr3lh2 scocr3lh1 scocr3lh0 144 (0xed) scocr3ll scocr3ll7 scocr3ll6 scocr3ll5 scocr 3ll4 scocr3ll3 scocr3ll2 scocr3ll1 scocr3ll0 144 (0xec) sctsrhh sctsrhh7 sctsrhh6 sctsrhh5 sctsrhh4 sctsrhh3 sctsrhh2 sctsrhh1 sctsrhh0 139 (0xeb) sctsrhl sctsrhl7 sctsrhl6 sctsrhl5 sctsrhl4 sctsrhl3 sctsrhl2 sctsrhl1 sctsrhl0 140 (0xea) sctsrlh sctsrlh7 sctsrlh6 sctsrlh5 sctsrlh4 sctsrlh3 sctsrlh2 sctsrlh1 sctsrlh0 140 (0xe9) sctsrll sctsrll7 sctsrll6 sctsrll5 sctsrll4 sctsrll3 sctsrll2 sctsrll1 sctsrll0 140 (0xe8) scbtsrhh scbtsrhh7 scbtsrhh6 scbtsrhh5 scbts rhh4 scbtsrhh3 scbtsrhh2 scbtsrhh1 scbtsrhh0 140 (0xe7) scbtsrhl scbtsrhl7 scbtsrhl6 scbtsrhl5 scbts rhl4 scbtsrhl3 scbtsrhl2 scbtsrhl1 scbtsrhl0 141 (0xe6) scbtsrlh scbtsrlh7 scbtsrlh6 scbtsrlh5 scbts rlh4 scbtsrlh3 scbtsrlh2 scbtsrlh1 scbtsrlh0 141 (0xe5) scbtsrll scbtsrll7 scbtsrll6 scbtsrll5 scbts rll4 scbtsrll3 scbtsrll2 scbtsrll1 scbtsrll0 141 (0xe4) sccnthh sccnthh7 sccnthh6 sccnthh5 sccnthh4 sccnthh3 sccnthh2 sccnthh1 sccnthh0 138 (0xe3) sccnthl sccnthl7 sccnthl6 sccnthl5 sccnthl4 sccnthl3 sccnthl2 sccnthl1 sccnthl0 139 (0xe2) sccntlh sccntlh7 sccntlh6 sccntlh5 sccntlh4 sccntlh3 sccntlh2 sccntlh1 sccntlh0 139 (0xe1) sccntll sccntll7 sccntll6 sccntll5 sccntll4 sccntll3 sccntll2 sccntll1 sccntll0 139 (0xe0) scirqs res2 res1 res0 irqsbo irqsof irqscp3 irqscp2 irqscp1 146 (0xdf) scirqm res2 res1 res0 irqmbo irqmof irqmcp3 irqmcp2 irqmcp1 147 500 8266c-mcu wireless-08/11 ATMEGA128RFA1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xde) scsr res6 res5 res4 res3 res2 res1 res0 scbsy 146 (0xdd) sccr1 res6 res5 res4 res4 res3 res2 res1 sce nbo 145 (0xdc) sccr0 scres scmbts scen sccksel sctse sccmp3 sccmp2 sccmp1 144 ... reserved (0xd1) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0xd0) reserved res7 res6 res5 res4 res3 res2 res1 res0 ... reserved (0xce) udr1 udr17 udr16 udr15 udr14 udr13 udr12 udr 11 udr10 361 (0xcd) ubrr1h res3 res2 res1 res0 ubrr11 ubrr10 ubr r9 ubrr8 365 (0xcc) ubrr1l ubrr7 ubrr6 ubrr5 ubrr4 ubrr3 ubrr2 u brr1 ubrr0 366 ... reserved (0xca) ucsr1c umsel11 umsel10 upm11 upm10 usbs1 udo rd1 ucpha1 ucpol1 377 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz 12 rxb81 txb81 376 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mp cm1 376 ... reserved (0xc6) udr0 udr07 udr06 udr05 udr04 udr03 udr02 udr 01 udr00 357 (0xc5) ubrr0h res3 res2 res1 res0 ubrr11 ubrr10 ubr r9 ubrr8 361 (0xc4) ubrr0l ubrr7 ubrr6 ubrr5 ubrr4 ubrr3 ubrr2 u brr1 ubrr0 361 ... reserved (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 udo rd0 ucpha0 ucpol0 375 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz 02 rxb80 txb80 375 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mp cm0 374 ... reserved (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 tw am0 res 407 (0xbc) twcr twint twea twsta twsto twwc twen res tw ie 403 (0xbb) twdr twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 406 (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgc e 406 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 res twps1 twps 0 404 (0xb8) twbr twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twb r1 twbr0 402 ... reserved (0xb6) assr exclkamr exclk as2 tcn2ub ocr2aub ocr2bu b tcr2aub tcr2bub 329 ... reserved (0xb4) ocr2b ocr2b7 ocr2b6 ocr2b5 ocr2b4 ocr2b3 ocr 2b2 ocr2b1 ocr2b0 328 (0xb3) ocr2a ocr2a7 ocr2a6 ocr2a5 ocr2a4 ocr2a3 ocr 2a2 ocr2a1 ocr2a0 328 (0xb2) tcnt2 tcnt27 tcnt26 tcnt25 tcnt24 tcnt23 tcn t22 tcnt21 tcnt20 328 (0xb1) tccr2b foc2a foc2b res1 res0 wgm22 cs22 cs21 cs20 327 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 res1 res0 wgm21 wgm20 326 ... reserved (0xad) ocr4ch ocr4ch7 ocr4ch6 ocr4ch5 ocr4ch4 ocr4c h3 ocr4ch2 ocr4ch1 ocr4ch0 292 (0xac) ocr4cl ocr4cl7 ocr4cl6 ocr4cl5 ocr4cl4 ocr4c l3 ocr4cl2 ocr4cl1 ocr4cl0 293 (0xab) ocr4bh ocr4bh7 ocr4bh6 ocr4bh5 ocr4bh4 ocr4b h3 ocr4bh2 ocr4bh1 ocr4bh0 292 (0xaa) ocr4bl ocr4bl7 ocr4bl6 ocr4bl5 ocr4bl4 ocr4b l3 ocr4bl2 ocr4bl1 ocr4bl0 292 (0xa9) ocr4ah ocr4ah7 ocr4ah6 ocr4ah5 ocr4ah4 ocr4a h3 ocr4ah2 ocr4ah1 ocr4ah0 291 (0xa8) ocr4al ocr4al7 ocr4al6 ocr4al5 ocr4al4 ocr4a l3 ocr4al2 ocr4al1 ocr4al0 291 (0xa7) icr4h icr4h7 icr4h6 icr4h5 icr4h4 icr4h3 icr 4h2 icr4h1 icr4h0 293 (0xa6) icr4l icr4l7 icr4l6 icr4l5 icr4l4 icr4l3 icr 4l2 icr4l1 icr4l0 293 (0xa5) tcnt4h tcnt4h7 tcnt4h6 tcnt4h5 tcnt4h4 tcnt4 h3 tcnt4h2 tcnt4h1 tcnt4h0 290 (0xa4) tcnt4l tcnt4l7 tcnt4l6 tcnt4l5 tcnt4l4 tcnt4 l3 tcnt4l2 tcnt4l1 tcnt4l0 290 ... reserved (0xa2) tccr4c foc4a foc4b foc4c res4 res3 res2 res1 res0 289 (0xa1) tccr4b icnc4 ices4 res wgm43 wgm42 cs42 cs41 cs40 288 (0xa0) tccr4a com4a1 com4a0 com4b1 com4b0 com4c1 co m4c0 wgm41 wgm40 286 ... reserved (0x9d) ocr3ch ocr3ch7 ocr3ch6 ocr3ch5 ocr3ch4 ocr3c h3 ocr3ch2 ocr3ch1 ocr3ch0 283 (0x9c) ocr3cl ocr3cl7 ocr3cl6 ocr3cl5 ocr3cl4 ocr3c l3 ocr3cl2 ocr3cl1 ocr3cl0 284 (0x9b) ocr3bh ocr3bh7 ocr3bh6 ocr3bh5 ocr3bh4 ocr3b h3 ocr3bh2 ocr3bh1 ocr3bh0 283 (0x9a) ocr3bl ocr3bl7 ocr3bl6 ocr3bl5 ocr3bl4 ocr3b l3 ocr3bl2 ocr3bl1 ocr3bl0 283 (0x99) ocr3ah ocr3ah7 ocr3ah6 ocr3ah5 ocr3ah4 ocr3a h3 ocr3ah2 ocr3ah1 ocr3ah0 282 (0x98) ocr3al ocr3al7 ocr3al6 ocr3al5 ocr3al4 ocr3a l3 ocr3al2 ocr3al1 ocr3al0 282 (0x97) icr3h icr3h7 icr3h6 icr3h5 icr3h4 icr3h3 icr 3h2 icr3h1 icr3h0 284 (0x96) icr3l icr3l7 icr3l6 icr3l5 icr3l4 icr3l3 icr 3l2 icr3l1 icr3l0 284 (0x95) tcnt3h tcnt3h7 tcnt3h6 tcnt3h5 tcnt3h4 tcnt3 h3 tcnt3h2 tcnt3h1 tcnt3h0 281 (0x94) tcnt3l tcnt3l7 tcnt3l6 tcnt3l5 tcnt3l4 tcnt3 l3 tcnt3l2 tcnt3l1 tcnt3l0 281 ... reserved 501 8266c-mcu wireless-08/11 ATMEGA128RFA1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0x92) tccr3c foc3a foc3b foc3c res4 res3 res2 res1 res0 280 (0x91) tccr3b icnc3 ices3 res wgm33 wgm32 cs32 cs31 cs30 279 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 co m3c0 wgm31 wgm30 277 ... reserved (0x8d) ocr1ch ocr1ch7 ocr1ch6 ocr1ch5 ocr1ch4 ocr1c h3 ocr1ch2 ocr1ch1 ocr1ch0 274 (0x8c) ocr1cl ocr1cl7 ocr1cl6 ocr1cl5 ocr1cl4 ocr1c l3 ocr1cl2 ocr1cl1 ocr1cl0 274 (0x8b) ocr1bh ocr1bh7 ocr1bh6 ocr1bh5 ocr1bh4 ocr1b h3 ocr1bh2 ocr1bh1 ocr1bh0 273 (0x8a) ocr1bl ocr1bl7 ocr1bl6 ocr1bl5 ocr1bl4 ocr1b l3 ocr1bl2 ocr1bl1 ocr1bl0 273 (0x89) ocr1ah ocr1ah7 ocr1ah6 ocr1ah5 ocr1ah4 ocr1a h3 ocr1ah2 ocr1ah1 ocr1ah0 272 (0x88) ocr1al ocr1al7 ocr1al6 ocr1al5 ocr1al4 ocr1a l3 ocr1al2 ocr1al1 ocr1al0 272 (0x87) icr1h icr1h7 icr1h6 icr1h5 icr1h4 icr1h3 icr 1h2 icr1h1 icr1h0 274 (0x86) icr1l icr1l7 icr1l6 icr1l5 icr1l4 icr1l3 icr 1l2 icr1l1 icr1l0 275 (0x85) tcnt1h tcnt1h7 tcnt1h6 tcnt1h5 tcnt1h4 tcnt1 h3 tcnt1h2 tcnt1h1 tcnt1h0 271 (0x84) tcnt1l tcnt1l7 tcnt1l6 tcnt1l5 tcnt1l4 tcnt1 l3 tcnt1l2 tcnt1l1 tcnt1l0 272 ... reserved (0x82) tccr1c foc1a foc1b foc1c res4 res3 res2 res1 res0 271 (0x81) tccr1b icnc1 ices1 res wgm13 wgm12 cs12 cs11 cs10 269 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 co m1c0 wgm11 wgm10 267 (0x7f) didr1 ain1d ain0d 410 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d ad c1d adc0d 434 (0x7d) didr2 adc15d adc14d adc13d adc12d adc11d adc 10d adc9d adc8d 434 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 428 (0x7b) adcsrb avddok acme refok acch mux5 adts2 adt s1 adts0 429 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 432 (0x79) adch adch7 adch6 adch5 adch4 adch3 adch2 adc h1 adch0 433 (0x78) adcl adcl7 adcl6 adcl5 adcl4 adcl3 adcl2 adc l1 adcl0 433 (0x77) adcsrc adtht1 adtht0 res0 adsut4 adsut3 adsu t2 adsut1 adsut0 433 ... reserved (0x75) nemcr res7 eneam aeam1 aeam0 res3 res2 res1 res 0 464 (0x74) reserved res7 res6 res5 res4 res3 res2 res1 res0 (0x73) timsk5 res1 res0 icie5 res ocie5c ocie5b oci e5a toie5 303 (0x72) timsk4 res1 res0 icie4 res ocie4c ocie4b oci e4a toie4 294 (0x71) timsk3 res1 res0 icie3 res ocie3c ocie3b oci e3a toie3 285 (0x70) timsk2 res4 res3 res2 res1 res0 ocie2b ocie2 a toie2 324 (0x6f) timsk1 res1 res0 icie1 res ocie1c ocie1b oci e1a toie1 275 (0x6e) timsk0 res4 res3 res2 res1 res0 ocie0b ocie0 a toie0 243 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint1 9 pcint18 pcint17 pcint16 225 (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint12 pcint1 1 pcint10 pcint9 pcint8 225 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pci nt2 pcint1 pcint0 226 (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 is c41 isc40 221 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 is c01 isc00 220 (0x68) pcicr res4 res3 res2 res1 res0 pcie2 pcie1 p cie0 224 (0x67) bgcr res bgcal_fine3 bgcal_fine2 bgcal_fine1 bgcal_fine0 bgcal2 bgcal1 bgcal0 434 (0x66) osccal cal7 cal6 cal5 cal4 cal3 cal2 cal1 ca l0 154 (0x65) prr1 res prtrx24 prtim5 prtim4 prtim3 prus art1 169 (0x64) prr0 prtwi prtim2 prtim0 prpga prtim1 prspi prusart0 pradc 169 (0x63) prr2 res3 res2 res1 res0 prram3 prram2 prram1 p rram0 170 ... reserved (0x61) clkpr clkpce res2 res1 res0 clkps3 clkps2 cl kps1 clkps0 155 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp 0 185 0x3f (0x5f) sreg i t h s v n z c 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 14 ... reserved 0x3b (0x5b) rampz res5 res4 res3 res2 res1 res0 rampz1 rampz0 14 ... reserved 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 462 ... reserved 0x35 (0x55) mcucr jtd res1 res0 pud res1 res0 ivsel ivce 205 0x34 (0x54) mcusr res2 res1 res0 jtrf wdrf borf extrf porf 185 0x33 (0x53) smcr res3 res2 res1 res0 sm2 sm1 sm0 se 168 ... reserved 0x31 (0x51) ocdr ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr 0 441 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 409 502 8266c-mcu wireless-08/11 ATMEGA128RFA1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page ... reserved 0x2e (0x4e) spdr spdr7 spdr6 spdr5 spdr4 spdr3 spdr2 spdr1 spdr 0 338 0x2d (0x4d) spsr spif wcol res4 res3 res2 res1 res0 spi2x 338 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 337 0x2b (0x4b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpio r22 gpior21 gpior20 27 0x2a (0x4a) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpio r12 gpior11 gpior10 27 ... reserved 0x28 (0x48) ocr0b ocr0b_7 ocr0b_6 ocr0b_5 ocr0b_4 ocr0b_3 ocr0b _2 ocr0b_1 ocr0b_0 243 0x27 (0x47) ocr0a ocr0a_7 ocr0a_6 ocr0a_5 ocr0a_4 ocr0a_3 ocr0a _2 ocr0a_1 ocr0a_0 242 0x26 (0x46) tcnt0 tcnt0_7 tcnt0_6 tcnt0_5 tcnt0_4 tcnt0_3 tcnt0 _2 tcnt0_1 tcnt0_0 242 0x25 (0x45) tccr0b foc0a foc0b res1 res0 wgm02 cs02 cs01 cs00 241 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 res1 res0 wgm01 wgm00 239 0x23 (0x43) gtccr tsm res4 res3 res2 res1 res0 psrasy psrsync 330 0x22 (0x42) eearh res3 res2 res1 res0 eear11 eear10 eear9 eear8 24 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eea r0 24 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr 0 25 0x1f (0x3f) eecr res1 res0 eepm1 eepm0 eerie eempe eepe eere 25 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpio r02 gpior01 gpior00 27 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 223 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf 0 223 0x1b (0x3b) pcifr res4 res3 res2 res1 res0 pcif2 pcif1 pcif0 224 0x1a (0x3a) tifr5 res1 res0 icf5 res ocf5c ocf5b ocf5a tov5 303 0x19 (0x39) tifr4 res1 res0 icf4 res ocf4c ocf4b ocf4a tov4 294 0x18 (0x38) tifr3 res1 res0 icf3 res ocf3c ocf3b ocf3a tov3 285 0x17 (0x37) tifr2 res4 res3 res2 res1 res0 ocf2b ocf2a tov2 325 0x16 (0x36) tifr1 res1 res0 icf1 res ocf1c ocf1b ocf1a tov1 276 0x15 (0x35) tifr0 res4 res3 res2 res1 res0 ocf0b ocf0a tov0 244 0x14 (0x34) portg res1 res0 portg5 portg4 portg3 portg2 portg1 portg0 210 0x13 (0x33) ddrg res1 res0 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 211 0x12 (0x32) ping res1 res0 ping5 ping4 ping3 ping2 ping1 ping0 211 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 por tf1 portf0 209 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 210 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf 0 210 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 por te1 porte0 208 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 209 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine 0 209 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 por td1 portd0 208 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 208 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind 0 208 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 por tc1 portc0 29 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 29 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc 0 29 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 por tb1 portb0 207 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 207 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb 0 207 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 por ta1 porta0 28 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 28 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina 0 28 notes: 1. reserved registers, bits and i/o memory a ddresses (marked as res*) may not be modified. 2. i/o registers within the address range 0x00 - 0x 1f are directly bit-accessible using the sbi and cb i instructions. in these registers, the value of single bits can be checked by using the sb is and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi in structions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi in structions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 ? 0x3f must be used. when a ddressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the device is a comple x microcontroller with more peripheral units than can be supported within the 6 4 location reserved in op-code for the in and out i nstructions. for the extended i/o space from 0x60 ? 0x1ff in sram, only the st/sts/st d and ld/lds/ldd instructions can be used. 503 8266c-mcu wireless-08/11 ATMEGA128RFA1 34 instruction set summary depending on the size of the flash memory the instr uctions ? eicall and eijmp do not exist in devices with 128k /64kbyte flash memory, ? elpm does not exist in the device with 64kbyte fla sh memory. 34.1 arithmetic and logic instructions mnemonics operands description operation flags #clo cks add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsig ned r1:r0 (rd x rr) << 1 z,c 2 34.2 branch instructions mnemonics operands description operation flags #clo cks rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 eijmp extended indirect jump to (z) pc (eind:z) none 2 jmp k direct jump pc k none 3 504 8266c-mcu wireless-08/11 ATMEGA128RFA1 mnemonics operands description operation flags #clo cks rcall k relative subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc z none 4 eicall extended indirect call to (z) pc (eind:z) none 4 call k direct subroutine call pc k none 5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd ? rr z,n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z,n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z,n ,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr( b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register is set if (rr(b) =1) pc pc + 2 or 3 none 1 / 2 / 3 sbic p, b skip if bit in i/o register cleared if ( p(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbis p, b skip if bit in i/o register is set if ( p(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if ( i = 1) th en pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1 / 2 34.3 bit and bit test instructions mnemonics operands description operation flags #clo cks sbi p,b set bit in i/o register i/o(p,b) 1 none 2 505 8266c-mcu wireless-08/11 ATMEGA128RFA1 mnemonics operands description operation flags #clo cks cbi p,b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set twos complement overflow v 1 v 1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1 t 1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 34.4 data transfer instructions mnemonics operands description operation flags #clo cks mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 506 8266c-mcu wireless-08/11 ATMEGA128RFA1 mnemonics operands description operation flags #clo cks ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q ) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory rd (rampz:z), rampz:z rampz:z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 34.5 mcu control instructions mnemonics operands description operation flags #clo cks nop no operation none 1 sleep sleep (see specific description for sleep function) none 1 wdr watchdog reset (see specific description for wdr/timer) none 1 break break for on-chip debug only none n/a 507 8266c-mcu wireless-08/11 ATMEGA128RFA1 35 electrical characteristics 35.1 absolute maximum ratings note that stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress ra ting only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exp osure to absolute maximum rating conditions for extended periods may affect device r eliability. symbol parameter condition min. typ. max. units t stor storage temperature -50 150 c t lead lead temperature t = 10s (soldering profile compl iant with ipc/jedec j-std-020b) 260 c v esd esd robustness compliant to [3] compliant to [4] 4 750 kv v p rf input rf level +14 dbm v ddmax maximum voltage maximum voltage from any pin to gr ound -0.3 3.6 v v dig voltage on all pins except pins 8,9,21,22,60,62 - 0.3 v ddmax v v ana voltage on pins 8,9,21,22,60,62 -0.3 2.0 v v comp_in comparator input voltage pins with comparator input connected by the analog multiplexer -0.3 v ddmax v v pga_in pga input voltage pins with pga input connected by the analog multiplexer -0.3 v ddmax v v adc_in adc input voltage pins with adc input connected b y the analog multiplexer (pga bypassed) -0.3 2.0 v 35.2 recommended operating range symbol parameter condition min. typ. max. units t op_zu operating temperature range -40 +85 c t op_zf operating temperature range -40 +125 c v dd supply voltage voltage on pins 23,34,44,54,59 (2) 1.8 3.0 3.6 v v dd1.8 supply voltage (on pins 21,22,60) external voltage supply (1) 1.7 1.8 1.9 v v ovrdrv pin overdrive voltage pin voltage exceeding supply voltage except pins 8,9,21,22,60,62 +0.3 v notes: 1. register vreg_ctrl needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8v supply, refer to section "voltage regulators (avreg, dvreg)" on page 165 . 2. even if an implementation uses the external 1.8v voltage supply v dd1.8 it is required to connect v dd . 35.3 digital pin characteristics test conditions: t op = -40c to 125c, v dd =1.8v to 3.6v (unless otherwise stated) symbol parameter condition min typ max units v ih high level input voltage (1) except pin rstn 0.7 v dd v v il low level input voltage (1) except pin rstn 0.3 v dd v 508 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min typ max units v ihrstn high level input voltage (1) pin rstn 0.9 v dd v v ilrstn low level input voltage (1) pin rstn 0.1 v dd v v oh high level output voltage (1) i oh = -12ma, v dd = 3.6v i oh = -6ma, v dd = 1.8v maximum. drive strength by dpds0/1 except pins 17,18 v dd ? 0.4 v v ol low level output voltage (1) i ol = 16ma, v dd = 3.6v i ol = 10ma, v dd = 1.8v maximum drive strength by dpds0/1 except pins 17,18 0.4 v v ohmin high level output voltage (1) i oh = -3ma, v dd = 3.6v i oh = -1.5ma, v dd = 1.8v minimum drive strength by dpds0/1 v dd ? 0.4 v v olmin low level output voltage (1) i ol = 4ma, v dd = 3.6v i ol = 2.5ma, v dd = 1.8v minimum. drive strength by dpds0/1 0.4 v r rstn reset pull-up resistor 120 360 k r gpio gpio pull-up resistor if pull-up resistor is enabl ed 120 360 k v dd = 3.6v, pin low 1 a i il input leakage current t = 25 c <10 na v dd = 3.6v, pin high 1 a i ih input leakage current t = 25 c <10 na note: 1. the capacitive load should not be larger t han 50 pf for all i/os when using the default drive r strength settings, refer to section "dpds0 ? port driver strength register 0" on page 1 75 and "dpds1 ? port driver strength register 1" on page 176 . generally, large load capacitances increase the o verall current consumption. 35.4 power supply currents (rf transceiver in sleep mode) test conditions: t op = 25c, v dd =3.0v (unless otherwise stated) symbol parameter condition / avr mode min typ max u nits standby mode 0.31 ma idle 1mhz 0.45 ma idle 8mhz 0.8 ma idle 16mhz 1.1 ma active 1mhz 0.8 ma active 8mhz 2.5 ma power supply current (prr0=0xff, prr1=0x3f, 16mhz rc oscillator selected) active 16mhz 3.7 ma active, 16mhz rc oscillator 4.0 ma active, 16mhz crystal oscillator 4.5 ma i supply power supply current (prr0=0x00, prr1=0x00) active, external 16mhz clock on clki 4.5 ma test conditions: t op = 25c, v dd =3.0v (unless otherwise stated) symbol parameter condition min typ max units i ds0 power supply current in deep_sleep avr in power down mode wdt disabled 0.25 a 509 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min typ max units i ds_pdw power down mode, wdt enabled 0.9 a i ds_psx power save mode, 32.768khz crystal oscillator enabled 1.0 a i ds_pswx power save mode, wdt and 32.768khz crystal oscillator enabled 1.65 a test conditions: v dd =3.0v (unless otherwise stated) symbol parameter condition min typ max units t = 25 c 0.25 a t = 85 c 1.5 a i ds0 deep_sleep current (transceiver in sleep mode, avr in power save/down mode, wdt disabled) t = 125 c 15.0 a 35.5 clock characteristics 35.5.1 calibrated internal rc oscillator accuracy table 35-2. calibration accuracy of internal rc oscillator frequency v devdd temperature calibration accuracy factory calibration 16 mhz 3.0v 25c 10 % user calibration 15.1 ? 17.5mhz 1.8v ? 3.6v -40c - 125c 1 % 35.5.2 external clock drive (pin clki) figure 35-1 external clock drive waveforms v il1 v ih1 table 35-3. external clock drive symbol parameter min. max. units 1/t clcl oscillator frequency 16 mhz t clcl clock period 62.5 ns t chcx high time 25 ns t clcx low time 25 ns t clch rise time 0.1 s t chcl fall time 0.1 s t clcl change in period from one clock cycle to the next 1 % 510 8266c-mcu wireless-08/11 ATMEGA128RFA1 35.6 system and reset characteristics table 35-4. reset, brown-out and internal voltage characterist ics symbol parameter condition min typ max units power-on reset threshold voltage (rising) power supply fully discharged 1.6 v v pot power-on reset threshold voltage (falling) ( 1 ) 0.05 0.3 v t pot power-on reset recovery time time of evdd/devdd 511 8266c-mcu wireless-08/11 ATMEGA128RFA1 35.7.2 voltage regulators table 35-7. timing characteristics of the voltage regulators symbol parameter condition min. typ. max. units t avreg power up time avreg c avdd = 1 f 60 s t dvreg power up time dvreg startup after power-on c dvdd = 100 nf c dvdd = 1 f 40 60 s s t dvreg power up time dvreg startup after deep_sleep c dvdd = 100 nf? 1 f 10 s 35.7.3 deep_sleep table 35-8. timing characteristics entering deep_sleep using p ower save/down symbol parameter condition min. typ. max. units t ds time to enter deep_sleep cpu sleep() instruction t o oscillator is turned off while transceiver is already in sleep state 3 clk 35.8 2-wire serial interface characteristics table 35-9 below describes the requirements for devices connected t o the 2-wire serial bus. the ATMEGA128RFA1 2-wire serial interface meet s or exceeds these requirements under the noted conditions. timing symbols refer to figure 35-2 on page 512. table 35-9. 2-wire serial bus requirements symbol parameter condition min max units v il input low-voltage -0.5 0.3v dd v v ih input high-voltage 0.7v dd v dd +0.5 v v hys ( 1 ) hysteresis of schmitt trigger inputs 0.05v dd ( 2 ) v v ol ( 1 ) output low-voltage 3 ma sink current 0 0.4 v t r ( 1 ) rise time for both sda and scl 20+0.1c b ( 2 , 3 ) 300 ns t of ( 1 ) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf ( 3 ) 20+0.1c b ( 2 , 3 ) 250 ns t sp ( 1 ) spikes suppressed by the input filter 0 50 ( 2 ) ns i i input current each i/o pin 0.1v dd < v i < 0.9v dd -10 10 a c i ( 1 ) capacitance for each i/o pin 10 pf f scl scl clock frequency f ck ( 4 ) >max(16f scl ,250 khz) ( 5 ) 0 400 khz v dd -0.4v 1000 ns f scl 100 khz 3ma c b v dd -0.4v 300 ns rp value of pull-up resistor f scl > 100 khz 3ma c b f scl 100 khz 4.0 s t hd;sta hold time (repeated) start condition f scl > 100 khz 0.6 s f scl 100 khz ( 6 ) 4.7 s t low low period of the scl clock f scl > 100 khz ( 7 ) 1.3 s 512 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min max units f scl 100 khz 4.0 s t high high period of the scl clock f scl > 100 khz 0.6 s f scl 100 khz 4.7 s t su;sta set-up time for a repeated start condition f scl > 100 khz 0.6 s f scl 100 khz 0 s t hd;dat data hold time f scl > 100 khz 0 s f scl 100 khz 250 ns t su;dat date setup time f scl > 100 khz 100 ns f scl 100 khz 4.0 s t su;sto setup time for stop condition f scl > 100 khz 0.6 s f scl 100 khz 4.7 s t buf bus free time between a stop and start condition f scl > 100 khz 1.3 s notes: 1. this parameter is characterized and not 1 00% tested 2. required only for f scl > 100 khz 3. c b =capacitance of one bus line in pf 4. f ck =cpu clock frequency 5. this requirement applies to all the atmega128rf a1 2-wire serial interface operation. other devices connected to the 2-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the atmega12 8rfa1 2-wire serial interface is (1/f scl ? 2/f ck ), thus f ck must be greater than 6mhz for the low time requirement to b e strictly met at f scl = 100 khz. 7. the actual low period generated by the atmega12 8rfa1 2-wire serial interface is (1/f scl ? 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, ATMEGA128RFA1 devices connected to the bus may communicated at full speed (400 khz) wi th other ATMEGA128RFA1 devices, as well as any othe r device with proper t low acceptance margin. figure 35-2. 2-wire serial bus timing t su;sta t low t high t low t of t hd;sta t hd;d at t su;dat t su;sto t buf scl sda t r 35.9 spi timing characteristics see figure 35-3 on page 513 and figure 35-4 on page 514 for details. table 35-10. spi timing parameters description mode min typ max units sck period master see "spcr ? spi control register" on page 337 . sck high/low master 50% duty cycle rise/fall time master 3.6 ns setup master 10 ns 513 8266c-mcu wireless-08/11 ATMEGA128RFA1 description mode min typ max units hold master 10 ns out to sck master 0.5 t sck sck to out master 10 ns sck to out high master 10 ns ss __ low to out slave 10 ns sck period slave 4 t ck sck high/low ( 1 ) slave 2 t ck rise/fall time slave 1600 ns setup slave 10 ns hold slave t ck sck to out slave 15 ns sck to ss __ high slave 20 ns ss __ high to tri-state slave 10 ns ss __ low to sck slave 20 ns note: 1. in spi programming mode the minimum sck hi gh/low period is 2 t clcl for f ck < 12 mhz and 3 t clcl for f ck > 12 mhz. figure 35-3. spi timing requirements (master mode) mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 6 1 2 2 3 4 5 8 7 514 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 35-4. spi timing requirements (slave mode) mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 35.10 adc characteristics table 35-11. adc electrical characteristics symbol parameter condition min typ max units v refint1 internal voltage reference 1.5 v v refint2 internal voltage reference 1.6 v v refint3 internal voltage reference avdd v r aref,ext external voltage impedance 6 i l,aref load current loading aref is not recommended. 0. 1 ma i supply,adcse supply current adc current (single ended conversio n, f clkadc = 2mhz) 0.85 1.0 ma i supply,adcd supply current adc current with pga (differential conversion, f clkadc = 1mhz) 1.75 2.0 ma table 35-12. adc characteristics, single ended channels (1)(2) symbol parameter condition min typ max units d res4m single ended conversion f clkadc 4 mhz 10 bits d res8m resolution single ended conversion f clkadc = 8 mhz 8 bits e abs500k single ended conversion v ref = 1.6v f clkadc = 500khz 2 lsb e abs2m single ended conversion v ref = 1.6v f clkadc = 2mhz 2 lsb e abs4m absolute accuracy (including inl, dnl, quantization error, gain and offset error) (3) single ended conversion v ref = 1.6v f clkadc = 4mhz 2 lsb e inl integral non-linearity (inl) single ended conversion v ref = 1.6v f clkadc = 4mhz 0.8 lsb e dnl differential non-linearity (dnl) single ended conversion v ref = 1.6v f clkadc = 4mhz -0.5 lsb e gain gain error single ended conversion v ref = 1.6v f clkadc = 4mhz 1 lsb 515 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min typ max units e offset offset error single ended conversion v ref = 1.6v f clkadc = 4mhz 1.5 lsb t conv,se conversion time free running conversion 3 240 s f clkadc clock frequency single ended conversion 8 mhz v ref reference voltage 1.5 avdd v v in,se input voltage 0 avdd v f ibw input bandwidth 20 khz c ain input sampling capacitance 14 pf r ain,ser analog series resistance (4) between pin and sampling capacitor 2 k r ain analog input resistance static load resistor of in put signal 100 m note: 1. values are guidelines only. 2. all values are valid for evdd = 3.0v. 3. absolute accuracies do not include dependencies on the absolute value of the reference voltage. 4. series resistor depends on supply voltage (mos s witch resistance ~ 1/v supply ). table 35-13. pga and adc characteristics, differential channels (1)(2)(4) symbol parameter condition min typ max units d res,d resolution all gain settings 10 bits e abs,d1 absolute accuracy (including inl, dnl, quantization error, gain and offset error) (3) gain = 1x v ref = 1.6v f clkadc = 2mhz 3 lsb e inl,d1 integral non-linearity (inl) gain = 1x v ref = 1.6v f clkadc = 2mhz 3 lsb e dnl,d1 differential non-linearity (dnl) gain = 1x v ref = 1.6v f clkadc = 2mhz -0.75 lsb e gain,d1 gain = 1x 1 e gain,d10 gain = 10x 1.5 e gain,d200 gain error gain = 200x 10 lsb e offset,d1 offset error gain = 1x v ref = 1.6v f clkadc = 2mhz 0.7 lsb t conv,d conversion time free running conversion 100 s f clkadc clock frequency single ended conversion 2 mhz v ref reference voltage 1.5 avdd v v cm input common mode voltage 0 evdd v v in,diff input differential voltage input pin voltage 0v -avdd avdd v d out,d adc conversion output -512 511 lsb f ibw,d input bandwidth 20 khz c ain,pga input sampling capacitance gain = 200x 7.5 pf r ain,ser analog series resistance (5) between pin and sampling capacitor 0.5 k r ain analog input resistance static load resistor of in put signal 100 m note: 1. values are guidelines only 2. all values are valid for evdd = 3.0v 3. absolute accuracies do not include dependencies on the absolute value of the reference voltage. 516 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min typ max units 4. performance of differential channels deteriorate s if pga output voltage is close to ground. 5. series resistor depends on supply voltage (mos s witch resistance ~ 1/v supply ). 35.11 temperature sensor characteristics table 35-14. temperature sensor characteristics symbol parameter condition min typ max units t distnocal temperature distribution typical, no calibration p erformed, t = 25 oc internal1.6v bandgap reference selected 3.5 k 35.12 transceiver electrical characteristics 35.12.1 digital interface timing characteristics test conditions: t op = 25c, v dd = 3.0v, c l = 50 pf (unless otherwise stated) symbol parameter condition min. typ. max. units t 12 aes core cycle time 24 s t irq interrupt event latency relative to the event to b e indicated 9 s t batmon battery monitor latency 2 s 35.12.2 general rf specifications test conditions (unless otherwise stated): v dd = 3.0v, f rf = 2.45 ghz, t op = 25c, measurement setup see figure 32-1 on page 495. symbol parameter condition min. typ. max. units f rf frequency range as specified in [1],[2] 2405 2480 mhz f ch channel spacing as specified in [1],[2] 5 mhz f hdr header bit rate (shr, phr) as specified in [1],[2] 250 kb/s f psdu psdu bit rate as specified in [1],[2] oqpsk_data_rate = 1 oqpsk_data_rate = 2 oqpsk_data_rate = 3 250 500 1000 2000 kb/s kb/s kb/s kb/s f chip chip rate as specified in [1],[2] 2000 kchip/s f clk crystal oscillator frequency reference oscillator 16 mhz t xtal reference oscillator settling time leaving sleep s tate to crystal clock available 215 1000 s symbol rate deviation reference frequency accuracy for correct functionality psdu bit rate 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s -60 (1) -40 -40 -30 +60 +40 +40 +30 ppm ppm ppm ppm b 20db 20 db bandwidth 2.8 mhz note: 5. a reference frequency accuracy of 40 ppm is required by [1], [2]. 517 8266c-mcu wireless-08/11 ATMEGA128RFA1 35.12.3 transmitter characteristics test conditions (unless otherwise stated): v dd = 3.0v, f rf = 2.45 ghz, t op = 25c, measurement setup see figure 32-1 on page 495 . symbol parameter condition min. typ. max. units p tx tx output power maximum configurable tx output pow er value register bit tx_pwr = 0 0 +3.5 +6 dbm p range output power range 16 steps, configurable in register phy_tx_pwr 20 db p acc output power tolerance 3 db tx return loss 100+j0 differential impedance, p tx = +3.5 dbm 10 db evm 8 %rms p harm harmonics 2 nd harmonic 3 rd harmonic -38 -45 dbm dbm p spur spurious emissions 30 ? 1000 mhz >1 ? 12.75 ghz 1.8 ? 1.9 ghz 5.15 ? 5.3 ghz complies with en 300 328/440, fcc-cfr-47 part 15, arib std-66, rss-210 -36 -30 -47 -47 dbm dbm dbm dbm 35.12.4 receiver characteristics test conditions (unless otherwise stated): v dd = 3.0v, f rf = 2.45 ghz, t op = 25c, psdu bit rate = 250 kb/s, measurement setu p see figure 32-1 on page 495 . symbol parameter condition min. typ. max. units receiver sensitivity 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s awgn channel, per 1%, psdu length 20 octets high data rate modes: psdu length 20 octets -100 -96 -94 -86 dbm dbm dbm dbm p sens antenna diversity 250 kb/s, psdu 20 octets -99 dbm rl return loss 100+j0 differential impedance 10 db nf noise figure 6 db p rxmax maximum rx input level per 1%, psdu length of 20 octets 10 dbm p acrn adjacent channel rejection: -5 mhz per 1%, psdu length of 20 octets, p rf = -82 dbm 34 db p acrp adjacent channel rejection: +5 mhz per 1%, psdu length of 20 octets, p rf = -82 dbm 38 db p aacrn alternate channel rejection: -10 mhz per 1%, psdu length of 20 octets, p rf = -82 dbm 54 db p aacrp alternate channel rejection: +10 mhz per 1%, psdu length of 20 octets, p rf = -82 dbm 54 db 518 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min. typ. max. units p spur spurious emissions: lo leakage 30 ? 1000 mhz >1 ? 12.75 ghz -71 -57 -47 dbm dbm dbm f rxtxoffs tx/rx carrier frequency offset sensitivity loss < 2 db -300 (1) +300 khz iip3 3 rd ? order intercept point at maximum gain offset freq. interf. 1 = 5 mhz offset freq. interf. 2 = 10 mhz -14 dbm iip2 2 nd ? order intercept point at maximum gain offset freq. interf. 1 = 60 mhz offset freq. interf. 2 = 62 mhz 17 dbm rssi tolerance tolerance within gain step 5 db rssi dynamic range 81 db rssi resolution 3 db rssi sensitivity defined as rssi_base_val -90 db m minimum rssi value p rf rssi_base_val 0 maximum rssi value p rf > rssi_base_val + 81 db 28 note: 1. offset equals 120 ppm 35.12.5 current consumption specifications test conditions (unless otherwise stated): v dd = 3.0v, f rf = 2.45 ghz, t op = 25c, measurement setup see figure 32-1 on page 495 . (power reduction register prr0 and prr1 are not s et). symbol parameter condition min. typ. max. units i busy_tx supply current transmit state p tx = 3.5 dbm p tx = 1.5 dbm p tx = -2.5 dbm p tx = -16.5 dbm (current consumption is reduced at v dd = 1.8v for each output power level) 14.5 10 9 8 ma ma ma ma i rx_on supply current rx_on state rx_on state 12.5 ma i rx_on_p supply current rx_on state rx_on state, with regis ter setting rx_pdt_level > 0 (1) 12.0 ma i pll_on supply current pll_on state pll_on state 5.7 ma i trx_off supply current trx_off state trx_off state 0.4 m a i sleep supply current sleep state sleep state 0.02 a note: 1. refer to section "figure 32-1" on page 495 35.12.6 crystal parameter requirements symbol parameter condition min. typ. max. units f 0 crystal frequency 16 mhz c l load capacitance 8 14 pf c 0 static capacitance 7 pf 519 8266c-mcu wireless-08/11 ATMEGA128RFA1 symbol parameter condition min. typ. max. units r 1 series resistance 100 36 typical characteristics 36.1 supply current vs. clock speed with transceive r in sleep 36.1.1 clock source 16mhz rc oscillator figure 36-5. active supply current vs. frequency (v dd = 3.0v, prr0/1 = 0xff/0x3f) -40c 25c 85c 125c 0 1 2 3 4 5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 evdd [v] current consumption [ma] frequency [mhz] 520 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-6. active supply current vs. v dd (f clk =1mhz, prr0/1 = 0xff/0x3f) -40c 25c 85c 125c 0 1 2 3 4 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] figure 36-7. active supply current vs. v dd (f clk = 16mhz, prr0/1 = 0x00/0x00) -40c 25c 85c 125c 0 1 2 3 4 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] 521 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-8. idle supply current vs. v dd (f clk = 1mhz; prr0/1 = 0xff/0x3f) -40c 25c 85c 125c 0 1 2 3 4 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] figure 36-9. idle supply current vs. v dd (f clk = 8mhz, prr0/1 = 0xff/0x3f) -40c 25c 85c 125c 0 1 2 3 4 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] 522 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.1.2 external clock source on pin clki figure 36-10. active supply current vs. frequency (v dd = 3.0v, prr0/1 = 0x00/0x00) -40c 25c 85c 125c 0 1 2 3 4 5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 clk [mhz] current consumption [ma] figure 36-11. active supply current vs. frequency (v dd = 3.0v, prr0/1 = 0xff/0x3f) -40c 25c 85c 125c 0 1 2 3 4 5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 clk [mhz] current consumption [ma] frequency [mhz] frequency [mhz] 523 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-12. idle supply current vs. frequency (v dd = 3.0v, prr0/1 set and reset) -40c prr set 25c prr set 85c prr set 125c prr set -40c no prr 25c no prr 85c no prr 125c no prr 0 1 2 3 4 5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 clk [mhz] current consumption [ma] 36.2 current consumption of bandgap source and digi tal voltage regulator the supply currents of band-gap reference source an d digital voltage regulator are part of all supply current measurement. in deep_sleep mo de both units are disabled. figure 36-13. combined supply current of bandgap source and volt age regulator -40c 25c 85c 125c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 clk [mhz] current consumption [ma] 36.3 current consumption in various transceiver sta tes the avr microcontroller is in active state with no power reduction set by the register prr0 and prr1. the clock source of the microcontrol ler is the internal 16mhz rc oscillator. frequency [mhz] evdd [v] 524 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-14. trxoff state supply current vs v dd -40c 25c 85c 125c 0 2 4 6 8 10 12 14 16 18 20 22 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] figure 36-15 . rx listen state supply current vs. v dd -40c 25c 85c 125c 0 2 4 6 8 10 12 14 16 18 20 22 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] 525 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-16. tx active state supply current vs. v dd (maximum tx output power) -40c 25c 85c 125c 0 2 4 6 8 10 12 14 16 18 20 22 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 evdd [v] current consumption [ma] 36.4 rf measurements for all rf power measurement results the calibratio n level is the differential rf input of the device. it enables an easy calculation for the different rf front-ends with external power amplifier and/or rf switches (diversity, rx/t x). the combined loss of balun, strip-line and sma connecter on the radio-controlle r-board is <1db. 36.4.1 packet error rate (per) figure 36-17. per vs. input power for 250kbit mode evdd=1.8v evdd=3.0v evdd=3.6v 0 1 2 3 4 5 6 7 8 9 10 -102.0 -100.0 -98.0 -96.0 -94.0 -92.0 -90.0 input power [dbm] per [%] 526 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.4.2 transmit power figure 36-18. tx maximum output power -40 c 25 c 85 c 125 c 0 1 2 3 4 5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage [v] tx maximum output power [dbm] figure 36-19. tx output power vs. tx_pwr in register phy_tx_pwr -40 c 125 c 25 c 85 c -20 -15 -10 -5 0 5 10 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 tx_pwr register value [#] tx output power [dbm] 527 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.5 bod threshold figure 36-20. brown-out threshold vs. temperature (rising supply voltage) bod_level=1.8 bod_level=1.9 bod_level=2.0 bod_level=2.1 bod_level=2.2 bod_level=2.3 bod_level=2.4 0 0.5 1 1.5 2 2.5 3 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 temperature [c] switch voltage level up [v] figure 36-21. brown-out threshold vs. temperature (falling supply voltage) bod_level=1.8 bod_level=1.9 bod_level=2.0 bod_level=2.1 bod_level=2.2 bod_level=2.3 bod_level=2.4 0 0.5 1 1.5 2 2.5 3 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 temperature [c] switch voltage level down [v] 528 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.6 pin driver strength figure 36-22. i/o pin output voltage vs. source current (v dd = 3.0v, dpds0=0) -40 c 25c 85c 125c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 ioh [ma] evdd-voh [v] figure 36-23. i/o pin output voltage vs. source current (25c, dp ds0=0) evdd=1.8 evdd=2.4 evdd=3.0 evdd=3.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 i_oh [ma] evdd-v_oh [v] 529 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-24. i/o pin output voltage vs. source current (25c, v dd = 3.0v) dpd=0 dpd=1 dpd=2 dpd=3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.0 5.0 10.0 15.0 20.0 25.0 30.0 ioh [ma] evdd-voh [v] figure 36-25. i/o pin output voltage vs. sink current (v dd =3.0v, dpds0 = 0) -40 c 25c 85c 125c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 iol [ma] vol [v] 530 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-26. i/o pin output voltage vs. sink current (25c, dpd s0=1) -40 degc 25 degc 85 degc 125 degc 0 0.05 0.1 0.15 0.2 0.25 0.3 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 i_ol [ma] v_ol [v] figure 36-27. i/o pin output voltage vs. sink current (25c, v dd = 3.0v) dpd=0 dpd=1 dpd=2 dpd=3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iol [ma] vol [v] 531 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.7 power-down current figure 36-28. power-down current vs. temperature (watchdog disab led) 1.8v 3.0v 3.6v 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [c] i supply [a] figure 36-29. power-down current vs. supply voltage (watchdog di sabled) -40c 25c 85c 125c 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 20 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] i supply [a] 532 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-30. power-down current vs. temperature (watchdog enabl ed) 1.8v 3.0v 3.6v 20 10 75 3 2 1 0.7 0.5 0.3 0.2 0.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [c] i supply [a] figure 36-31. power-down current vs. supply voltage (watchdog en abled) -40c 25c 85c 125c 20 10 75 3 2 1 0.7 0.5 0.3 0.2 0.1 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] i supply [a] 36.8 static adc parameter ? inl and dnl all static parameter of the adc have been obtained with f adclk = 2 mhz, sut = 10, tht = 0 and an internal reference voltage of 1.6v. 533 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-32. integral nonlinearity vs. output code (single-ended , 3.0v, 25c) -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1024 digital output code inl [lsb] figure 36-33. differential nonlinearity vs. output code (single- ended, 3.0v, 25c) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1024 digital output code dnl [lsb] 534 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-34. integral nonlinearity vs. output code (with pga, ga in=10, 3.0v, 25c) -4.0 -3.0 -2.0 -1.0 0.0 1.0 -512 -384 -256 -128 0 128 256 384 512 digital output code inl [lsb] figure 36-35. differential nonlinearity vs. output code (with pga , gain=10, 3.0v, 25c) -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -512 -384 -256 -128 0 128 256 384 512 digital output code dnl [lsb] 535 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-36. integral nonlinearity vs. temperature at v devdd = 3.6v single ended gain = 1 gain = 10 gain = 200 0 2 4 6 8 10 12 14 16 -40 -20 0 20 40 60 80 100 120 140 temperature [c] |inl| max [lsb] figure 36-37. integral nonlinearity vs. supply voltage at 25c single ended gain = 1 gain = 10 gain = 200 0 2 4 6 8 10 12 14 16 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] |inl| max [lsb] 536 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-38. differential nonlinearity vs. temperature at v evdd = 3.6v single ended gain = 1 gain = 10 gain = 200 0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80 100 120 140 temperature [c] |dnl| max [lsb] figure 36-39. differential nonlinearity vs. supply voltage v evdd at 25c single ended gain = 1 gain = 10 gain = 200 0 1 2 3 4 5 6 7 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] |dnl| max [lsb] 36.9 dynamic adc parameter ? enob the dynamic adc parameters for the single-ended cha nnels have been measured with f adclk = 4 mhz, sut = 20, tht = 0 and an internal referen ce voltage of 1.6v. the sine 537 8266c-mcu wireless-08/11 ATMEGA128RFA1 wave of the input signal had a frequency of f in,sin = 20.207 khz and peak-to-peak amplitude of v in,pp = 1.58v. figure 36-40. 2048 point fft output for a single-ended adc chann el (3.0v, 25 c) 101.04; -78.53 80.83; -71.80 60.62; -74.25 40.41; -64.27 20.21; 0.00 -120 -100 -80 -60 -40 -20 0 20 0 20 40 60 80 100 120 140 160 frequency [khz] amplitude [db] figure 36-41. effective number of bits vs. supply voltage for sin gle-ended channels -40c 25c 85c 125c 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] enob [lsb] sinad = 57.54 db enob = 9.27 bit thd = -63.08 db 538 8266c-mcu wireless-08/11 ATMEGA128RFA1 the dynamic adc parameters for the differential cha nnels with a gain of 10 have been measured with f adclk = 2 mhz, sut = 10, tht = 0 and an internal referen ce voltage of 1.6v. the input sine wave had a frequency of f in,sin = 20.124 khz and peak-to-peak amplitude of v in,pp = 0.31v. figure 36-42. 2048 point fft output for a gain=10 adc channel (3. 0v, 25 c) 60.37; -56.28 40.25; -53.42 20.12; 0.00 -120 -100 -80 -60 -40 -20 0 20 0 10 20 30 40 50 60 70 80 frequency [khz] amplitude [db] figure 36-43. effective number of bits vs. supply voltage for gai n=10 channels -40c 25c 85c 125c 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] enob [lsb] sinad = 43.59 db enob = 6.95 bit thd = -51.61 db 539 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.10 adc voltage reference figure 36-44. 1.6v adc voltage reference vs. supply voltage -40c 27c 85c 125c 1.56 1.57 1.58 1.59 1.60 1.61 1.62 1.63 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] v aref [v] 36.11 temperature sensor the temperature measurement results have been measu red with an adc clock of 500 khz, sut = 80, tht = 4 and an internal reference vo ltage of 1.6v. to enhance the accuracy and resolution the data of 128 measurement s per temperature step have been decimated. 540 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-45. measured temperature value vs. temperature and v evdd 1.8v 3.0v 3.6v -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 temperature [c] measured temperature [c] figure 36-46. error of measured temperature value meas ? ideal vs. temperature 3.0v -4 -3 -2 -1 0 1 2 3 4 -40 -20 0 20 40 60 80 100 120 140 temperature [c] mean error [c] 541 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-47. standard deviation of measured temperature vs. tem perature 3.0v -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 140 temperature [c] standard deviation [c] 36.12 internal oscillator speed figure 36-48. 128 khz rc oscillator frequency vs. osccal registe r value -40c 25c 85c 125c 0 25 50 75 100 125 150 175 200 0 32 64 96 128 160 192 224 256 osccal f rc [khz] 542 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-49. 128 khz rc oscillator frequency vs. supply voltage -40c 25c 85c 125c 0 25 50 75 100 125 150 175 200 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] f rc [khz] figure 36-50. 16 mhz rc oscillator frequency vs. osccal register value -40c 25c 85c 125c 0 4 8 12 16 20 24 0 32 64 96 128 160 192 224 256 osccal f rc [mhz] 543 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-51. 16 mhz rc oscillator frequency vs. supply voltage v devdd -40c 25c 85c 125c 0 4 8 12 16 20 24 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] f rc [mhz] 36.13 programming current the programming currents shown in the following fig ures are averaged over the entire write/erase time. the value is primarily defined by the integrated charge pump. therefore the currents for flash, eeprom, fuse- and lock-bit programming operations are similar. 544 8266c-mcu wireless-08/11 ATMEGA128RFA1 figure 36-52. programming current vs. supply voltage v devdd -40c 25c 85c 125c 0 1 2 3 4 5 6 7 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v dd [v] i supply [ma] 545 8266c-mcu wireless-08/11 ATMEGA128RFA1 37 ordering information ATMEGA128RFA1 speed (mhz) power supply ordering code package pack ing operation range 16 1.8 ? 3.6v ATMEGA128RFA1-zu pi tray industrial ( -40oc to 85oc) 16 1.8 ? 3.6v ATMEGA128RFA1-zur pi tape & reel indu strial (-40oc to 85oc) 16 1.8 ? 3.6v ATMEGA128RFA1-zf pi tray industrial ( -40oc to 125oc) 16 1.8 ? 3.6v ATMEGA128RFA1-zfr pi tape & reel indu strial (-40oc to 125oc) notes: 1. pb-free packaging, complies to european d irective for restriction of hazardous substances (r ohs directive). also halide free and fully green. 2. performance figures for 125oc are only valid for devices with ordering code ATMEGA128RFA1-zf/-zfr. package type pi 64-lead, 9 x 9 x 0.9 mm body, quad flat no-lead pac kage (qfn) 546 8266c-mcu wireless-08/11 ATMEGA128RFA1 38 packaging information pi all dimensions are in millimeters. package warpage max 0.08 mm. --- ccc 0.05 0.002 --- tolerances of form and position aaa bbb r 0.09 0.10 0.10 0.004 0.004 0.004 --- --- 0.028 0.001 0.012 0.50 bsc e e2 d2 0.020 bsc 0.65 0.25 d a2 a1 b --- 0.18 0.010 0.007 --- 0.70 0.05 0.30 0.026 0.035 max. millimeter --- nom. symbol a --- min. --- min. 0.90 max. inch --- nom. a3 0.20 ref. 9.00 bsc 5.75 5.65 5.55 e 0.354 bsc 0.008 ref. 0.219 0.222 0.226 d2 a3 a a2 a1 e2 l d e a d aaa c a d bbb c b b c e b j 0.10 m c a b pin1 id 0.20 r d ccc c seating plane r top view side view bottom view l 0.45 l 0.35 0.40 0.45 0.014 0.016 0.018 1.72 --- --- --- 0.10 9.00 bsc 0.354 bsc laser mark for pin 1 identification in this area --- 1.27 4.85 4.75 4.65 0.183 0.187 0.191 title 44306 nantes cedex 3 - france atmel nantes s.a. la chantrerie - bp 70602 drawing no. rev. drawings not scaled a pi - 64 leads - 9.0 x 9.0 mm - pitch 0.5mm quad flat no lead package qfn 02/12/2008 pi 547 8266c-mcu wireless-08/11 ATMEGA128RFA1 39 errata 39.1 ATMEGA128RFA1 revision d (1.2) ? power-chain turns off when power supply drops below 1.6v ? jtag interface reads wrong data ? csma back-off calculation has reduced degree of ran domness ? update of internal temporary registers for csma_see d register may fail ? interrupt trx24_cca_ed_done may occur twice ? acch bit of register adcsrb is not functional ? asynchronous mode of timer/counter 2 requires a run ning clock source ? write to eeprom while flash page buffer is loaded c auses additional current consumption 39.2 ATMEGA128RFA1 revision c (1.1) ? power-chain turns off when power supply drops below 1.6v ? jtag interface reads wrong data ? csma back-off calculation has reduced degree of ran domness ? update of internal temporary registers for csma_see d register may fail ? interrupt trx24_cca_ed_done may occur twice ? dvreg_ext bit is not write-protected ? endrt bits have wrong reset value ? acch bit of register adcsrb is not functional ? asynchronous mode of timer/counter 2 requires a run ning clock source ? write to eeprom while flash page buffer is loaded c auses additional current consumption 39.3 ATMEGA128RFA1 revision ab (1.0) not sampled. 39.4 compiler package winavr-20090313 in the compiler package winavr-20090313 the sram st art address has a wrong value of 0x100. in this case the variables are randomly a llocated across the extended i/o space 0x100 to 0x1ff. it causes an unpredictable be havior by random overwrite of registers (see also "jtag interface reads wrong data" on page 548 and "dvreg_ext bit is not write-protected" on page 548). problem fix/workaround use the linker option -wl,--section-start=.data= 0x800200 39.5 detailed errata description 39.5.1 power-chain turns off when power supply drop s below 1.6v if the voltage of the pins devdd drops below 1.6v, the internal power chain turns off. some hardware settings (e.g. clock source) can alte r their state unintentionally. raising the supply voltage above 1.8v again does not bring the circuit back to normal operation. this condition can happen either by lowering the po wer supply voltage below 1.6v or turn-off the supply source while other external dev ices are feeding devdd by the internal esd diodes of the io stages (e.g. hardware debugger attached to the jtag interface) (2606). if the power supply drops below 1.6v while being in deep sleep mode, the internal power chain is not affected. 548 8266c-mcu wireless-08/11 ATMEGA128RFA1 problem fix/workaround turn on the brown-out detector at any voltage level . the supply current in deep sleep does not increase. 39.5.2 jtag interface reads wrong data if the power reduction register bits associated wit h the sram?s (prram3?0 in prr2) and the 2.4ghz transceiver (prtrx24 in prr1) are set, the jtag interface reads wrong data. (2613). problem fix/workaround do not use prram3?0 in prr2 and prtrx24 in prr1. for ce pin rstn=0 and the jtag interface can erase the program memory. 39.5.3 csma back-off calculation has reduced degree of randomness the csma back-off calculation in the transceiver ex tended operating modes has a reduced degree of randomness (e.g. transceiver is i n the state tx_aret_on) (2665). problem fix/workaround initialize csma_seed registers with a random value. 39.5.4 update of internal temporary registers for c sma_seed register may fail the update of the internal temporary registers of t he csma_seed registers may fail. read/write operation to the csma_seed registers its elf works as expected (2646). problem fix/workaround a sleep cycle of the transceiver updates the intern al temporary registers. 39.5.5 interrupt trx24_cca_ed_done may occur twice when requesting a manually initiated cca measuremen t in busy_rx state and during an internal ed measurement, a trx24_cca_ed_done int errupt could be issued immediately after the request. in this case the reg ister bit cca_done is equal to 0 and an additional trx24_cca_ed_done interrupt is issued after finishing the cca measurement and register bit cca_done is set to 1 ( 2000). problem fix/workaround prevent a frame reception during manually initiated cca measurement ? make sure that trx_status is not in rx_busy (i.e. start from state pll_on) ? set bit rx_pdt_dis=1 ? switch trx_state to rx_on ? perform cca measurement ? set bit rx_pdt_dis=0 39.5.6 dvreg_ext bit is not write-protected the external mode of the dvdd voltage regulator is not write-protected. if it is enabled (dvreg_ext=1 in the register vreg_ctrl) with no ext ernal power supply for dvdd, the device leaves normal operation and can?t be rec overed by the watchdog (2658). problem fix/workaround do not write the bit dvreg_ext in the register vreg _ctrl. 549 8266c-mcu wireless-08/11 ATMEGA128RFA1 39.5.7 endrt bits have wrong reset value the endrt bits in the registers drtram3?0 have the w rong reset value. the data retention of the associated sram in deep_sleep is d isabled (2495). problem fix/workaround set endrt=1 in drtram3?0 at the beginning of the fir mware program. 39.5.8 acch bit of register adcsrb is not functiona l the acch bit of register adcsrb of the adc interfac e cannot be used to force a reset of the analog blocks. problem fix/workaround such a reset can only be achieved by disabling and re-enabling the entire adc (3094). 39.5.9 asynchronous mode of timer/counter 2 require s a running clock source the access to the registers of the timer/counter2 i n asynchronous mode requires a running clock provided by the selected asynchronous clock source (including alternate pin function amr) (3398). problem fix/workaround depending on the selected clock source apply at lea st 3 clocks to the selected input. 39.5.10 write to eeprom while flash page buffer is loaded causes additional current consumption if the eeprom is written while the page buffer of t he flash memory is loaded additional current is drawn. the same happens if th e page buffer of the eeprom is loaded and the flash memory is written (3586). problem fix/workaround if the page buffer of a non-volatile memory (eeprom or flash) is loaded the write command shall be applied immediately. do not mix op eration of flash and eeprom. 550 8266c-mcu wireless-08/11 ATMEGA128RFA1 40 revision history please note that the referring page numbers in this section are referring to this document. the referring revision in this section ar e referring to the document revision rev. 8266a-mcu wireless-12/09 1. initial release rev. 8266b-mcu wireless-03/11 1. endurance added to "data retention and endurance" on page 8 and updated 2. removed wrong references ( "eecr ? eeprom control register" on page 25 , "frequency agility" on page 83 ) 3. updated "eeprom data memory" on page 20 4. updated "boot loader support ? read-while-write self-progra mming" on page 451 5. updated "memory programming" on page 465 / "table 31-16" on page 481 6. electrical characteristics updated 7. improved temperature sensor resolution in "internal temperature measurement" on page 426 8. typical characteristics added 9. typos corrected 10. application schematics modified, chapter for u nused pins added 11. 125 oc temperature range option added 12. default fuse value changed (bod enabled with 1 .8v trigger level, bit 3 reserved) 13. "power management and sleep modes" on page 157 - notes added (1.8v operation, register access) 14. clock distribution diagram corrected 15. wdtcsr access by lds / sts (see example assemb ler listing) 16. "adc input channels" on page 419 - timing in table 27-6 on page 419 corrected 17. "differential amplifier limitations" on page 422 added rev. 8266c-mcu wireless-08/11 1. update of "deep-sleep mode" on page 157 (notes added for synchronous t/c2 mode and wake-up by the symbol counter) 2. note for cpu clock frequency added to "clock source selection and sleep/active mode operation" on page 134 3. item order in the legend of the pin drive curren t chart corrected 4. "errata" on page 547 updated 5. upper value of ed range corrected in "measurement description" on page 70 , "data interpretation" on page 74 and "phy_ed_level ? transceiver energy detection level register" on page 110 6. "table 35-4" on page 510 updated 7. "instruction set summary" on page 503 added 8. turn off time towards deep_sleep added in "power management electrical characteristics" on page 510 9. removed wrong ?_? in clock names 10. supply current using 16mhz xosc added ( "electrical characteristics" on page 507 ) 11. ant_ctrl enumeration corrected ( "ant_div ? antenna diversity control register" on page 114 ) 551 8266c-mcu wireless-08/11 ATMEGA128RFA1 12. latency note added to sub-register trac_status in "trx_state ? transceiver state control register" on page 105 13. cross reference added for register mcucr and mc usr in the chapter "boundary- scan related register in i/o memory" on page 448 and "register description" on page 205 14. x-axis corrected([hz] to [mhz]) in "supply current vs. clock speed with transceiver in sleep" on page 519 15. associated pin of internal net asvss corrected (see "pin configurations" on page 2 , asvss moved from pin 61 to pin 58) 16. chapter title "external clock drive (pin clki)" on page 509 extended 17. typos corrected (units style) 18. battery monitor latency added to "digital interface timing characteristics" on page 516 552 8266c-mcu wireless-08/11 ATMEGA128RFA1 table of contents 1 pin configurations............................... ............................................... 2 2 disclaimer....................................... ................................................... .. 2 3 overview ......................................... ................................................... .. 3 3.1 block diagram .................................. ................................................... ................... 3 3.2 pin descriptions............................... ................................................... .................... 5 3.3 unused pins .................................... ................................................... .................... 6 3.4 compatibility to atmega1281/2561 ............... ................................................... ..... 7 4 resources........................................ ................................................... . 7 5 about code examples.............................. .......................................... 8 6 data retention and endurance..................... ..................................... 8 6.1 data retention................................. ................................................... .................... 8 6.2 endurance of the code memory (flash) ........... .................................................. 8 6.3 endurance of the data memory (eeprom) .......... ................................................ 8 7 avr cpu core..................................... ................................................ 9 7.1 introduction................................... ................................................... ....................... 9 7.2 architectural overview ......................... ................................................... ............... 9 7.3 alu ? arithmetic logic unit .................... ................................................... .......... 10 7.4 status register ................................ ................................................... .................. 11 7.5 general purpose register file .................. ................................................... ........ 12 7.6 stack pointer .................................. ................................................... ................... 13 7.7 instruction execution timing ................... ................................................... .......... 15 7.8 reset and interrupt handling ................... ................................................... ......... 15 8 avr memories..................................... .............................................. 18 8.1 in-system reprogrammable flash program memory.. ........................................ 18 8.2 sram data memory ............................... ................................................... .......... 18 8.3 eeprom data memory ............................. ................................................... ....... 20 8.4 eeprom register description .................... ................................................... ..... 24 8.5 i/o memory..................................... ................................................... ................... 26 8.6 general purpose i/o registers .................. ................................................... ....... 27 8.7 other port registers........................... ................................................... ............... 28 9 low-power 2.4 ghz transceiver.................... .................................. 30 9.1 features ....................................... ................................................... ..................... 30 9.2 general circuit description .................... ................................................... ........... 31 9.3 transceiver to microcontroller interface....... ................................................... ..... 32 9.4 operating modes ................................ ................................................... ............... 36 553 8266c-mcu wireless-08/11 ATMEGA128RFA1 9.5 functional description......................... ................................................... .............. 62 9.6 module description............................. ................................................... ............... 75 9.7 radio transceiver usage........................ ................................................... .......... 84 9.8 radio transceiver extended feature set ......... ................................................... 86 9.9 continuous transmission test mode.............. ................................................... .. 97 9.10 abbreviations................................. ................................................... .................. 99 9.11 reference documents........................... ................................................... ........ 101 9.12 register description .......................... ................................................... ............ 101 10 mac symbol counter .............................. ..................................... 134 10.1 main features................................. ................................................... ............... 134 10.2 clock source selection and sleep/active mode o peration ............................... 134 10.3 32 bit register access (atomic read/write) .... ................................................ 135 10.4 symbol counter (32 bit, sccnt) ................ ................................................... .. 135 10.5 symbol counter sfd timestamp register (32 bit, sctsr, read only) ........ 135 10.6 symbol counter beacon timestamp register (32 b it, scbtsr) .................... 136 10.7 compare unit (3x 32 bit, scocr1, scocr2, scocr 3) ............................... 136 10.8 interrupt control registers ................... ................................................... ......... 136 10.9 backoff slot counter .......................... ................................................... ........... 137 10.10 symbol counter usage ......................... ................................................... ...... 137 10.11 register description ......................... ................................................... ........... 138 11 system clock and clock options.................. .............................. 148 11.1 overview...................................... ................................................... .................. 148 11.2 clock systems and their distribution .......... ................................................... .. 148 11.3 clock sources ................................. ................................................... .............. 149 11.4 calibrated internal rc oscillator............. ................................................... ...... 150 11.5 128 khz internal oscillator ................... ................................................... ......... 151 11.6 external clock ................................ ................................................... ............... 151 11.7 transceiver crystal oscillator ................ ................................................... ....... 152 11.8 clock output buffer ........................... ................................................... ............ 153 11.9 timer/counter oscillator ...................... ................................................... ......... 153 11.10 system clock prescaler ....................... ................................................... ....... 153 11.11 register description ......................... ................................................... ........... 154 12 power management and sleep modes ................ ........................ 157 12.1 deep-sleep mode ............................... ................................................... .......... 157 12.2 avr microcontroller sleep modes ............... ................................................... . 157 12.3 power reduction register...................... ................................................... ....... 160 554 8266c-mcu wireless-08/11 ATMEGA128RFA1 12.4 minimizing power consumption .................. ................................................... .. 160 12.5 supply voltage and leakage control............ ................................................... 162 12.6 register description .......................... ................................................... ............ 168 13 system control and reset ........................ ................................... 178 13.1 resetting the avr ............................. ................................................... ............ 178 13.2 reset sources ................................. ................................................... .............. 178 13.3 internal voltage reference.................... ................................................... ........ 181 13.4 watchdog timer ................................ ................................................... ............ 182 13.5 register description .......................... ................................................... ............ 185 14 i/o-ports....................................... .................................................. 1 88 14.1 introduction.................................. ................................................... .................. 188 14.2 ports as general digital i/o.................. ................................................... ......... 189 14.3 alternate port functions...................... ................................................... .......... 193 14.4 register description .......................... ................................................... ............ 205 15 interrupts ...................................... ................................................. 21 2 15.1 interrupt vectors in ATMEGA128RFA1 ............ ................................................. 21 2 15.2 reset and interrupt vector placement .......... ................................................... 214 15.3 moving interrupts between application and boot section ............................... 217 15.4 register description .......................... ................................................... ............ 217 16 external interrupts ............................. ........................................... 219 16.1 pin change interrupt timing ................... ................................................... ...... 219 16.2 register description .......................... ................................................... ............ 220 17 8-bit timer/counter0 with pwm ................... ................................ 227 17.1 features ...................................... ................................................... .................. 227 17.2 overview...................................... ................................................... .................. 227 17.3 timer/counter clock sources ................... ................................................... .... 228 17.4 counter unit .................................. ................................................... ................ 228 17.5 output compare unit ........................... ................................................... ......... 229 17.6 compare match output unit..................... ................................................... ..... 231 17.7 modes of operation ............................ ................................................... ........... 233 17.8 timer/counter timing diagrams ................. ................................................... .. 237 17.9 register description .......................... ................................................... ............ 239 18 16-bit timer/counter (timer/counter 1, 3, 4, and 5)................... 245 18.1 features ...................................... ................................................... .................. 245 18.2 overview...................................... ................................................... .................. 245 18.3 accessing 16-bit registers.................... ................................................... ........ 247 555 8266c-mcu wireless-08/11 ATMEGA128RFA1 18.4 timer/counter clock sources ................... ................................................... .... 250 18.5 counter unit .................................. ................................................... ................ 250 18.6 input capture unit ............................ ................................................... ............. 251 18.7 output compare units.......................... ................................................... ......... 253 18.8 compare match output unit..................... ................................................... ..... 255 18.9 modes of operation ............................ ................................................... ........... 257 18.10 timer/counter timing diagrams ................ ................................................... . 265 18.11 register description ......................... ................................................... ........... 267 19 timer/counter 0, 1, 3, 4, and 5 prescaler ....... ............................. 305 19.1 internal clock source ......................... ................................................... ........... 305 19.2 prescaler reset ............................... ................................................... .............. 305 19.3 external clock source......................... ................................................... .......... 305 19.4 register description .......................... ................................................... ............ 306 20 output compare modulator (ocm1c0a).............. ....................... 308 20.1 overview...................................... ................................................... .................. 308 20.2 description................................... ................................................... .................. 308 20.3 timing example................................ ................................................... ............. 309 21 8-bit timer/counter2 with pwm and asynchronous o peration 310 21.1 features ...................................... ................................................... .................. 310 21.2 overview...................................... ................................................... .................. 310 21.3 timer/counter clock sources ................... ................................................... .... 311 21.4 counter unit .................................. ................................................... ................ 312 21.5 modes of operation ............................ ................................................... ........... 312 21.6 output compare unit ........................... ................................................... ......... 317 21.7 compare match output unit..................... ................................................... ..... 318 21.8 timer/counter timing diagrams ................. ................................................... .. 320 21.9 asynchronous operation of timer/counter2...... .............................................. 321 21.10 timer/counter prescaler ...................... ................................................... ....... 323 21.11 register description ......................... ................................................... ........... 324 22 spi- serial peripheral interface................ .................................... 331 22.1 features ...................................... ................................................... .................. 331 22.2 functional description........................ ................................................... ........... 331 22.3 ss __ pin functionality ................................ ................................................... ...... 335 22.4 register description .......................... ................................................... ............ 337 23 usart........................................... ................................................. 34 0 23.1 features ...................................... ................................................... .................. 340 556 8266c-mcu wireless-08/11 ATMEGA128RFA1 23.2 overview...................................... ................................................... .................. 340 23.3 clock generation.............................. ................................................... ............. 341 23.4 frame formats ................................. ................................................... ............. 344 23.5 usart initialization .......................... ................................................... ............ 345 23.6 data transmission ? the usart transmitter..... ............................................ 346 23.7 data reception ? the usart receiver ........... ............................................... 349 23.8 asynchronous data reception................... ................................................... ... 353 23.9 multi-processor communication mode............ ................................................. 35 6 23.10 register description ......................... ................................................... ........... 357 23.11 examples of baud rate setting ................ ................................................... .. 366 24 usart in spi mode ............................... ....................................... 369 24.1 overview...................................... ................................................... .................. 369 24.2 usart mspim vs. spi ........................... ................................................... ...... 369 24.3 spi data modes and timing ..................... ................................................... .... 370 24.4 frame formats ................................. ................................................... ............. 371 24.5 data transfer................................. ................................................... ................ 372 24.6 usart mspim register description .............. ................................................. 37 4 25 2-wire serial interface......................... .......................................... 378 25.1 features ...................................... ................................................... .................. 378 25.2 2-wire serial interface bus definition ........ ................................................... .... 378 25.3 data transfer and frame format................ ................................................... .. 379 25.4 multi-master bus systems, arbitration and sync hronization ........................... 381 25.5 overview of the twi module .................... ................................................... ..... 383 25.6 using the twi................................. ................................................... ............... 385 25.7 transmission modes ............................ ................................................... ......... 388 25.8 multi-master systems and arbitration .......... ................................................... . 401 25.9 register description .......................... ................................................... ............ 402 26 ac ? analog comparator .......................... ................................... 408 26.1 analog comparator multiplexed input........... ................................................... 408 26.2 register description .......................... ................................................... ............ 409 27 adc ? analog to digital converter............... ............................... 411 27.1 features ...................................... ................................................... .................. 411 27.2 operation..................................... ................................................... .................. 412 27.3 adc start-up.................................. ................................................... ............... 413 27.4 starting a conversion......................... ................................................... ........... 413 27.5 pre-scaling and conversion timing ............. ................................................... . 414 557 8266c-mcu wireless-08/11 ATMEGA128RFA1 27.6 changing channel or reference selection....... ............................................... 418 27.7 adc noise canceller ........................... ................................................... ......... 420 27.8 adc conversion result ......................... ................................................... ....... 424 27.9 internal temperature measurement.............. ................................................... 426 27.10 sram drt voltage measurement ................. ............................................... 427 27.11 register description ......................... ................................................... ........... 428 28 jtag interface and on-chip debug system......... ...................... 436 28.1 features ...................................... ................................................... .................. 436 28.2 overview...................................... ................................................... .................. 436 28.3 tap - test access port ........................ ................................................... ......... 437 28.4 tap controller ................................ ................................................... ............... 438 28.5 using the boundary-scan chain................. ................................................... ... 439 28.6 using the on-chip debug system ................ ................................................... . 439 28.7 on-chip debug specific jtag instructions ...... ................................................ 440 28.8 using the jtag programming capabilities....... ............................................... 440 28.9 bibliography.................................. ................................................... ................. 441 28.10 on-chip debug related register in i/o memory. ........................................... 441 29 ieee 1149.1 (jtag) boundary-scan................ ............................ 442 29.1 features ...................................... ................................................... .................. 442 29.2 system overview ............................... ................................................... ........... 442 29.3 data registers................................ ................................................... ............... 442 29.4 boundary-scan specific jtag instructions ...... ................................................ 444 29.5 boundary-scan chain........................... ................................................... ......... 445 29.6 boundary-scan related register in i/o memory.. ............................................ 448 29.7 boundary-scan description language files ...... .............................................. 449 29.8 ATMEGA128RFA1 boundary-scan order ............. ............................................ 449 30 boot loader support ? read-while-write self-prog ramming... 451 30.1 features ...................................... ................................................... .................. 451 30.2 application and boot loader flash sections .... ............................................... 451 30.3 read-while-write and no read-while-write flash sections .......................... 452 30.4 boot loader lock bits ......................... ................................................... .......... 454 30.5 addressing the flash during self-programming.. ............................................ 454 30.6 self-programming the flash.................... ................................................... ...... 455 30.7 register description .......................... ................................................... ............ 462 31 memory programming.............................. .................................... 465 31.1 program and data memory lock bits ............. ................................................. 46 5 558 8266c-mcu wireless-08/11 ATMEGA128RFA1 31.2 fuse bits..................................... ................................................... ................... 466 31.3 signature bytes ............................... ................................................... .............. 468 31.4 calibration byte .............................. ................................................... ............... 468 31.5 page size ..................................... ................................................... ................. 468 31.6 parallel programming parameters, pin mapping, and commands ................. 468 31.7 parallel programming.......................... ................................................... .......... 470 31.8 serial downloading ............................ ................................................... ........... 479 31.9 programming via the jtag interface............ ................................................... 483 32 application circuits ............................ .......................................... 495 32.1 basic application schematic ................... ................................................... ...... 495 32.2 extended feature set application schematic.... .............................................. 496 33 register summary ................................ ........................................ 498 34 instruction set summary......................... ..................................... 503 34.1 arithmetic and logic instructions ............. ................................................... ..... 503 34.2 branch instructions........................... ................................................... ............. 503 34.3 bit and bit test instructions................. ................................................... .......... 504 34.4 data transfer instructions .................... ................................................... ......... 505 34.5 mcu control instructions ...................... ................................................... ........ 506 35 electrical characteristics ...................... ....................................... 507 35.1 absolute maximum ratings...................... ................................................... ..... 507 35.2 recommended operating range................... .................................................. 5 07 35.3 digital pin characteristics ................... ................................................... .......... 507 35.4 power supply currents (rf transceiver in sleep mode)............................... 508 35.5 clock characteristics......................... ................................................... ............ 509 35.6 system and reset characteristics .............. ................................................... .. 510 35.7 power management electrical characteristics... .............................................. 510 35.8 2-wire serial interface characteristics ....... ................................................... ... 511 35.9 spi timing characteristics .................... ................................................... ........ 512 35.10 adc characteristics .......................... ................................................... .......... 514 35.11 temperature sensor characteristics ........... .................................................. 5 16 35.12 transceiver electrical characteristics ....... ................................................... .. 516 36 typical characteristics......................... ........................................ 519 36.1 supply current vs. clock speed with transceive r in sleep .......................... 519 36.2 current consumption of bandgap source and digi tal voltage regulator ....... 523 36.3 current consumption in various transceiver sta tes........................................ 523 36.4 rf measurements ............................... ................................................... .......... 525 559 8266c-mcu wireless-08/11 ATMEGA128RFA1 36.5 bod threshold................................. ................................................... ............. 527 36.6 pin driver strength ........................... ................................................... ............. 528 36.7 power-down current ............................ ................................................... ......... 531 36.8 static adc parameter ? inl and dnl ............ ................................................. 53 2 36.9 dynamic adc parameter ? enob.................. ................................................. 53 6 36.10 adc voltage reference ........................ ................................................... ...... 539 36.11 temperature sensor ........................... ................................................... ........ 539 36.12 internal oscillator speed .................... ................................................... ......... 541 36.13 programming current.......................... ................................................... ........ 543 37 ordering information ............................ ........................................ 545 38 packaging information ........................... ...................................... 546 39 errata .......................................... ................................................... 547 39.1 ATMEGA128RFA1 revision d (1.2) ................ ................................................... 547 39.2 ATMEGA128RFA1 revision c (1.1) ................ ................................................... 547 39.3 ATMEGA128RFA1 revision ab (1.0) ............... .................................................. 5 47 39.4 compiler package winavr-20090313 .............. .............................................. 547 39.5 detailed errata description ................... ................................................... ......... 547 40 revision history ................................ ............................................ 550 table of contents.................................. ............................................. 552 560 8266c-mcu wireless-08/11 ATMEGA128RFA1 disclaimer headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 product contact atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature request www.atmel.com/literature disclaimer: the information in this document is provided in co nnection with atmel products. no license, express o r implied, by estoppel or otherwise, to any intellectual property right is granted by this docu ment or in connection with the sale of atmel produc ts. except as set forth in atmel?s terms and condi tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but no t limited to, the implied warrant y of merchantability, fitness for a particular purpose, or non- infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without l imitation, damages for loss of profits, bus iness interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completene ss of the contents of this document and reserves th e right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided ot herwise, atmel products are not suitable for, and s hall not be used in, automotive applications. atmel ?s products are not intended, authorized, or warranted for use as components in applications int ended to support or sustain life. ? 2011 atmel corporation. all rights reserved . atmel?, atmel logo and combinations thereof, avr? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries . other terms and product names may be trademarks o f others. 8266c-mcu wireless-08/11 |
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